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Understanding Von Neumann Architecture

Von Neumann Architecture past paper questions

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13 views9 pages

Understanding Von Neumann Architecture

Von Neumann Architecture past paper questions

Uploaded by

siva
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Chapter 3 -Revision

Von Neumann
Architecture
1 Paige has a computer that has a central processing unit (CPU) based on the Von Neumann model
for a computer system.

(a) Identify the component within the CPU that controls the flow of data.

............................................................................................................................................. [1]

(b) Identify the component within the CPU where calculations are carried out.

............................................................................................................................................. [1]

(c) Identify the component within the CPU that stores the address of the next instruction to be
processed.

............................................................................................................................................. [1]

(d) Identify the register within the CPU that holds an instruction that has been fetched from
memory.

............................................................................................................................................. [1]

(e) Identify the register within the CPU that holds data that has been fetched from memory.

............................................................................................................................................. [1]

2 The Von Neumann model for a computer system has several components that are used in the
fetch-execute cycle.

(a) One component is main memory.

(i) Describe what is meant by main memory and how it is used in the Von Neumann model
for a computer system.

...........................................................................................................................................

...........................................................................................................................................

...........................................................................................................................................

...........................................................................................................................................

...........................................................................................................................................

..................................................................................................................................... [3]

(ii) State two other components in the Von Neumann model for a computer system.

1 ........................................................................................................................................

2 ........................................................................................................................................
[2]

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(b) Computer systems often use interrupts.

Five statements are given about interrupts.

Tick (3) to show if each statement is True or False.

True False
Statement
(3) (3)
Interrupts can be hardware based or software based
Interrupts are handled by the operating system
Interrupts allow a computer to multitask
Interrupts work out which program to give priority to
Interrupts are vital to a computer and it cannot function without them
[5]

3 The Von Neumann model for a computer system uses several components in the fetch-execute
cycle. One component that is used is the Control Unit (CU).

Identify four other components that are used in the Von Neumann model for a computer system.

1 .......................................................................................................................................................

2 .......................................................................................................................................................

3 .......................................................................................................................................................

4 .......................................................................................................................................................

[4]

4 To process an instruction, a central processing unit (CPU) goes through a cycle that has three
main stages.

Name each stage in this cycle.

Stage 1 ................................................................................

Stage 2 ................................................................................

Stage 3 ................................................................................
[3]
5 Name three different buses that are used in the fetch-execute cycle.

Bus 1 ................................................................................................................................................

Bus 2 ................................................................................................................................................

Bus 3 ................................................................................................................................................
[3]

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6 A Von Neumann model for a computer system has a central processing unit (CPU) that makes
use of registers.

(a) Identify three registers that may be used.

Register 1 .................................................................................................................................

Register 2 .................................................................................................................................

Register 3 .................................................................................................................................
[3]

(b) The CPU is responsible for processing instructions.

One stage of processing instructions is the decode stage.

(i) Identify the two other stages of processing instructions.

Stage 1 ..............................................................................................................................

Stage 2 ..............................................................................................................................
[2]

(ii) Identify the component of the CPU that is responsible for decoding instructions.

..................................................................................................................................... [1]

7 Vanessa writes a paragraph as an answer to an examination question about the central processing
unit (CPU).

Use the list given to complete Vanessa’s answer by inserting the correct six missing terms.
Not all terms will be used.

• Components
• Data
• Decoded
• Executed
• Fetched
• Instructions
• RAM
• ROM
• Secondary storage

The CPU processes ........................................................ and ........................................................ .

An instruction is ........................................................ from ........................................................

into the CPU where it is then ........................................................ . Once this has taken place the

instruction is then ........................................................ .


[6]

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8 Kelvin correctly answers an examination question about the Von Neumann model.

Eight different terms have been removed from his answer.

Complete the sentences in Kelvin’s answer, using the list given.

Not all items in the list need to be used.

• accumulator (ACC)
• address bus
• arithmetic logic unit (ALU)
• control unit (CU)
• data bus
• executed
• fetches
• immediate access store (IAS)
• memory address register (MAR)
• memory data register (MDR)
• program counter (PC)
• saved
• transmits

The central processing unit (CPU) ....................................................................................

the data and instructions needed and stores them in the

.................................................................................... to wait to be processed.

The .................................................................................... holds the address of the next

instruction. This address is sent to the .................................................................................... .

The data from this address is sent to the .................................................................................... .

The instruction can then be decoded and .................................................................................... .

Any calculations that are carried out on the data are done by the

.................................................................................... . During calculations, the data is temporarily

held in a register called the .................................................................................... .


[8]

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9 Six components of the Von Neumann model for a computer system and six descriptions are given.

Draw a line to match each component to the most suitable description.

Component Description

Immediate Holds data and instructions when they are


access store loaded from main memory and are waiting
(IAS) to be processed.

Holds data temporarily that is currently


Register
being used in a calculation.

Control unit Holds data or instructions temporarily


(CU) when they are being processed.

Accumulator Manages the flow of data and interaction


(ACC) between the components of the processor.

Arithmetic logic
Carries out the calculations on data.
unit (ALU)

Pathway for transmitting data and


Bus
instructions.
[5]

10 Signals are sent to and from the components of a processor using buses.

Identify and describe the purpose of two different buses.

Bus 1 ....................................................................

Purpose ............................................................................................................................................

..........................................................................................................................................................

..........................................................................................................................................................

..........................................................................................................................................................

Bus 2 ....................................................................

Purpose ............................................................................................................................................

..........................................................................................................................................................

..........................................................................................................................................................

..........................................................................................................................................................

[6]
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11 (a) One of the key features of von Neumann computer architecture is the use of buses.

Three buses and three descriptions are shown below.

Draw a line to connect each bus to its correct description.


Bus Description

this bus carries signals used


address bus to coordinate the computer’s
activities

this bi-directional bus is used


to exchange data between
control bus
processor, memory and input/
output devices

this uni-directional bus carries


signals relating to memory
data bus
addresses between processor
and memory
[2]

(b) The seven stages in a von Neumann fetch-execute cycle are shown in the table below.

Put each stage in the correct sequence by writing the numbers 1 to 7 in the right hand column.
The first one has been done for you.

Sequence
Stage
number
the instruction is then copied from the memory location contained
in the MAR (memory address register) and is placed in the MDR
(memory data register)

the instruction is finally decoded and is then executed

the PC (program counter) contains the address of the next instruction


to be fetched 1
the entire instruction is then copied from the MDR (memory data
register) and placed in the CIR (current instruction register)

the address contained in the PC (program counter) is copied to the


MAR (memory address register) via the address bus

the address part of the instruction, if any, is placed in the MAR


(memory address register)

the value in the PC (program counter) is then incremented so that it


points to the next instruction to be fetched

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[6]
12 A section of computer memory is shown below:

Address Contents
1000 0000 0110 1110
1000 0001 0101 0001
1000 0010 1000 1101
1000 0011 1000 1100

1000 1100
1000 1101
1000 1110
1000 1111

(a) (i) The contents of memory location 1000 0001 are to be read.

Show the contents of the Memory Address Register (MAR) and the Memory Data
Register (MDR) during this read operation:

MAR

MDR

[2]

(ii) The value 0111 1001 is to be written into memory location 1000 1110.

Show the contents of the MAR and MDR during this write operation:

MAR

MDR

[2]

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(iii) Show any changes to the computer memory following the read and write operations in
part (a)(i) and part (a)(ii).

Address Contents
1000 0000 0110 1110
1000 0001 0101 0001
1000 0010 1000 1101
1000 0011 1000 1100

1000 1100
1000 1101
1000 1110
1000 1111
[1]

(b) Name three other registers used in computers.

1 ................................................................................................................................................

2 ................................................................................................................................................

3 ................................................................................................................................................
[3]

(c) The control unit is part of a computer system.

What is the function of the control unit?

...................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

.............................................................................................................................................. [3]

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Common questions

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The stages of the fetch-execute cycle—fetch, decode, and execute—support sequential instruction processing by organizing the orderly flow of instruction handling. In the fetch stage, the CPU retrieves the next instruction from memory, allowing for sequential execution as indicated by the Program Counter incrementing. During the decode stage, it translates the instruction to understand the required operation, facilitating preparation for the execute phase. Finally, during the execute stage, the CPU performs the actual operation. This structured process ensures that instructions are handled in a precise order, optimizing execution and maintaining system predictability .

The fetch-execute cycle is a fundamental CPU process involving three stages: fetch, decode, and execute. During the fetch stage, the processor retrieves an instruction from memory at the address indicated by the Program Counter (PC) and places it in the Current Instruction Register (CIR). In the decode stage, the instruction is translated into signals that can trigger other operations. Finally, during the execute stage, the instruction's command is performed, which could involve arithmetic operations, memory access, or device communication, utilizing various components like the ALU and control unit. This cycle is essential for the CPU to process instructions sequentially .

The Control Unit (CU) manages the flow of data and the interaction between the components of the processor. It interprets instructions from the program stored in memory and translates them into control signals that execute or manage the operations within the CPU. During the fetch-execute cycle, it coordinates with the Arithmetic Logic Unit (ALU) for executing operations, manages data flow through various buses, and controls the sequence of instruction execution. It ensures correct operation by managing the timings and signals that control the movement of data within the CPU and between the CPU and other hardware components .

The Memory Address Register (MAR) holds the address of a memory location where data needs to be read from or written to. During memory operations, the address bus conveys this address to memory. The Memory Data Register (MDR) holds the actual data that is being transferred to or from a specified memory location, facilitating the exchange of data via the data bus. Together, they play a crucial role in interfacing between the CPU and memory, ensuring that data retrieval and storage operations are correctly aligned with memory addresses .

The decode stage of the instruction cycle facilitates the execution of complex instructions by translating encoded instructions into control signals that direct the subsequent processes. It involves interpreting the instruction format and generating the necessary control signals required for the CPU components to execute tasks. This stage allows for the breakdown of complex instructions into simpler operational commands that can be executed sequentially or in parallel, depending on the CPU architecture, effectively managing resources and operational overlaps. This enables the handling of complex and compound operations by directing specific actions to various CPU units like the ALU, registers, and memory interface, crucial for sophisticated computing tasks .

Registers significantly enhance CPU processing speed and efficiency by providing high-speed storage locations within the CPU for immediate access to instruction data. This allows the processor to retrieve, store, and manipulate data without the latency of accessing the main memory, which is considerably slower. The use of registers, such as the Accumulator (ACC), Program Counter (PC), and others, eliminates the bottleneck associated with repetitive memory operations, thereby improving overall throughput and processing efficiency of the CPU .

Interrupts enhance CPU efficiency by allowing the processor to respond immediately to high-priority tasks, thus reducing idle time and increasing overall system responsiveness. They enable multitasking by permitting the system to pause the execution of a running task, address an urgent task, and then resume the original task. This process is crucial for maintaining system performance and responsiveness, allowing essential and time-sensitive operations to receive processor attention without significant delays or backlog creation, which otherwise would degrade performance in single-threaded processing scenarios .

In the Von Neumann architecture, the data bus is a bi-directional bus that moves data between the processor, memory, and input/output devices. The address bus carries information about where data should be sent or retrieved, carrying signals that specify memory addresses from the processor to memory or other devices; it is unidirectional. The control bus carries control signals that coordinate various activities across the computer system, such as read or write signals to memory. Each bus serves a distinct function in managing data flow and operation coordination within the computing system .

The Immediate Access Store (IAS) is used to hold data and instructions that have been fetched from main memory and are ready to be used by the CPU. It serves as a temporary storage area within the CPU for data and instructions that need to be accessed quickly, facilitating faster processing since the CPU does not need to repeatedly access slower main memory during the execution of instructions. By storing frequently accessed data, it speeds up the processing cycle within the Von Neumann architecture .

Buses are crucial for integrating the CPU with peripheral devices in the Von Neumann model by providing standardized pathways for data, address, and control signals. The data bus facilitates data transfer between the CPU and devices, allowing for efficient data sharing. The address bus ensures that communication is accurately targeted by transmitting address information to memory and I/O interfaces. The control bus helps synchronize data transfers, manage command signals like bus arbitration, and enforce access protocols, thereby maintaining system coherence and operational integrity. These buses enable seamless interaction and coordination between the CPU and peripheral components, essential for system functionality and multitasking .

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