// Code your design here
//AND GATE using structural modelling
module and_gate_s(a,b,y);
input a,b;
output y;
and(y,a,b);
endmodule
// AND Gate Test Bench
module and_gate_tb;
reg a,b;
wire y;
and_gate_s uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design here
//AND GATE using data flow modelling
module and_gate_d(a,b,y);
input a,b;
output y;
assign y=a&b;
endmodule
// AND Gate Test Bench
module and_gate_tb;
reg a,b;
wire y;
and_gate_d uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design here
//AND GATE using behavioral modelling
module and_gate_b(a,b,y);
input a,b;
output reg y;
always @(a,b)
y=a&b;
endmodule
// Code your testbench here
// or browse Examples
// AND Gate Test Bench
module and_gate_tb;
reg a,b;
wire y;
and_gate_b uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//OR Gate using strutural modelling
module or_gate_s(a,b,y);
input a,b;
output y;
or(y,a,b);
endmodule
// Code your testbench here
// or browse Examples
// OR Gate Test Bench
module or_gate_tb;
reg a,b;
wire y;
or_gate_s uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//OR Gate using data flow modelling
module or_gate_d(a,b,y);
input a,b;
output y;
assign y=a|b;
endmodule
// Code your testbench here
// or browse Examples
// OR Gate Test Bench
module or_gate_tb;
reg a,b;
wire y;
or_gate_d uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
module or_gate_b(a,b,y);
input a,b;
output reg y;
always @(a,b)
y=a | b;
endmodule
// Code your testbench here
// or browse Examples
// OR Gate Test Bench
module or_gate_tb;
reg a,b;
wire y;
or_gate_b uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//NAND Gate using structural modelling
module nand_gate_s(a,b,y);
input a,b;
output y;
nand(y,a,b);
endmodule
// Code your testbench here
// or browse Examples
// NAND Gate Test Bench
module nand_gate_tb;
reg a,b;
wire y;
nand_gate_s uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//NAND Gate using data flow modelling
module nand_gate_d(a,b,y);
input a,b;
output reg y;
assign y=~(a&b);
endmodule
// Code your testbench here
// or browse Examples
// NAND Gate Test Bench
module nand_gate_tb;
reg a,b;
wire y;
nand_gate_d uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//NAND Gate using behavioural modelling
module nand_gate_b(a,b,y);
input a,b;
output reg y;
always @(a,b)
y=~(a&b);
endmodule
// Code your testbench here
// or browse Examples
// NAND Gate Test Bench
module nand_gate_tb;
reg a,b;
wire y;
nand_gate_b uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
End
Endmodule
// Code your design
//NOR GATE USING behavioural modelling
module nor_gate_b(a,b,y);
input a,b;
output reg y;
always @(a,b)
y=~(a|b);
endmodule
// Code your testbench here
// or browse Examples
// NOR Gate Test Bench
module nor_gate_tb;
reg a,b;
wire y;
nor_gate_b uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//NOR GATE USING data flow modelling
module nor_gate_d(a,b,y);
input a,b;
output y;
assign y=~(a|b);
endmodule
// Code your testbench here
// or browse Examples
// NOR Gate Test Bench
module nor_gate_tb;
reg a,b;
wire y;
nor_gate_d uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//NOR GATE USING structural modelling
module nor_gate_s(a,b,y);
input a,b;
output y;
nor(y,a,b);
endmodule
// Code your testbench here
// or browse Examples
// NOR Gate Test Bench
module nor_gate_tb;
reg a,b;
wire y;
nor_gate_s uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//XOR GATE USING structural modelling
module xor_gate_s(a,b,y);
input a,b;
output y;
xor(y,a,b);
endmodule
// Code your testbench here
// or browse Examples
// XOR Gate Test Bench
module nor_gate_tb;
reg a,b;
wire y;
xor_gate_s uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//XOR GATE USING data flow modelling
module xor_gate_d(a,b,y);
input a,b;
output reg y;
assign y=a^b;
endmodule
// Code your testbench here
// or browse Examples
// XOR Gate Test Bench
module nor_gate_tb;
reg a,b;
wire y;
xor_gate_d uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//XOR GATE USING behavioural modelling
module xor_gate_b(a,b,y);
input a,b;
output reg y;
always @(a,b)
y=a^b;
endmodule
// Code your testbench here
// or browse Examples
// XOR Gate Test Bench
module nor_gate_tb;
reg a,b;
wire y;
xor_gate_b uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//EXNOR GATE USING behavioural modelling
module exnor_gate_b(a,b,y);
input a,b;
output reg y;
always @(a,b)
y=~(a^b);
endmodule
// Code your testbench here
// or browse Examples
// EXNOR Gate Test Bench
module exnor_gate_tb;
reg a,b;
wire y;
exnor_gate_b uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//EXNOR GATE USING data flow modelling
module exnor_gate_d(a,b,y);
input a,b;
output reg y;
assign y=~(a^b);
endmodule
// Code your testbench here
// or browse Examples
// EXNOR Gate Test Bench
module exnor_gate_tb;
reg a,b;
wire y;
exnor_gate_d uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule
// Code your design
//EXNOR GATE USING structural modelling
module exnor_gate_s(a,b,y);
input a,b;
output y;
xnor(y,a,b);
endmodule
// Code your testbench here
// or browse Examples
// EXNOR Gate Test Bench
module exnor_gate_tb;
reg a,b;
wire y;
exnor_gate_s uut(a,b,y);
initial begin
//dump waves
$dumpfile("[Link]");
$dumpvars(1);
a=0;b=0;
#10
a=0;b=1;
#10
a=1;b=0;
#10
a=1;b=1;
#10
$finish();
end
endmodule