Communication and Protocols

Introduction to Communications
• Links connect one computer to another.
• The link is implemented with a technology, which follow a
protocol.
• The protocol is a set of rules that determine how information is
communicated.
Introduction to Communications
• Simplex communication is defined as the ability to communicate
in only one direction.
• Half-duplex communication allows for communication in both
directions, but only one direction at time.
• Full-duplex communication can communicate in both directions
simultaneously.
 I/O Synchronization
• A performance measure is a quantitative metric that the goodness of
the system.
• Latency is the time between when the I/O device indicated service
is required and the time when service is initiated.
• Latency includes hardware delays in the digital hardware plus
computer software delays.
• For an input device, software latency (or software response time) is
the time between new input data ready and the software reading the
data. For an output device, latency is the delay from output device
idle and the software giving the device new data to output.
• Software latency in this case is the time between when the ADC
conversion is supposed to be started, and when it is actually started.
 I/O Synchronization
• The microcomputer-based control system also employs periodic software
processing. Similar to the data acquisition system, the latency in a control
system is the time between when the control software is supposed to be run,
and when it is actually run.
• A real-time system is one that can guarantee a worst case latency. In other
words, the software response time is small and bounded. Furthermore, this
bound is small enough to satisfy overall specification of the system, such as
no lost data.
• Throughput or bandwidth is the maximum data flow in bytes/second that can
be processed by the system.
• Sometimes the bandwidth is limited by the I/O device, while other times it is
limited by computer software. Bandwidth can be reported as an overall
average or a short-term maximum. Priority determines the order of service
when two or more requests are made simultaneously. Priority also determines
if a high-priority request should be allowed to suspend a low priority request
that is currently being processed. We may also wish to implement equal
priority, so that no one device can monopolize the computer. In some
computer literature, the term "soft-real-time" is used to describe a system that
supports priority.
 I/O Synchronization
• The purpose of our interface is to allow the microcontroller to
interact with its external I/O device, see Figure below. One of the
choices the designer must make is the algorithm for how the software
synchronizes with the hardware.
• There are five mechanisms to synchronize the microcontroller with
the I/O device. Each mechanism synchronizes the I/O data transfer to
the busy to done transition.
• Blind cycle is a method where the software simply waits a fixed
amount of time and assumes the I/O will complete before that fixed
delay has elapsed. For an input device, the software triggers (starts)
the external input hardware, waits a specified time, then reads data
from device. Blind cycle synchronization for an input device is
shown on the left part of Figure above.
• For an output device, shown on the left part of Figure, the
software writes data to the output device, triggers (starts) the
device, then waits a specified time.
• We call this method blind, because there is no status information
about the I/O device reported to the software.
• It is appropriate to use this method in situations where the I/O
speed is short and predictable.
• We can ask the LCD to display an ASCII character, wait 37 µs,
and then we are sure the operation is complete.
• This method works because the LCD speed is short and
predictable. Another good example of blind-cycle synchronization
is spinning a stepper motor.
• If we repeat this 8-step sequence over and over 1) output a 0x05,
2) wait 1ms, 3) output a 0x06, 4) wait 1ms, 5) output a 0x0A, 6)
wait 1ms, 7) output a 0x09, 8) wait 1ms, the motor will spin at a
constant speed.
• Busy Wait is a software loop that checks the I/O status waiting for
the done state.
• For an input device, the software waits until the input device has
new data, and then reads it from the input device.
• For an output device, the software writes data, triggers the output
device then waits until the device is finished.
• Another approach to output device interfacing is for the software
to wait until the output device has finished the previous output,
write data, and then trigger the device.
• Busy-wait synchronization will be used in situations where the
software system is relatively simple and real-time response is not
important. The UART software use busy-wait synchronization.
 Interrupt
• An interrupt uses hardware to cause special software execution.
• With an input device, the hardware will request an interrupt when
input device has new data.
• The software interrupt service will read from the input device and
save in global RAM.
• With an output device, the hardware will request an interrupt when
the output device is idle.
• The software interrupt service will get data from a global structure,
and then write to the device.
• Sometimes we configure the hardware timer to request interrupts
on a periodic basis. The software interrupt service will perform a
special function. A data acquisition system needs to read the ADC
at a regular rate. Interrupt synchronization will be used in
situations where the system is fairly complex (e.g., a lot of I/O
devices) or when real-time response is important.
 Interrupt
• One can think of the hardware being in one of three states. The
idle state is when the device is disabled or inactive. No I/O
occurs in the idle state. When active (not idle) the hardware
toggles between the busy and ready states. The interface
includes a flag specifying either busy (0) or ready (1) status.
Hardware-software synchronization revolves around this flag:
• The hardware will set the flag when the hardware component
is complete.
• The software can read the flag to determine if the device is
busy or ready.
• The software can clear the flag, signifying the software
component is complete.
• This flag serves as the hardware triggering event for an
interrupt.
• For an input device, a status flag is set when new input data is
available.
• Once the software recognizes the input device has new data, it
will read the data and ask the input device to create more data.
• It is the busy to ready state transition that signals to the software
that the hardware task is complete, and now software service is
required.
• When the hardware is in the ready state the I/O transaction is
complete. Often the simple process of reading the data will clear
the flag and request another input.
• The problem with I/O devices is that they are usually much
slower than software execution.
• Therefore, we need synchronization, which is the process of the
hardware and software waiting for each other in a manner such
that data is properly transmitted.
• A way to visualize this synchronization is to draw a state versus
time plot of the activities of the hardware and software.
• For an input device, the software begins by waiting for new input.
When the input device is busy it is in the process of creating new
input.
• When the input device is ready, new data is available.
• When the input device makes the transition from busy to ready, it
releases the software to go forward. In a similar way, when the
software accepts the input, it can release the input device
hardware.
• The arrows in Figure represent the synchronizing events. In this
example, the time for the software to read and process the data is less
than the time for the input device to create new input. This situation
is called I/O bound, meaning the bandwidth is limited by the speed
of the I/O hardware.
•
• If the input device were faster than the software, then the
software waiting time would be zero.
• This situation is called CPU bound (meaning the bandwidth is
limited by the speed of the executing software).
• In real systems the bandwidth depends on both the hardware
and the software.
• Another characteristic of real systems is the data can vary over
time, like car traffic arriving and leaving a road intersection.
• In other words, the same I/O channel can sometimes be I/O
bound, but at other times the channel could be CPU bound.
• The busy-wait method is classified as unbuffered because the
hardware and software must wait for each other during the
transmission of each piece of data.
• The interrupt solution is classified as buffered, because the
system allows the input device to run continuously, filling a
FIFO with data as fast as it can.
• In the same way, the software can empty the buffer whenever it
is ready and whenever there is data in the buffer.
• The buffering used in an interrupt interface may be a hardware
FIFO, a software FIFO, or both hardware and software FIFOs.
We will see the FIFO queues will allow the I/O interface to
operate during both situations: I/O bound and CPU bound.
• For an output device, a status flag is set when the output is idle and
ready to accept more data.
• Once the software recognizes the output is idle, it gives the output
device another piece of data to output. It will be important to make
sure the software clears the flag each time new output is started.
• Figure contains a state versus time plot of the activities of the
output device hardware and software.
• For an output device, the software begins by generating data then
sending it to the output device.
• When the output device is busy it is processing the data.
• Normally when the software writes data to an output port, that only
starts the output process.
• The time it takes an output device to process data is usually longer
than the software execution time. When the output device is done, it is
ready for new data.
• When the output device makes the transition from busy to ready, it
releases the software to go forward.
• In a similar way, when the software writes data to the output, it
releases the output device hardware.
• The output interface illustrated in Figure is also I/O bound because the
time for the output device to process data is longer than the time for
the software to generate and write it. Again, I/O bound means the
bandwidth is limited by the speed of the I/O hardware.
• The busy-wait solution for this output interface is also unbuffered,
because when the hardware is done, it will wait for the software and
after the software generates data, it waits for the hardware.
• On the other hand, the interrupt solution ( is buffered, because the
system allows the software to run continuously, filling a FIFO as fast
as it wishes.
• In the same way, the hardware can empty the buffer whenever it is
ready and whenever there is data in the FIFO. Again, FIFO queues
allow the I/O interface to operate during both situations: I/O bound
and CPU bound.
• On some systems an interrupt will be generated on a hardware failure.
Examples include power failure, temperature too high, memory failure,
and mechanical tampering of secure systems.
• Usually, these events are extremely important and require immediate
attention.
• The Cortex™-M processor will execute special software (fault) when
it tries to execute an illegal instruction, access an illegal memory
location, or attempt an illegal I/O operation.
 Port
A port- a device
1. to receive the bytes from external peripheral(s) [or device(s) or
processor(s) or controllers] for reading them later using instructions
executed on the processor or
2. to send the bytes to external peripheral or device or processor using
instructions executed on processor
 Ports
• Connects to the processor using address decoder and system buses
Processor uses the addresses Port-Register addresses for
programming the port functions or modes, reading port status and for
writing or reading bytes. Port-Buffer addresses
 Examples of Port
• Examples
• SI serial interface in 8051
• SPI serial peripheral interface in 68HC11
• PPI parallel peripheral interface 8255
• Ports P0, P1, P2 and P3 in 8051 or PA, PB, PC and PD in
68HC11
• COM1 and COM2 ports in an IBM PC
• Sybchronus and Asynchronus
 Synchronus Serial Data
Communication
• Inter-processor data transfer, reading from CD or hard disk, audio
input, video input, dial tone, network input, transceiver input, scanner
input, remote controller input, serial I/O bus input, writing to flash
memory using SDIO (Secure Data Association IO based card)
 Synchronu serial Data
• The sender along with the serial bits also sends the clock pulses
SCLK (serial clock) to the receiver port pin.
• The port synchronizes the serial data input bits with clock bits. Each
bit in each byte as well as each byte in synchronization
• Synchronization means separation by a constant interval or phase
difference.
• If clock period = T, then each byte at the port is received at input in
period = 8T.
• The bytes are received at constant rates. Each byte at input port
separates by 8T and data transfer rate for the serial line bits is (1/T) bps.
[1bps = 1 bit per s]
Serial Data and Clock Pulse Inputs
• On same input line- when clock pulses either encode or modulate
serial data input bits suitably. Receiver detects the clock pulses and
receives data bits after decoding or demodulating.
• On separate input line- When a separate SCLK input is sent, the
receiver detects at the middle or + ve edge or –ve edge of the clock
pulses that whether the data-input is 1 or 0 and saves the bits in an
8-bit shift register. The processing element at the port (peripheral)
saves the byte at a port register from where the microprocessor
reads the byte.
 Master output slave input (MOSI) and Master
input slave output (MISO)

• MOSI when the SCLK is sent from the sender to the receiver and
slave is forced to synchronize sent inputs from the master as per the
inputs from master clock.
• MISO when the SCLK is sent to the sender (slave) from the receiver
(master) and slave is forced to synchronize for sending the inputs to
master as per the master clock outputs.
• Synchronous serial input is used for inter_x0002_processor
transfers, audio inputs and streaming data inputs.
 Example Synchronous Serial Output

• Inter-processor data transfer, multiprocessor communication,

writing to CD or hard disk, audio Input/output, video Input/output,
dialer output, network device output, remote TV Control,
transceiver output, and serial I/O bus output or writing to flash
memory using SDIO
 Synchronous Serial Output
• Each bit in each byte sent in synchronization with a clock.
• Bytes sent at constant rates. If clock period = T, then data transfer
rate is (1/T) bps.
• Sender either sends the clock pulses at SCLK pin or sends the
serial data output and clock pulse-input through same output line
with clock pulses either suitably modulate or encode the serial
output bits.
 Synchronous serial output using
shift register
• The processing element at the port (peripheral) sends the byte
through a shift register at the port to where the microprocessor
writes the byte.
• Synchronous serial output is used for inter_x0002_processor
transfers, audio outputs and streaming data outputs.
 Interrupt Synchronization
• Interrupt synchronization is required when the software in a real-time
system must respond to hardware events within a prescribed time.
• Given a change in input, it is not only necessary to get the correct
response, but it will be necessary to get the correct response at the
correct time.
• To illustrate the need for interrupts, consider a keyboard interface
where the time between new keyboard inputs might be as small as
10ms.
• In this situation, the software latency is the time from when the new
keyboard input is ready until the time the software reads the new data.
• In order to prevent loss of data in this case, the software latency must
be less than 10ms.
• We can implement real-time software using busy-wait polling only
when the size and complexity of the system is very small
 Interrupt Synchronization
• Interrupts are important for real-time systems because they provide a
mechanism to guarantee an upper bound on the software response time.
• Interrupts also give us a way to respond to infrequent but important
events.
• Alarm conditions like low battery power and error conditions can be
handled with interrupts.
• Periodic interrupts, generated by the timer at a regular rate, will be
necessary to implement data acquisition and control systems.
• An interrupt is the automatic transfer of software execution in response
to a hardware event that is asynchronous with the current software
execution.
• This hardware event is called a trigger. The hardware event can either
be a busy to ready transition in an external I/O device (like the UART
input/output) or an internal event (like bus fault, memory fault,or a
periodic timer.)
 Interrupt Synchronization
• When the hardware needs service, signified by a busy to ready state
transition, it will request an interrupt by setting its trigger flag.
• A thread is defined as the path of action of software as it executes.
The execution of the interrupt service routine is called a background
thread.
• This thread is created by the hardware interrupt request and is
killed when the interrupt service routine returns from interrupt (e.g.,
executing a BX LR )
• A new thread is created for each interrupt request. It is important to
consider each individual request as a separate thread because local
variables and registers used in the interrupt service routine are
unique and separate from one interrupt event to the next interrupt.
 Interrupt Synchronization
• In a multithreaded system, we consider the threads as cooperating to
perform an overall task.
• Consequently we will develop ways for the threads to communicate
(e.g., FIFO) and synchronize with each other.
• Most embedded systems have a single common overall goal.
• On the other hand, general-purpose computers can have multiple
unrelated functions to perform.
• A process is also defined as the action of software as it executes.
• Processes do not necessarily cooperate towards a common shared
goal. Threads share access to I/O devices, system resources, and
global variables, while processes have separate global variables and
system resources.
• Processes do not share I/O devices.
Interfacing
 Serial and Parallel Port Interfacing
• I/O interfacing is connected to serial and parallel ports.
• It can be used to interface external devices to the
microcontroller such as GPS, DAC, LCD,OLED, and ADC
devices.
• Various I/O devices such as keyboards, optical sensors,
relays, solenoids,
• DC motors, and stepper motors will be interfaced. In
addition, the pulse width modulation will beused when
interfacing DC motors so that the software can control
power delivered to the motor.
• UART is popular serial Interface
Universal Asynchronous
Receiver-Transmitter
(UART)
 Kudlick Classroom

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lectern

Indicates a “null-modem” PC-to-PC serial cable connection

PC-to-PC communications

student student
workstation workstation

KVM cable KVM cable

rackmount rackmount
PC system ‘null-modem’ serial cable PC system

ethernet cables
 UART Histrory
• Original purpose of the UART was for PCs
to communicate via the telephone network
• Telephones were for voice communication
(analog signals) whereas computers need
so exchange discrete data (digital signals)
• Special ‘communication equipment’ was
needed for doing the signal conversions
(i.e. a modulator/demodulator, or modem)
 UART
• Universal Asynchronous Receiver/Transmitter
(UART) allows the microcontroller to communicate
with devices such as other computers, printers,
input sensors, and LCDs.
• Serial transmission involves sending one bit at a
time, such that the data is spread out over time.
• The total number of bits transmitted per second is
called the baud rate.
• The reciprocal of the baud rate is the bit time,
which is the time to send one bit.
• TM4C123 has 4 UART
 Tx and Rx
• The UART has a transmission engine, and
also a reception engine (they can operate
simultaneously)
• Software controls the UART’s operations
by accessing several registers, using the
CPU’s input and output instructions
• A little history is needed for understanding
some of the UART’s terminology
 Serial data-transmission
The Transmitter Holding Register (8-bits) Software outputs a byte
of data to the THR
0 1 1 0 0 0 0 1
The bits are immediately
copied into an internal
‘shift’-register

The bits are shifted out,

one-at-a-time, in sync
with a clock-pulse

0 1 1 0 0 0 0 1 1-0-1-1-0-0-0-0-1-0
The transmitter’s internal ‘shift’ register data-bits

stop start
clock clock-pulses bit bit
trigger bit-shifts
 Serial data reception
input voltage

clock
clock-pulses trigger
voltage-sampling
and bit-shifts
at regular intervals The receiver’s internal ‘shift’ register

1-0-1-1-0-0-0-0-1-0 0 1 1 0 0 0 0 1
data-bits

stop start
bit bit

Software can input

the received byte
0 1 1 0 0 0 0 1
from the RBR
The Receiver Buffer Register (8-bits)
 UART
• Each UART will have a baud rate control register, which we use to
select the transmission rate.
• Each device is capable of creating its own serial clock with a
transmission frequency approximately equal to the serial clock in the
computer with which it is communicating.
• A frame is the smallest complete unit of serial transmission a single
frame, which includes a start bit (which is 0), 8 bits of data (least
significant bit first), and a stop bit (which is 1).
• There is always only one start bit, but the Stellaris ® and Tiva ®
UARTs allow us to select the 5 to 8 data bits and 1 or 2 stop bits.
• The UART can add even, odd, or no parity bit
 UART
• Typical protocol of 1 start bit, 8 data bits, no parity, and 1 stop bit.
• This protocol is used for both transmitting and receiving.
• The information rate, or bandwidth, is defined as the amount of data
or useful information transmitted per second.
• From Figure show that 10 bits are sent for every byte of usual data.
Therefore, the bandwidth of the serial channel (in bytes/second) is
the baud rate (in bits/sec) divided by 10.

• If you change the bus clock frequency without changing the baud
rate register, the UART will operate at an incorrect baud rate.
Asychnronus Communication Tx
• The transmitter portion of the UART includes a data output pin.
• The transmitter has a 16-element FIFO and a 10-bit shift register,
which cannot be directly accessed by the programmer (Figure 8.5).
• The FIFO and shift register in the transmitter are separate from the
FIFO and shift register associated with the receiver
 Asychnronus Communication
• To output data using the UART, the software will first check to
make sure the transmit FIFO is not full (it will wait if TXFFis 1)
and then write to the transmit data register (e.g., UART0_DR_R ).
• The bits are shifted out in this order: start, b0, b1, b2, b3, b4, b5, b6
, b7, and then stop, where b0 is the LSB and b7is the MSB.
• The transmit data register is write only, which means the software
can write to it (to start a new transmission) but cannot read from it.
• The transmit and receive data registers are two separate registers.
 Asychnronus Communication
• When a new byte is written to UART0_DR_R , it is put into the
transmit FIFO. Byte by byte, the UART gets data from the FIFO
and loads them into the 10-bit transmit shift register.
• The 10-bit shift register includes a start bit, 8 data bits, and 1 stop
bit.
• Then, the frame is shifted out one bit at a time at a rate specified by
the baud rate register.
• If there are already data in the FIFO or in the shift register when the
UART0_DR_R is written, the new frame will wait until the
previous frames have been transmitted, before it too is transmitted.
• The FIFO guarantees the data are transmitted in the order they were
written.
 Asychnronus Communication
• The serial port hardware is actually controlled by a clock that is 16
times faster than the baud rate, referred to in the datasheet as
Baud16.
• When the data are being shifted out, the digital hardware in the
UART counts 16 times in between changes to the U0Tx output line.
• The software can actually write 16 bytes to the UART0_DR_R ,
and the hardware will send them all one at a time in the proper
order.
• This FIFO reduces the software response time requirements of the
operating system to service the serial port hardware
 Receiver UART
• Receiving data frames is a little trickier than transmission because
we have to synchronize the receive shift register with the
incoming data.
• The receiver portion of the UART includes a U0Rx data input pin
with digital logic levels.
• At the input of the microcontroller, true is 3.3V and false is 0V.
• There is also a 16-element FIFO and a 10-bit shift register, which
cannot be directly accessed by the programmer (Figure 8.6).
 Receiver UART

• There are six status bits generated by receiver activity.

• The Receive FIFO empty flag, RXFE, is clear when new input
data are in the receive FIFO.
• When the software reads from UART0_DR_R , data are removed
from the FIFO.
• When the FIFO becomes empty, the RXFE flag will be set,
meaning there are no more input data.
• There are other flags associated with the receiver. There is a
Receive FIFO full flag RXFF, which is set when the FIFO is full.
• There are four status bits associated with each byte of data. For
this reason, the receive FIFO is 12 bits wide.
 Receiver UART
• The overrun error, OE, is set when input data are lost because the
FIFO is full and more input frames are arriving at the receiver. An
overrun error is caused when the receiver interface latency is too
large.
• The break error, BE, is set when the input is held low for more than
a frame.
• The PE bit is set on a parity error. Because the error rate is so low,
most systems do not implement parity.
• The framing error, FE, is set when the stop bit is incorrect. Framing
errors are probably caused by a mismatch in baud rate.
 Receiver UART
• The receiver waits for a start bit, then shifts in 10 bits of data one at a
time from the U0Rx line.
• The internal Baud16 clock is 16 times faster than the baud rate. After
the 1 to 0 edge, the receiver waits 8 Baud16 clocks and samples the
start bit.
• Every 16 Baud16 clocks it samples another bit until it reaches the
stop bit.
• The UART needs an internal clock faster than the baud rate so it can
wait the half a bit time between the 1 to 0 edge beginning the start bit
and the middle of the bit window needed for sampling.
• The start and stop bits are removed (checked for framing errors), the
8 bits of data and 4 bits of status are put into the receive FIFO.
• The FIFO implements hardware buffering so data can be safely
stored if the software is performing other tasks.
 Obervation for Rx
• If the receiving UART device has a baud rate mismatch of more
than 5%, then a framing error can occur when the stop bit is
incorrectly captured.
• An overrun occurs when there are 16 elements in the receive FIFO,
and a 17th frame comes into the receiver.
• The latency of a UART receiver is the delay between the time when
new data arrives in the receiver (RXFE=0) and the time the
software reads the data register.
• If the latency is always less so overrun will never occur.
 UART Details
• To activate a UART you will need to turn on the UART clock in the
SYSCTL_RCGCUART_R register.
• Turn on the clock for the digital port in the SYSCTL_RCGCGPIO_R
register.
• Enable the transmit and receive pins as digital signals. The alternative
function for these pins must also be selected.
• The status of the two FIFOs can be seen in the UART0_FR_R register.
• The BUSY flag is set while the transmitter still has unsent bits, even if
the transmitter is disabled.
• It will become zero when the transmit FIFO is empty and the last stop
bit has been sent.
 UART Details
• The UART0_CTL_R control register contains the bits that turn on the
UART.
• TXE is the Transmitter Enable bit, and RXE is the Receiver Enable bit
• We set TXE, RXE, and UARTEN equal to 1 in order to activate the
UART device.
• However, we should clear UARTEN during the initialization sequence
• The UART0_IBRD_R and UART0_FBRD_R registers specify the
baud rate.
• The baud rate divider is a 22-bit binary fixed-point value with a
resolution of 2-6
• The Baud16 clock is created from the system bus clock, with a
frequency of (Bus clock frequency)/divider.
• The baud rate is 16 timesslower than Baud16
 UART Details
• For example, if the bus clock is 8 MHz and the desired baud rate is
19200 bits/sec, then the divider should be 8,000,000/16/19200 or
26.04167.
• As a binary fixed-point number, this number is about 11010.000011.
• We can establish this baud rateby putting the 11010 into
UART0_IBRD_R and the 000011 into UART0_FBRD_R .
• In reality, 11010.000011 is equal to 1667/64 or 26.046875.
• The three registers UART0_LCRH_R , UART0_IBRD_R , and
UART0_FBRD_R form an internal 30-bit register.
 UART Details
• This internal register is only updated when a write operation to
UART0_LCRH_R is performed, so any changes to the baud-rate
divisor must be followed by a write to the UART0_LCRH_R register
for the changes to take effect.
• Out of reset, both FIFOs are disabled and act as 1-byte-deep holding
registers. The FIFOs are enabled by setting the FENbit in
UART0_LCRH_R .
Synchronous Serial Interface