21ECL66 - VLSI Lab Manual Dept.

of ECE

STEPS TO EXECUTE DIGITAL DESIGN

(a) Simulation:

1. Right Click on the Desktop and Create a folder(ex-USN)

2. Open the folder and create two files by clicking on applications on Desktop --> accessories -->
text editor

3. Rename the created file by Design_name.v (ex-inv1.v) and Test_name.v(ex-inv2.v)

4. OpenDesign_name file, type the verilog program and save it.

5. OpenTest_name file, type the test bench program and save it andclose the folder.

6. Right click ->Open in Terminal and type the following commands

csh
source /home/install/cshrc
(Welcome to cadence tool suite)
nclaunch -new
(NC Launch Window opens, Select Multisteps)

Make sure that

-> In Design Directory the path should be /root/Desktop/folder name (USN)
-> In Library Mapping File the path should be/root/Desktop/folder name(USN)/[Link]
-> Click on create [Link] file -> save -> yes -> select don‟ t include any libraries-> ok ->ok

KSSEM Page 1
 21ECL66 - VLSI Lab Manual Dept. of ECE

7. In NC Launch window select both design and test bench file and click on “Launch Verilog
Compiler with current selection” icon and check for any syntax errors.
8. Expand Worklib, select only test bench and click “launch elaborator with current
selection” ICON.
9. Expand snapshots, select only test bench and click “launch simulator with current
selection” icon

KSSEM Page 2
 21ECL66 - VLSI Lab Manual Dept. of ECE

KSSEM Page 3
 21ECL66 - VLSI Lab Manual Dept. of ECE

10. Sim vision window opens. In Design Browser select test bench-> right click -
>send to waveform window -> click run icon. Verify the waveforms.

11. Close all simulation windows except terminal window

Performing Synthesis:

In terminal window type the following commands

First, close all windows including terminal window. Open terminal window in working directory.
type "pwd" to get the present working directory. copy the path and paste in 2 nd 6th line of
[Link] file. Change program name and report names.

KSSEM Page 4
 21ECL66 - VLSI Lab Manual Dept. of ECE

save the tcl file, close Terminal and open once again follow regular steps to invoke cadence tool
by givingcommands.
csh
source /home/install/cshrc
cadence tool appears. type "genus" and enter. It will invoke genus platform. Type following
source [Link] & press enter
GUI window opens and click on + symbol of layout tab. Select schematic and view the RTL
schematic
Verify Power, Area and Timing Reports which are automatically generated and stored in your
current working directory

[Link] file have following commands

set_db lib_search_path ./lib/90

set_db library [Link]
read_hdl design_filename.v (ex:counter.v)
elaborate
read_sdc constraints_filename.sdc (ex constraints_count.sdc) //Reading Top Level SDC
set_db syn_generic_effort medium //Effort level to medium for generic, mapping &
Optimization
set_db syn_map_effort medium
set_db syn_opt_effort medium
syn_generic
syn_map
Syn_opt //Performing Synthesis Mapping and Optimisation
report_timing -unconstrained> counter_timing.rep //GeneratesTiming report for worst
datapath and dumps into file
report_area > counter_area.rep //Generates Synthesis Area report and dumps into a
filereport_power > counter_power.rep //Generates Power Report [Pre-Layout]
write_hdl > counter_netlist.v //Creates readable Netlist File
write_sdc > counter_sdc.sdc //Creates Block Level SDC
gui_show

KSSEM Page 5
 21ECL66 - VLSI Lab Manual Dept. of ECE

PART A
ASIC DIGITAL DESIGN

Program 1: 4-Bit Adder

Aim: Write Verilog Code and Verify the Functionality using Test-bench.
• Synthesize the design by setting proper constraints and obtain the netlist. From the report
generated identify Critical path, Maximum delay, Total number of cells, Power requirement and
Total area required.

Design Information and Bock Diagram:

A full adder is a combinational circuit that performs the arithmetic sum of three input bits Ai,
addend Bi and carry in C in from the previous adder. Its results contain the sum Si and the
carryout, C out tothe next stage. So to design a 4-bit adder circuit we start by designing the 1 –bit
full adder then connecting the four 1-bit full adders to get the 4-bit adder as shown in the
diagram below.
For the 1-bit full adder, the design begins by drawing the Truth Table for the three input and the
corresponding output SUM and CARRY.

Fig: Diagram and truth table of full adder

KSSEM Page 6
 21ECL66 - VLSI Lab Manual Dept. of ECE

Adder Design Program:

`resetall
`timescale 1ns/1ns
module adder_4bit(a,b,c,sum,carry);
output [3:0]sum;
output carry;
input[3:0]a,b;
input c;
wire s1,s2,s3;
full_adder fa0 (a[0],b[0],c,sum[0], s1);
full_adder fa1 (a[1],b[1],s1,sum[1], s2);
full_adder fa2 (a[2],b[2],s2,sum[2], s3);
full_adder fa3 (a[3],b[3],s3,sum[3],carry);
endmodule
module full_adder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum = a^b^c;
assign carry = ((a&b)| (b&c)|(c&a));
endmodule

Adder-testbench Program:
`resetall
`timescale 1ns/1ns
module test_4_bit;
reg [3:0] a;

reg [3:0] b;
reg c;
wire [3:0] sum;
wire carry;
adder_4bit dut(a,b,c,sum,carry);
initial
begin
a = 4'b0011;b=4'b0011;c = 1'b0;
#10 a = 4'b1011;b=4'b0011;c = 1'b1;

KSSEM Page 7
 21ECL66 - VLSI Lab Manual Dept. of ECE

#10 a = 4'b1111;b=4'b0101;c = 1'b0;

#50 $finish;
end
endmodule

Simulation Waveform:

Synthesize RTL Schematic:

KSSEM Page 8
 21ECL66 - VLSI Lab Manual Dept. of ECE

Program 2: BOOTH MULTIPLIER

Aim: To write a verilog code for 4bit Booth Multiplier and verify the functionality using Test
bench.
• Synthesize, Analyse Reports and Netlist, Critical Path and Max Operating Frequency.
• From the report generated find the total number of cells, power requirement and total area
requirement.

Design Information and Flow Chart:

The booth algorithm is a multiplication algorithm that allows us to multiply the two signed binary
integers in 2's complement, respectively. It is also used to speed up the performance of the
multiplication process. It is very efficient too. It works on the string bits 0's in the multiplier that
requires no additional bit only shift the right-most string bits and a string of 1's in a multiplier bit
weight 2k to weight 2m that can be considered as 2k+ 1 - 2m.

• In the above flowchart, initially, AC and Qn + 1 bits are set to 0, and the SC is a
sequence counter that represents the total bits set n, which is equal to the number of bits
KSSEM Page 9
 21ECL66 - VLSI Lab Manual Dept. of ECE

in the multiplier. There are BR that represent the multiplicand bits, and QR represents
the multiplier bits.
• After that, we encountered two bits of the multiplier as Qn and Qn + 1, where Qn
represents the last bit of QR, and Qn + 1 represents the incremented bit of Qn by 1.
Suppose two bits of the multiplier is equal to 10; it means that we have to subtract the
multiplier from the partial product in the accumulator AC and then perform the arithmetic
shift operation (ashr).
• If the two of the multipliers equal to 01, it means we need to perform the addition of the
multiplicand to the partial product in accumulator AC and then perform the arithmetic
shift operation (ashr), including Qn + 1. The arithmetic shift operation is used in Booth's
algorithm to shift AC and QR bits to the right by one and remains the sign bit in AC
unchanged. And the sequence counter is continuously decremented till the computational
loop is repeated, equal to the number of bits (n).

Example: Multiply the two numbers 7 and 3 by using the Booth's multiplication
algorithm.
Ans. Here we have two numbers, 7 and 3. First of all, we need to convert 7 and 3 into binary
numbers like 7 = (0111) and 3 = (0011). Now set 7 (in binary 0111) as multiplicand (M) and 3
(in binary 0011) as a multiplier (Q). And SC (Sequence Count) represents the number of bits,
and here we have 4 bits, so set the SC = 4. Also, it shows the number of iteration cycles of the
booth's algorithms and then cycles run SC = SC - 1 time
The numerical example of the Booth's Multiplication Algorithm is 7 x 3 = 21 and the binary
representation of 21 is 10101. Here, we get the resultant in binary 00010101. Now we convert
it into decimal, as (000010101)10 = 2*4 + 2*3 + 2*2 + 2*1 + 2*0 => 21.

KSSEM Page 10
 21ECL66 - VLSI Lab Manual Dept. of ECE

Booth Multiplier Design Program:

KSSEM Page 11
 21ECL66 - VLSI Lab Manual Dept. of ECE

Booth Multiplier Testbench Program:

KSSEM Page 12
 21ECL66 - VLSI Lab Manual Dept. of ECE

Waveform:

Synthesis RTL Schematic:

KSSEM Page 13
 21ECL66 - VLSI Lab Manual Dept. of ECE

Program 3: 32-Bit ALU

Aim: 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if
statement for ALU Behavioral Modeling.
• Write Verilog Code
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing
constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path

Design Information and Bock Diagram:

The ALU will take in two 32-bit values, and control line. An Arithmetic unit does the
following task like addition subtraction, multi-fiction, and logical operations. As the
input is given in 32 bit we get 32 bit output. The arithmetic will show only one output at a
time, so a selector is necessaryto select one of the operator.

Fig: Block Diagram

32-bit ALU Design:

`resetall
`timescale 1ns/1ns
module alu_32bit1(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
case(f)
KSSEM Page 14
 21ECL66 - VLSI Lab Manual Dept. of ECE

3'b000:y=a&b; //AND Operation

3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b100:y=a+b; //Addition
3'b101:y=a-b; //Subtraction
3'b110:y=~a; //Notdefault:y=32'bz;
endcase
end
endmodule

32-bit ALU Testbench:

`resetall
`timescale 1ns/1ns
module alu_32bit_tb_case;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit1 test2(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b011;
#10 f=3'b100;
#10 f=3'b101;
#10 f=3'b110;
#10 f=3'b111;
#100 $finish;
end
endmodule

KSSEM Page 15
 21ECL66 - VLSI Lab Manual Dept. of ECE

Simulation Waveform:

Synthesize RTL Schematic:

Progarm 4: Latches and Flip Flops

Aim: Write a Verilog code for Latch and Flip-flops (D, SR, JK), Synthesize the design
andcompare the synthesis report.

Theory: Latches and flip-flops are the basic elements for storing information. One latch
or flip-flop can store one bit of information. The main difference between latches and
flip-flops is that for latches, their outputs are constantly affected by their inputs if the
enable signal is asserted. In other words, when they are enabled, their content changes

KSSEM Page 16
 21ECL66 - VLSI Lab Manual Dept. of ECE

immediately when their inputs change.

Flip-flops, on the other hand, have their content change only either at the rising or falling
edge of the enable signal. This enable signal is usually the controlling clock signal. After
the rising or falling edge of the clock, the flip-flop content remains constant even if the
input changes. There are basically four main types of latches and flip-flops: SR, D, and
JK. The major differences in these flip-flop types are the number of inputs they have and
how they change state. For each type, there are also different variations that enhance their
operations

(a) D latch Design Program:

`resetall
`timescale 1ns/1ns
module dlatch(e,d,q);
input e,d;
output q;
reg q;
always @(e or d)
begin
if(!e)
q<= 1’bz;else
q<= d;
end
endmodule

(a) D latch test_bench Program:

`resetall
`timescale 1ns/1ns
module dlatch_test;
wire q;
reg e,d;
dlatch d1(e,d,q);
initial
begin
d=1’b0; e=1’b0;
#20 e=1’b1; d=1’b0;
#20 e=1’b1; d=1’b1;

KSSEM Page 17
 21ECL66 - VLSI Lab Manual Dept. of ECE

#20 e=1’b1; d=1’b0;

#100 $finish;
end
endmodule

Simulation Waveform:

Synthesis RTL Schematic:

(b) D flip flop design Program:

`resetall
`timescale 1ns/1ns
module dff(d, clk, Q);
input d, clk;
output reg Q;
always @(posedge clk)
begin
if(d == 1)
Q = 1;

KSSEM Page 18
 21ECL66 - VLSI Lab Manual Dept. of ECE

else if(d == 0)
Q = 0;
end
endmodule

(b) D flip flop test bench:

`resetall
`timescale 1ns/1ns
module test_dff;
reg d ,clk;
wire Q;
dff dut(d, clk, Q);
always
#10 clk = ~clk;
initial
begin
clk=1'b0;
#40 d=1'b1;
#40 d=1'b0;
#40 $finish;
end
endmodule

Wave Forms for D-Flip Flop:

KSSEM Page 19
 21ECL66 - VLSI Lab Manual Dept. of ECE

Synthesis RTL Schematic:

(c)SR Latch Design Program:

`resetall
`timescale 1ns/1ns
Module srlatch(s,r,en,q)
input s,r,en;
output q;
reg q;
always @(en or s or r)
begin
if(!en)
begin
q=1'bz;
end
else
begin
if(s == 1 && r == 0)
q = 1;
else if(s == 0 && r == 1)
q = 0;
else if(s == 1 && r == 1)
q = 1'bx;

KSSEM Page 20
 21ECL66 - VLSI Lab Manual Dept. of ECE

else if(s== 0 && r == 0)

q = q;
end
end
endmodule

(c)SR Latch Test-bench Program:

`timescale 1ns/1ns
module srl_tt;
wire q,qb;
reg en,s,r;
srlatch l1(en,s,r,q,qb);
initial
begin
en= 1'b0; s=1'b0; r=1'b1;
#20 en= 1'b1; s=1'b1; r=1'b0;
#20 en= 1'b1; s=1'b0; r=1'b1;
#20 en= 1'b1; s=1'b0; r=1'b0;
#20 en= 1'b1; s=1'b1; r=1'b1;
#100 $finish;
end
endmodule

KSSEM Page 21
 21ECL66 - VLSI Lab Manual Dept. of ECE

Simulation Waveform:

Synthesis Report:
@genus:root: 16> report_area
============================================================
Generated by: Genus(TM) Synthesis Solution 17.22-s017_1
Generated on: Nov 02 2021 [Link] pm
Module: srlatch
Operating conditions: slow (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================
Instance Module Cell Count Cell Area Net Area Total Area Wireload
---------------------------------------------------------------------
srlatch 9 77.204 0.000 77.204 <none> (D)

@genus:root: 17> report_power

============================================================
Generated by: Genus(TM) Synthesis Solution 17.22-s017_1
Generated on: Nov 02 2021 [Link] pm
Module: srlatch
Operating conditions: slow (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================
Leakage Dynamic Total
Instance Cells Power(nW) Power(nW) Power(nW)
---------------------------------------------
srlatch 9 464.521 2144.658 2609.179

KSSEM Page 22
 21ECL66 - VLSI Lab Manual Dept. of ECE

@genus:root: 15> report_timing

Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'srlatch'.
: Use 'report timing -lint' for more information.
============================================================
Generated by: Genus(TM) Synthesis Solution 17.22-s017_1
Generated on: Nov 02 2021 [Link] pm
Module: srlatch
Operating conditions: slow (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================
Some unconstrained paths have not been displayed.
Use -unconstrained or set the root attribute 'timing_report_unconstrained' to 'true' to see only
these unconstrained paths.

Synthesis RTL Schematic:

(
d
)
S
R

F
l
i
p
-
F
l
o
p

D
e
sign:
`resetall
`timescale 1ns/1ns
module srff(S, R, clk, Q);
input S, R, clk;
output reg Q;

KSSEM Page 23
 21ECL66 - VLSI Lab Manual Dept. of ECE

always @(posedge clk)

begin
if(S == 1 &&R == 0)
Q = 1;
else if(S == 0 && R == 1)
Q = 0;
else if(S == 1 && R == 1)
Q = 1'bz;
else if(S== 0 && R == 0)
Q = Q;
end
endmodule

(d)SR Flip-Flop Testbench:

`resetall
`timescale 1ns/1ns
module test_srff;
reg S, R ,clk;
wire Q;
srff dut(S, R, clk, Q);
always
#10 clk = ~clk;
Initial
begin
clk=1'b0;
#40 S=1'b1; R = 1'b0;
#40 S=1'b0; R = 1'b0;
#40 S=1'b0; R = 1'b1;
#40 S=1'b1; R = 1'b1;
#40 S=1'b1; R = 1'b1;
#240 $finish;
end
endmodule

KSSEM Page 24
 21ECL66 - VLSI Lab Manual Dept. of ECE

Synthesize RTL Schematic:

JK Latch Design:
`resetall
`timescale 1ns/1ns
module jkl(j, k, en, Q);
input j, k, en;
output reg Q;
always @(j or k or en)
begin
if(!en)
begin
Q = 1'bz;
end
else
begin
if(j == 1 && k == 0)
Q = 1;
else if(j == 0 && k == 1)
Q = 0;
else if(j == 1 && k == 1)
Q = ~Q;
else if(j== 0 && k == 0)
Q = Q;
end
end
KSSEM Page 25
 21ECL66 - VLSI Lab Manual Dept. of ECE

endmodule

JK Latch testbench:
`resetall
`timescale 1ns/1ns
module test_jkl;
reg j, k , en;
wire Q;
jkl dut(j, k, en, Q);
initial
begin
en=1'b0; j=1'b1; k = 1'b0;
#40 en=1'b1; j=1'b1; k = 1'b0;
#40 en=1'b1; j=1'b0; k = 1'b0;
#40 en=1'b1; j=1'b0; k = 1'b1;
#40 en=1'b1; j=1'b1; k = 1'b1;
#40 en=1'b1; j=1'b1; k = 1'b1;
#40 $finish;
end
endmodule

@genus:root: 16> report_area

============================================================
Generated by: Genus(TM) Synthesis Solution 17.22-s017_1
Generated on: Nov 02 2021 [Link] pm
Module: jklatch
Operating conditions: slow (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================
Instance Module Cell Count Cell Area Net Area Total Area Wireload
-------------------------------------------------------------------------
jklatch 12 90.828 0.000 90.828 <none> (D)

(D) = wireload is default in technology library

@genus:root: 17> report_power

============================================================
Generated by: Genus(TM) Synthesis Solution 17.22-s017_1
Generated on: Nov 02 2021 [Link] pm
Module: jklatch

KSSEM Page 26
 21ECL66 - VLSI Lab Manual Dept. of ECE

Operating conditions: slow (balanced_tree)

Wireload mode: enclosed
Area mode: timing library
============================================================
Leakage Dynamic Total
Instance Cells Power(nW) Power(nW) Power(nW)
---------------------------------------------
jklatch 12 550.613 2816.223 3366.836

@genus:root: 14> reporrt_timing

invalid command name "reporrt_timing"
@genus:root: 15> report_timing
Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'jklatch'.
: Use 'report timing -lint' for more information.
============================================================
Generated by: Genus(TM) Synthesis Solution 17.22-s017_1
Generated on: Nov 02 2021 [Link] pm
Module: jklatch
Operating conditions: slow (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================
Some unconstrained paths have not been displayed.
Use -unconstrained or set the root attribute 'timing_report_unconstrained' to 'true' to see only
these unconstrained patHS.

Synthesis RTL schematic:

KSSEM Page 27
 21ECL66 - VLSI Lab Manual Dept. of ECE

JK Flip-Flop Design:
`resetall
`timescale 1ns/1ns
module jkff(j, k, clk, Q);
input j, k, clk;
output reg Q;
always @(posedge clk)
begin
if(j == 1 && k== 0)
Q = 1;
else if(j == 0 && k == 1)
Q = 0;
else if(j == 1 && k == 1)
Q = ~Q;
else if(j== 0 && k == 0)
Q = Q;
end
endmodule

JK flip-flop testbench:
`resetall
`timescale 1ns/1ns
module test_jkff;
reg j, k ,clk;
wire Q;
jkff dut(j, k, clk, Q);
always
#10 clk = ~clk;
initial
begi
n
clk=
1'b0;
#40 j=1'b1; k = 1'b0;
#40 j=1'b0; k = 1'b0;
#40 j=1'b0; k = 1'b1;
#40 j=1'b1; k = 1'b1;
#40 j=1'b1; k = 1'b1;
#40

KSSEM Page 28
 21ECL66 - VLSI Lab Manual Dept. of ECE

$finish;
end
endmodule

@genus:root: 16> report_area

============================================================
Generated by: Genus(TM) Synthesis Solution 17.22-s017_1
Generated on: Nov 02 2021 [Link] pm
Module: jkff
Operating conditions: slow (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================
Instance Module Cell Count Cell Area Net Area Total Area Wireload
----------------------------------------------------------------------------
jkff 13 97.640 0.000 97.640 <none> (D)

@genus:root: 17> report_power

============================================================
Generated by: Genus(TM) Synthesis Solution 17.22-s017_1
Generated on: Nov 02 2021 [Link] pm
Module: jkff
Operating conditions: slow (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================
Leakage Dynamic Total
Instance Cells Power(nW) Power(nW) Power(nW)
---------------------------------------------
jkff 13 504.704 44198.794 44703.498

@genus:root: 15> report_timing

Capture Launch
Clock Edge:+ 2000 0
Src Latency:+ 0 0
Net Latency:+ 0 (I) 0 (I)
Arrival:= 2000 0
Output Delay:- 1000
Uncertainty:- 10

Required Time:= 990

KSSEM Page 29
 21ECL66 - VLSI Lab Manual Dept. of ECE

Launch Clock:- 0
Data Path:- 537
Slack:= 453

Exceptions/Constraints:
output_delay 1000 constraints_jkff.sdc_line_9

# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay ArrivalInstance
# (fF) (ps) (ps) (ps)
Location#

q_reg38/CK - - R (arrival) 3 - 100 - 0(-,-

)
q_reg38/Q - CK->Q F DFFQX1 1 2.7 47 330330 (-,-)
g218/Y - A->Y R CLKINVX1 2 6.8 66 66396 (-,-)
qb_tri 4547/Y - OE->Y F TBUFX1 2 5.1 50 141537 (-,-)
qb <<< - F (port) - - - 0537 (-,-)

Synthesis RTL schematic:

KSSEM Page 30
 21ECL66 - VLSI Lab Manual Dept. of ECE

PART B
ANALOG DESIGN

Steps to Execute Analog Design

1. Right Click on the Desktop and Create a new folder(ex-USN)
2. Right click ->Open in Terminal and type the following commands
csh
source /home/install/cshrc
(Welcome to cadence tool suite)
Virtuoso &
3. Virtuoso 6.1.6 window opens and follow the steps below to create library
• Tools ->Library Manager -> File ->new -> Library
• In the new library window give a new library name (ex: your name) ->ok
• In the Technology file for new library window select “Attach to an existing technology library”
->ok ->select gpdk180->ok
4. In Library manager work area window select your created library, File -> new -> cellview. In new
File window type cell name (ex:inv) {Make sure that library is your library name} and click ok ->
yes

A blank Schematic Editor window opens. In this window schematic has to be drawn using following
steps

Adding Components to schematic

a) Create -> Instance or press i from keyboard.
b) Click on browse button. Browse to gpdk180 library and select the required

KSSEM Page 31
 21ECL66 - VLSI Lab Manual Dept. of ECE

components.(ex: PMOS and NMOS) Modify the specifications as required.

c) After you complete the Add Instance form, move your cursor to schematic window and
left click to place a component.
d) After entering the components, click cancel in the Add Instance or press ESC.
e) Adding PINS to Schematic
f) Create pin or press “p”
g) The add pin form appears.
h) Type all the required pins along with input/output and place it on schematic window.

Adding Wires to Schematic

a) Click the Wire(narrow) icon in the schematic window.
b) Connect all the components using the wires. click on check and save icon in the schematic
editor window. Check for any errors in CIW window.
Symbol Creation
a) Create --> cellview --> From Cellview
b) In Cellviewform , verify that From View Name field is to schematic, and TO View Name
field is set to symbol, with the Tool/Data Type set as Schematic Symbol.
c) Click ok in the CellView form and Symbol generation form appears.
d) Modify the Pin Specifications. For ex: Put pins in appropriate position ie.,
left/right/top/bottom.
e) Click ok and a new window appears with automatically created symbol.
Building the test design
a) In CIW(Library Manager), File-->new-->Cellview
b) Set up New file form appears as follows:

KSSEM Page 32
 21ECL66 - VLSI Lab Manual Dept. of ECE

In the above form for library select your library created by you.
c) Click ok; a blank schematic window for test design appears.
Building the Test circuit
a) Draw the design test circuits according to the specification by adding symbol from your
library and Vpulse, Vdc , gnd from analog library.
b) Once design is completed click check and save icon.
To simulate the test design
a) Launch -->ADE L
b) Virtuoso ADE(Analog Design Environment) simulating window appears. Setup→Model
libraries → 180nm technology file should be ticked. Other files should be unticked.
Choosing Analyses
Transient Analysis:
a) Select Analyses --> choose
b) To setup the transient analysis, select tran.
c) Click at the moderate button and press apply.
d) Enter all the required specification and press ok.

DC analysis:
a) Select Analyses--> choose
b) To setup dc analysis, select dc.
c) In the DC analysis window, select save DC operating point.
d) Turn on the Component Parameter.
e) Click on the select component, which takes you to test schematic window.
f) Select input signal (ex: vpulse source in inverter_test).
g) Select DC from the appeared window
AC analysis:
a) Select Analyses-->choose
b) To setup ac analysis, select ac
c) Enter all the required specification and press ok.
Selecting outputs for plotting
a) Outputs --> To be plotted --> select on Schematic or click on setup output icon.
b) In the Select the required inputs and outputs from schematic.

KSSEM Page 33
 21ECL66 - VLSI Lab Manual Dept. of ECE

Running the simulation

a) Simulation --> Netlist and Run or select Netlist and Run icon.
b) When simulation finishes, the Transint, DC,and AC plots automatically will be popped up
along with netlist.

Layout Design Steps

1. Open schematic editor window and draw the schematic circuit of the specified experiment.
Save the circuit and select check and save icon.
2. If no errors in the circuit then select Launch -> Layout XL -> select create new and Automatic
in start up option window. In new file window set cell name as eg: inverter, View as Layout
and type should be Layout. Then select ok.
3. In Layout editor window select connectivity -> Generate -> All from sourceok.
4. Extend the PR boundary area by using stretch icon.
5. Place NMOS and PMOS transistor inside PR boundary and press shift f.
6. Select the NMOS/PMOS, Right click and select properties. In properties window select
parameter -> Body type -> Integrated/Detachable as per requirement.
7. Select place icon -> pin placement and select input parameters one by one eg (Vss, then Vdd,
then Vin etc ). Select attribute and select edge as a bottom for VSS and top for Vddand then
select apply. Later select HR rails. Whereas for other inputs select only the attributes as left
and outputs as right. No HR rails are selected for these parameters.
8. Select create -> Via, Via define and select -> M1-poly to connect metal to polysilicon for
inputs.
9. For Vdd and Vss connection select “p” from keyboard and select metal1 from the layer
window and connect. ( When narrow wire is required use “p” form keyboard else select create
-> wiring -> wire and then select required layer in layer window.

10. Design the layout of specified circuit and save the design.
11. For Simulation
a) Assura -> Technology->home/install/Foundary/Analog/180nm/assura_tech.lib
b) Select Assura ->Run DRC -> type file name as abc and select technology asgpdk180->ok.

c) If no errors then select Assura->Run LVS->type file name abcd and select technology as

KSSEM Page 34
 21ECL66 - VLSI Lab Manual Dept. of ECE

gpdk180 -> ok.

d) If LVS matches then select Assura -> Run Quantus-> select setup -> technology -> gpdk180
and output -> extract view, In the same window select Extraction type -> RC -> reference
node -> Vss -> ok.
e) Select file -> open -> select cell -> ok (eg: cell:inverters, view: AV_extracted ok). Check for
the pcacitor and presistor(type shift f to see the values of pcacitor and presistor) from the
layout.

KSSEM Page 35
 21ECL66 - VLSI Lab Manual Dept. of ECE

1. CMOS INVERTER

Aim: Capture the Schematic of a CMOS Inverter with Load Capacitance of 0.1 pF and set the Widths
of Inverter with
(i) WN = WP
(ii) WN = 2 WP
(iii) WN = WP / 2
and Length at selected Technology. Carry out the following:
1. Set the Input Signal to a pulse with Rise Time, Fall Time of 1 ps and Pulse Width of 10 ns, Time
Period of 20 ns and plot the input voltage and output voltage of the designed Inverter
2. From the Simulation Results, compute tpHL, tpLH and tPD for all the three geometrical settings of
Width
3. Tabulate the results of delay and find the best geometry for minimum delay forCMOS Inverter

(i) Wn = Wp

KSSEM Page 36
 21ECL66 - VLSI Lab Manual Dept. of ECE

(ii)Wn=2Wp:

Fig: Schematic Diagram

(iii) Repeat the schematic, symbol, and test circuit for case Wn=Wp/2, by choosingWp=2µm

Fig: Inverter Symbol

KSSEM Page 37
 21ECL66 - VLSI Lab Manual
Dept. of ECE

Specifications: Vpulse →V1=0 V2=1.8 V Delay = 0

Rise time =Fall time = 1n
Pulse width = 10n , Period = 20n

Vdc → DC Voltage= 1.8V

Capacitance → Cap=0.1pF

Inverter_test Circuit:

Simulation settings:
set up for transient analysis:

1. Stop time= 200n --->Click on “moderate” --> Apply

Setup for DC analysis:

1. Enable -->Save DC operating point
2. From Sweep variable --> Component Parameter --> click on select parameter --> select vpulse
--> select DC from the appeared window

3. In sweep Range --> Start-stop-->Start = 0 , stop = 1.8

4. Sweep type: Linear --> Step size -->0.01

KSSEM Page 38
 21ECL66 - VLSI Lab Manual Dept. of ECE

Inverter output Waveforms

Calculation of 𝒕𝒑 , 𝒕𝒑𝑳𝑯 and td:

• In the waveform window right click on input signal, send to calculator, in calculator window
copy the function of input signal and paste it in function panelusing delay function. Repeat the
same for output signal.
• Initialize the threshold of (VDC/2= 0.9)
• Edge no.1= 1 for signal1 and edge no. 1=2 for signal 2
• Edge type = rising for signal 1 and edge type =falling for signal 2
• Click ok --> click on Evaluate the Buffer and Display the results in a Table

• Note down 𝒕𝒑𝑯𝑳. Repeat the same for Edge type falling to raising and note down 𝒕𝒑𝑳𝑯.

• To calculate the Propagation Delay (𝑡𝑃𝐷), the formula used is

KSSEM Page 39
 21ECL66 - VLSI Lab Manual Dept. of ECE

INVERTER LAYOUT:

KSSEM Page 40
 21ECL66 - VLSI Lab Manual Dept. of ECE

2. CMOS NAND

Aim: Capture the Schematic of 2-input CMOS NAND gate having similar delay as that of
CMOSinverter computed in experiment 1. Verify the functionality of NAND gate and find out
the delaytd for all four possible combinations of input vectors.

Fig : NAND Schematic

Fig: NAND Symbol

KSSEM Page 41
 21ECL66 - VLSI Lab Manual Dept. of ECE

Fig: NAND_test

Simulation settings:
Forcing inputs:
Setup → stimuli → tick A and B inputs and give parameters such as one value as 1, zero value as
0, rise time 1ns, fall time 1ns, time period 20ns, delay as 0.
set up for transient analysis: Stop time = 200n
Output waveform:

KSSEM Page 42
 21ECL66 - VLSI Lab Manual Dept. of ECE

NAND Layout:

KSSEM Page 43
 21ECL66 - VLSI Lab Manual Dept. of ECE

3: COMMON SOURCE AMPLIFIER WITH PMOS CURRENT MIRROR

LOAD

Aim: Capture the Schematic of a Common Source Amplifier with PMOS Current Mirror Load and
find its Transient Response and AC Response. Measure the UGB and Amplification Factor by
varying transistor geometries, study the impact of variation in width to UGB.
• Draw the layout of Common Source Amplifier, use optimum layout methods. Verify DRC and
LVS, extract the parasitics and perform the post layout simulation, compare the results with pre
layout simulations. Record the observations.

SCHEMATIC CAPTURE:
• Following the techniques demonstrated in Lab – 01, Create a New Library using the
option “File → New → Library”, create a New Cell View upon selecting the newly created
library using the option “File → New → Cell View” and instantiate the required devices
using the “Create → Instance” option.

Schematic of Common Source Amplifier with PMOS Current Mirror Load

KSSEM Page 44
 21ECL66 - VLSI Lab Manual Dept. of ECE

Symbol of Common Source Amplifier with PMOS Current Mirror Load

FUNCTIONAL SIMULATION:

Using the symbol created, build the Test Schematic. Create a New Cell View, instantiate the
symbol of Common Source Amplifier with PMOS Current Mirror Load, DC Voltage
Source, Current Source, AC Voltage Source, Capacitance, Resistance and Ground, connect
the using wires.

Test Schematic for Common Source Amplifier with PMOS Current Mirror Load

KSSEM Page 45
 21ECL66 - VLSI Lab Manual Dept. of ECE

Launch ADE L, import the design variables, mention the values and select the Transient
Analysis, DC Analysis and AC Analysis, mention the parameters and choose the signals to
be plotted as shown in below Figure.

KSSEM Page 46
 21ECL66 - VLSI Lab Manual Dept. of ECE

Transient Analysis

AC Analysis

KSSEM Page 47
 21ECL66 - VLSI Lab Manual Dept. of ECE

Gain and Phase plot

Layout:

KSSEM Page 48
21ECL66 - VLSI Lab Manual Dept. of
ECE

KSSEM Page 49