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Data Manipulation in Computer Architecture

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4 views46 pages

Data Manipulation in Computer Architecture

Uploaded by

binthanha7
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

DATA MANIPULATION

Computer Science: An Overview by J. Glenn Brookshear and Dennis Brylow publisher Pearson
Data Manipulation
 Computer Architecture
 Machine Language
 Program Execution
 Arithmetic/Logic Instructions
 Communicating with Other Devices
 Other Architectures

6
COMPUTER ARCHITECTURE
Computer Architecture
 Central Processing Unit (CPU) or processor
 Arithmetic/Logic unit versus Control unit
 Registers
 General purpose
 Special purpose
 Bus
 Motherboard

8
CPU and main memory connected via
a bus

9
Motherboards
 The motherboard
 is the main printed circuit board.
 contains the buses, or electrical
pathways found in a computer.
Buses allow data to travel
among the various components.
 accommodates CPU, RAM,
expansion slots, heat sink/fan
assembly, BIOS chip, chip set,
sockets, internal and external
connectors, various ports, and
the embedded wires that
interconnect the motherboard
components.

10
Central Processing Unit
 The Central Processing Unit (CPU) is known as the brain
of the computer. It is also referred to as the processor.
 The CPU executes a program, which is a sequence of
stored instructions.

11
Central Processing Unit
 Some CPUs incorporate hyperthreading or
hypertransport to enhance the performance of the CPU.
 The amount of data that a CPU can process at one time
depends on the size of the processor data bus.
 Speed of the CPU is measured in cycles per second -
megahertz (MHz) or gigahertz (GHz).
 Overclocking is a technique used to make a processor
work at a faster speed than its original specification.

12
Central Processing Unit
 The latest processor technology has resulted in CPU
manufacturers finding ways to incorporate more than one
CPU core onto a single chip.
 Dual Core CPU - Two cores inside a single CPU
 Triple Core CPU - Three cores inside a single CPU
 Quad Core CPU - Four cores inside a single CPU
 Hexa-Core CPU - Six cores inside a single CPU
 Octa-Core CPU - Eight cores inside a single CPU

13
The Arithmetic/Logic Unit
 Subsystem that performs addition, subtraction, and
comparison for equality
 Components
 Registers, interconnections between components, and the
ALU circuitry
 Register
 Storage cell that holds the operands of an arithmetic
operation and holds its result
 Bus
 Path for electrical signals

14
The Arithmetic/Logic Unit
 Registers are similar to RAM with following minor
differences
 They do not have a numeric memory address but are
accessed by a special register designator such as A, X or R0
 They can be accessed much more quickly than regular
memory cells
 They are not used for general purpose storage but for
specific purposes such as holding the operands for an
upcoming arithmetic computations.
 A typical ALU has 16, 32 or 64 registers.

15
The Control Unit
 Control unit
 Tasks: fetch, decode, and execute

16
MACHINE LANGUAGE
Stored Program Concept
 A program can be encoded as bit patterns and stored in
main memory.
 From there, the CPU can then extract the instructions and
execute them.
 In turn, the program to be executed can be altered easily.

18
Terminology
 Machine instruction: An instruction (or command)
encoded as a bit pattern recognizable by the CPU

 Machine language: The set of all instructions recognized


by a machine

19
Machine Language Philosophies
 Reduced Instruction Set Computing (RISC)
 Few, simple, efficient, and fast instructions
 Examples: PowerPC from Apple/IBM/Motorola and ARM

 Complex Instruction Set Computing (CISC)


 Many, convenient, and powerful instructions
 Example: Intel

20
Machine Instruction Types
 Data Transfer: copy data from one location to another
 Arithmetic/Logic: use existing bit patterns to compute a
new bit patterns
 Control: direct the execution of the program

21
Dividing values stored in memory

23
An architecture of the machine

24
Parts of a Machine Instruction
 Op-code: Specifies which operation to execute
 Operand: Gives more detailed information about the
operation
 Interpretation of operand varies depending on op-code

25
The composition of an instruction

26
Decoding the instruction 35A7

27
A Simple Machine Language
Op-code Operand Description
1 RXY LOAD reg. R from cell XY.
2 RXY LOAD reg. R with XY.
3 RXY STORE reg. R at XY.
4 0RS MOVE R to S.
5 RST ADD S and T into R. (2’s comp.)
6 RST ADD S and T into R. (floating pt.)
7 RST OR S and T into R.
8 RST AND S and T into R.
9 RST XOR S and T into R.
A R0X ROTATE reg. R X times.
B RXY JUMP to XY if R = reg. 0. 28
C 0 HALT.
A Simple Machine Language
 14A3: Load
 The contents of the memory cell located at address A3 to
be placed in register 4.
 20A3: Load
 The value A3 to be placed in register 0.
 35B1: Store
 The contents of register 5 to be placed in the memory cell
whose address is B1.
 40A4: Move
 The contents of register A to be copied into register 4.

29
An encoded version of the instructions

QUIZ
33
PROGRAM EXECUTION
Program Execution
 Controlled by two special-purpose registers
 Program counter: address of next instruction
 Instruction register: current instruction
 Machine Cycle
 Fetch
 Decode
 Execute

39
The machine cycle

40
Decoding the instruction B258

41
A program stored in main memory

42
ARITHMETIC/LOGIC
INSTRUCTIONS
Arithmetic/Logic Operations
 Logic: AND, OR, XOR
 Masking
 Rotate and Shift:
 circular shift (rotation)
 logical shift
 arithmetic shift
 Arithmetic: add, subtract, multiply, divide
 Precise action depends on how the values are encoded
(two’s complement versus floating-point).

46
Masking

47
Circular shift

48
Logical shift

QUIZ 49
COMMUNICATING WITH
OTHER DEVICES
Communicating with Other Devices
 Controller: An intermediary apparatus that handles
communication between the computer and a device
 Specialized controllers for each type of device
 General purpose controllers (USB and FireWire)
 Port: The point at which a device connects to a computer
 Memory-mapped I/O: CPU communicates with peripheral
devices as though they were memory cells

56
Controllers attached to a machine’s
bus

57
A conceptual representation of
memory-mapped I/O

58
Communicating with Other Devices

 Direct memory access (DMA): Main memory access by a


controller over the bus
 Von Neumann Bottleneck: Insufficient bus speed impedes
performance
 Handshaking: The process of coordinating the transfer of
data between components

59
Communicating with Other Devices

 Parallel Communication: Several communication paths


transfer bits simultaneously.
 Serial Communication: Bits are transferred one after the
other over a single communication path.

10101001

1
0
1
0
1
0
0
60
1
Data Communication Rates
 Measurement units
 Bps: Bits per second
 Kbps: Kilo-bps (1,000 bps)
 Mbps: Mega-bps (1,000,000 bps)
 Gbps: Giga-bps (1,000,000,000 bps)
 Bandwidth: Maximum available rate

61
OTHER ARCHITECHTURES
Other Architectures
 Technologies to increase throughput:
 Pipelining: Overlap steps of the machine cycle
 Parallel Processing: Use multiple processors simultaneously
 SISD: No parallel processing
 MIMD: Different programs, different data
 SIMD: Same program, different data

75
Pipelining

76
Parallel processing
 Method where more than one processor performs at the
same time—faster processing

77

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