Chapter 1 Background

1
Outlines
1.1 Introduction
1.2 System Software and Machine Architecture
1.3 The Simplified Instructional Computer (SIC)
SIC Machine Architecture
SIC/XE Machine Architecture
SIC Programming Examples
1.4 Traditional (CISC) Machines
1.5 RISC Machines

2
1.1 Introduction

• Definition of System software

– System software consists of a variety of programs that
support the operation of a computer

3
1.1 Introduction (cont’d)

•Write programs in assembler language and use macro instructions

to read or write data or perform other high-level functions.
•These programs are converted to machine language using an
assembler with a macro processor. The converted code can be
loaded into the system for execution using a loader or linker, and a
debugger can be used to detect program errors.
1.1 Introduction (cont’d)

•User controlled all of these processes by interacting with the

operating system of the computer
• UNIX or DOS
• Type commands at a keyboard (Command Line)
• Windows or MacOS
• With menus and point-and-click interface (GUI)
• The operating system took care of all the machine-level details for
the user
• Network, storage devices, input/output
1.1 Introduction (cont’d)
•Machine architecture-dependent (ch2~6)
• Assemblers
• Loaders
• Linker
• Macro Processor
• Compilers
• Operating Systems
•Other important types of system software (ch7)
• Database Management System
• Text Editor and Interactive Debugging System
• Software engineering concepts and techniques (ch8)
1.2 System Software and Machine Architecture
• One characteristic in which most system software differs from
application software is machine dependency
• System programs are intended to support the operation and use
of the computer itself, rather than any particular application.
• – E.g.
• Assemblers: instruction formats, addressing mode
• Compilers: resisters and machine instruction
• Operating systems: directly management the resources of a computing system

7
1.2 System Software and Machine Architecture (Cont’d)
• There are some aspects of system software that do not directly
depend upon the type of computing system being supported
• For example, the general design and logic of the assembler is basically the
same on most computers.
• The second para. of Section 1.2

8
1.2 System Software and Machine Architecture (Cont’d)
• Because most system software is machine-dependent, we must
include real machines and real pieces of software in our study.
• Simplified Instructional Computer (SIC)
• SIC is a hypothetical computer that has been carefully designed to
include the hardware features most often found on real machines,
while avoiding unusual or irrelevant complexities

9
1.2 System Software and Machine Architecture (Cont’d)
1. Features that are fundamental, and that should be found in any
example of this type of software
2. Features whose presence and character are closely related to the
machine architecture
3. Other features that are commonly found in implementation of this
type of software, and that are relatively machine-independent
4. Major design option for structuring a particular piece of software –
for example, single-pass vs. multi-pass processing
5. Example of implementations on actual machine, stressing unusual
software feature and those that are related to machine characteristics
 1.3 The Simplified Instructional Computer (SIC)
• Like many other products, SIC comes in two versions
– The standard model
– An XE version
• “extra equipment”, “extra expensive”
• The two versions has been designed to be upward compatible
– An object program for the standard SIC machine will also execute
properly on a SIC/XE system

11
Von Neumann architecture
•A computer architecture based on a 1945 description by John von
Neumann
• A processing unit with both an
arithmetic logic unit and a control
unit
– A control unit that includes an
instruction register and a program
counter
• Memory that stores data and
instructions
CPU
• Input and output mechanisms
• Single bus system

12
1.3.1 SIC Machine Architecture
•Memory
• Memory consists of 8-bit bytes
• Any 3 consecutive bytes form a word (24 bits)
• Total of 32768 (215) bytes in the computer memory

13
 1.3.1 SIC Machine Architecture (cont’d)
• Registers
– Five registers
– Each register is 24 bits in length
Mnemonic Number Special use
A 0 Accumulator; used for a arithmetic operations
X 1 Index register; used for addressing
L 2 Linkage register; the Jump to Subroutine (JSUB) instruction stores the return
address in this register
PC 8 Program counter; contains the address of the next instruction to be fetched for
execution
SW 9 Status word; contains a variety of information, including a Condition Code (CC)

14
1.3.1 SIC Machine Architecture (cont’d)
• Data Formats
– Integers are stored as 24-bit binary number
– 2’s complement representation for negative values
– Characters are stored using 8-bit ASCII codes (See Appendix B)
– No floating-point hardware on the standard version of SIC

15
1.3.1 SIC Machine Architecture (cont’d)
• Instruction Formats
– Standard version of SIC
– 24 bits

8 1 15
opcode x address

The flag bit x is used to indicate indexed-addressing mode

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1.3.1 SIC Machine Architecture (cont’d)
• Addressing Modes
– There are two addressing modes available
• Indicated by x bit in the instruction

Mode Indication Target address calculation

Direct x=0 TA=address
Indexed x=1 TA=address+(X)

(X): the contents of register X (Index register)

17
1.3.1 SIC Machine Architecture (cont’d)
• Instruction Set
– Load and store registers
• LDA, LDX, STA, STX, etc.
– Integer arithmetic operations
• ADD, SUB, MUL, DIV
• All arithmetic operations involve register A and a word in memory, with the result
being left in A
– COMP
– Conditional jump instructions
• JLT, JEQ, JGT
– Subroutine linkage
• JSUB, RSUB
• See Appendix A, Pages 495-499

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1.3.1 SIC Machine Architecture (cont’d)
• Input and Output
– Input and output are performed by transferring 1 byte at a
time to or from the rightmost 8 bits of register A
– Each device is assigned a unique 8-bit code (device code).
– SIC has 3 I/O instruction
• Test Device (TD) instruction
• Read Data (RD)
• Write Data (WD)

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1.3.2 SIC/XE Machine Architecture

• Memory
• Maximum memory available on a SIC/XE system is 1 megabyte (220
bytes)

20
1.3.2 SIC/XE Machine Architecture (cont’d)

• Registers
•Additional registers are provided by SIC/XE

Mnemonic Number Special use

B 3 Base register; used for addressing
S 4 General working register– no special use
T 5 General working register– no special use
F 6 Floating-point accumulator (48 bits)

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1.3.2 SIC/XE Machine Architecture (cont’d)
•There is a 48-bit floating-point data type

1 11 36
s exponent fraction

f * 2(e-1024)
The sign of floating-point number is indicated by the value of s (0 = positive, 1 = negative)

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1.3.2 SIC/XE Machine Architecture (cont’d)

• Instruction Formats
•15 bits in (SIC), 20 bits in (SIC/XE)
8
Format 1 (1 byte) op

8 4 4
Format 2 (2 bytes) op r1 r2

Formats 1 and 2 are instructions that do not reference memory at all

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1.3.2 SIC/XE Machine Architecture (cont’d)
Format 3 (3 bytes)
6 1 11111 12
e =0 : format 3
op n i x b p e disp e =1 : format 4

Format 4 (5 bytes)
6 1 11111 20
op n i x b p e address

Mode Indication Target address calculation

Base relative b=1,p=0 TA=(B)+disp (0≤disp ≤4095)
Program-counter
b=0,p=1 TA=(PC)+disp (-2048≤disp ≤2047)
relative
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1.3.2 SIC/XE Machine Architecture (cont’d)

• Format 3 and 4

mode Bit n Bit i Target address

immediate addressing 0 1 Operand value
indirect addressing 1 0 The word at the location given the target address
simple address 0 0 The target address is taken as the location of the
1 1 operand
1.3.2 SIC/XE Machine Architecture (cont’d)
•Instruction Formats
• See Figure 1.1, P. 11.

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1.3.2 SIC/XE Machine Architecture (cont’d)
• Instruction Set
– Instructions to load and store the new registers
• LDB, STB, etc.
– Floating-point arithmetic operations
• ADDF, SUBF, MULF, DIVF
– Register move instruction
• RMO
– Register-to-register arithmetic operations
• ADDR, SUBR, MULR, DIVR
– Supervisor call instruction
• SVC

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1.3.2 SIC/XE Machine Architecture (cont’d)

• Input and Output

• There are I/O channels that can be used to perform input and output
while the CPU is executing other instructions
• SIO, TIO, and HIO are used to start, reset, and halt the operation of I/O
channels

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1.3.2 SIC Programming Examples
• Figure 1.2
– Sample data movement operations
• Figure 1.3
– Sample arithmetic operations
• Figure 1.4
– Sample looping and indexing operations
• Figure 1.5
– Sample looping and indexing operations
• Figure 1.6
– I/O
• Figure 1.7
– Subroutine call

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1.4 Traditional (CISC) Machines

•The machines as Complex Instruction Set Computers (CISC)

•CISC machines have relatively large and complicated instruction
set, several instruction formats, lengths, and many different
addressing modes.
•The implementation of hardware tends to be complex
• VAX architecture
• Intel x86 architecture
1.4.1 VAX Architecture

•The VAX family of computers was introduced by Digital

Equipment Corporation (DEC) in 1978.
•The VAX architecture was designed for compatibility with earlier
PDP-11 machine
1.4.1 VAX Architecture (cont’d)

•Memory
• 8-bits bytes
• Two consecutive bytes form a word.
• Four consecutive bytes form a longword.
• Eight consecutive bytes form a quadword.
• Sixteen consecutive bytes form an octaword.
•All VAX programs can operate in a virtual address space of 232
bytes.
• Half of the virtual address for OS (system space); the other half is called
process space
1.4.1 VAX Architecture (cont’d)
•Registers
• The VAX machine has 16 general-purpose registers, denoted by R0 through
R15.
• All general registers are 32 bits in length.
• R15 is the “program counter” (PC).
• R14 is the stack pointer (SP).
• R13 is the frame pointer (FP)
• R12 is the argument pointer (AP)
• R6 to R11: General purpose
• R0 to R5 : General Purpose/Special Purpose
• Processor status longword (PSL): contain state variable and flags
1.4.1 VAX Architecture (cont’d)
•Data Format
• Integers are stored in bytes, words, longs, quads, or octets. 2’s complement is used
for negative values
• Characters are stored in 8-bit ASCII code.
• There are four different floating-point data formats, ranging in length from 4 to 16
bytes.
• Packed decimal: each byte represents two decimal digits, each digit encoded using
4 bits of the byte. The sign is encoded in the last 4 bits.
• Numeric: used to represent numeric with one digit per byte, sign may appear in the
last byte (tailing numeric) or separate byte preceding the first digit (leading
separate numeric)
• queues and variable-length bit strings.
1.4.1 VAX Architecture (cont’d)

•Instruction Formats
• Variable-length instruction format.
• Operand (one or two bytes) and up to six “operand specifiers” depending
on the instruction type.
1.4.1 VAX Architecture (cont’d)

•Addressing Mode
• Register mode
• Register deferred mode
• Autoincrement and Autodecrement modes
• Base-relative addressing modes: program counter-relative modes.
• All addressing modes can contain an index register.
• Specifying Indirect Addressing Modes (called deferred model)
• Immediate operator and many application-specific addressing modes.
1.4.1 VAX Architecture (cont’d)

•Instruction Set
• A prefix that specifies the type of operator.
• A suffix that specifies the type of operands.
• A modifier (on some instructions) that given the number of operands
involved.
1.4.1 VAX Architecture (cont’d)

•Input and output

• Inputs and outputs are accomplished by I/O device controllers.
• Each controller has a set of control/status and data registers, which are
assigned locations in physical address space. The portion of the address
space into which the device controller registers are mapped is called I/O
space.
1.4.2 Pentium Pro Architecture

•The Pentium pro microprocessor (the end of 1995) is the latest in

the Intel x86 family.
•x86 family are presently used in a majority of PC and there is a
vast amount of software.
1.4.2 Pentium Pro Architecture (cont’d)

•Memory
•At the physical level, memory consists of 8-bit bytes.
• Two consecutive bytes form a word.
• Four consecutive bytes form a double-word (also called a dword).
•Programmers usually view the x86 memory as a collection of
segments.
• The address will contain two parts: the number of the segment and the
offset of the segment.
• The segment/offset address automatically into physical byte address by
the x86 Memory Management Unit (MMU).
1.4.2 Pentium Pro Architecture (cont’d)
•Registers
• Eight general-purpose registers: EAX, EBX, ECX, EDX, ESI, EDI, EBP,
and ESP (all 32 bits long).
• EAX, EBX, ECX, and EDX are generally used for data manipulation. The
other 4 registers can also be used to data or hold address.
• FLAGS is a 32-bit register that contains many different bit flags.
• 6 16-bit Segment registers are used to locate segments in memory.
• CS contains the address of the currently executing code segment.
• SS contains the address of the current stack segment.
• DS, ES, FS, and GS indicate the address of the data segment.
• Floating-point unit(FPU): eight 80bit data register and serval other control
and status registers
1.4.2 Pentium Pro Architecture (cont’d)

•Data Formats
• The x86 architecture provides storage for integers, floats, characters, and
strings.
• The last significant part of a numeric is stored at the lowest-numbered
address (little-endian byte ordering)
• Integers can be sotred in binary code decimal (BCD)
• The FPU can handle 64-bit signed integers.
• The x86 architecture has three different floating-point data formats.
• The single-precision format is 32 bits long.
• The double-precision format is 64 bits long.
• The extended-precision format is 80 bits long.
1.4.2 Pentium Pro Architecture (cont’d)

•Instruction Format
• All the x86 machine instructions use variations of the same basic format
• Prefixes
• Opcodes (one or two bytes)
• Following the opcode are a number of bytes that specify the operands and addressing
modes to be used.
1.4.2 Pentium Pro Architecture (cont’d)

•Addressing Mode
• An operand value may be specified as part of the instruction itself
(immediate mode), or stored in a register (register mode).
• TA = (base register) + (index register) * (scale factor) + displacement
scale factor: 1, 2, 4 or 8
displacement: 8-, 16-, or 32-bit value
1.4.2 Pentium Pro Architecture (cont’d)

•Instruction Set
• Over 400 different machine instructions
• Each instruction may have zero, one, two, or three operands.
• Register-to-register instructions
• Register-to-memory instructions
• Memory-to-memory instructions
1.4.2 Pentium Pro Architecture (cont’d)

•Input and Output

• Input is performed by instruction that transfer one byte, word, or
doubleword at a time from I/O port to register EAX.
• Output instruction transfers one byte, word, or doubleword from EAX to an
I/O port.
• Repetitioned prefixes allows these instructions to transfer an entire string in
a single operation.
1.5 RISC Machines

•Reduced Instruction Set Computer (RISC)

•The RISC concept developed in the early 1980s.
•To simplify the design of processors
• Faster
• Less expensive
• Greater reliability
• Faster instruction execution times
1.5 RISC Machines (cont’d)

•Standard and fixed instruction lengths.

•Single-cycle execution of most instructions.
•Memory access is usually done by loaded and stored instructions.
•All instructions are register-to-register operations.
•The number of general-purpose registers is relatively large.
•The number of machine instructions, instruction formats, and
addressing modes is relatively small.
1.5.1 UltraSPARC Architecture

•Sun Microsystems in 1995

•The name SPARC stands for scalable processor architecture
•Suitable for a wide range of implementations, from
microcomputers to supercomputers
1.5.1 UltraSPARC Architecture (cont’d)

•Memory
• Memory consists of bytes of eight bits in length.
• Two consecutive bytes form a halfword.
• Four consecutive bytes form a word.
• Eight consecutive bytes form a doubleword.
• UltraSPARC programs can use 264 bytes of virtual memory.
• The address space is divided into pages; multiple page sizes are supported
1.5.1 UltraSPARC Architecture (cont’d)

•Registers
• Very large number of register files
• More than 100 general-purpose registers
• A program can only access 32 registers (r0 through r31).
• The first eight registers (r0 through r7) are global.
• The other 24 registers available to a procedure can be visualized as a
windows through which part of the register file can be seen
• There widows overlap, some registers in the register file are shared between procedures.
This facilitates the passing of parameters
1.5.1 UltraSPARC Architecture (cont’d)
• In the original SPARC architecture, the general-purpose registers were 32
bits long, Later implementation expanded to 64 bits
• Floating-point unit (FPU) contains a file of 64 double-precision floating-
point registers, and several other control and status registers
• Program counter PC, condition code registers, and a number of other
control registers
1.5.1 UltraSPARC Architecture (cont’d)
•Data formats
• Integers, floating point values, and characters.
• Integers are stored as binary values of 8, 16, 32, or 64 bits.
• In original SPARC, the most significant part of numeric value is stored at the
lowest-numbered address (big-endian byte ordering)
• Three different floating-point data formats
• single-precision (single-precision) format is 32 bits long, has 23 bits for floating-point values
and 8 bits for exponential values.
• The double-precision format is 64 bits long, has 52 bits for floating-point values and 11 bits
for exponential values..
• The quad-precision format has 63 bits for floating-point values and 15 bits for exponential
values.
• Characters are stored one per byte, using 8-bit ASCII codes.
1.5.1 UltraSPARC Architecture (cont’d)

•Instruction Formats
• The length is 32 bits. The first 2 bits of the instruction word identify which
format is being used
• Format 1 is used for the Call instruction.
• Format 2 is used for branch instructions.
• The remaining instruction using Format 3, which provides for register loads and stores,
and three-operand arithmetic operations.
1.5.1 UltraSPARC Architecture (cont’d)

•Addressing Modes
• Immediate mode: operand value may be specified as part of the instruction
• Register direct mode: operand value in the register
Mode Target address calculation
PC-relative TA=(PC) + displacement (30 bits, signed)
Register indirect with displacement TA=(register) + displacement (13 bits, signed)
Register indirect indexed TA=(register-1) + (register-2)

PC-relative mode is used only for branch instruction

1.5.1 UltraSPARC Architecture (cont’d)

•Instruction set
• Fewer than 100 machine instructions
• The only instructions that have access to memory are the load and store
instructions.
• All other instructions operate from register to register.
• “pipelined” : one instruction is being executed, the next one is being
fetched from memory and decoded
• Branch instruction might cause the process to “stall”
• Special-purpose instruction for operating systems and optimizing compiler
1.5.1 UltraSPARC Architecture (cont’d)

•Inputs and outputs

• Communication with I/O devices is accomplished through memory.
• A range of memory locations is logically replaced by device registers.
• Each I/O device has a unique address or a set of addresses.
• When a load or store instruction refers to this device register area of
memory, the corresponding device is activated.
1.5.2 PowerPC Architecture

•POWER architecture first introduced by IBM, in early 1990 with

RS/6000
•POWER (Performance Optimization With Enhanced RISC)
•In October 1991 , IBM, Apple, and Motorola formed an alliance
to develop and market such microprocessors, which named
PowerPC
1.5.2 PowerPC Architecture (cont’d)

•Memory
• 8-bit bytes
• Two consecutive bytes form a halfword.
• Four consecutive bytes form a word.
• Eight consecutive bytes form a doubleword.
• Sixteen consecutive bytes form a quadword.
• PowerPC programs can use 264 bytes of virtual memory.
• This address is divided into fixed-length segments, which 256 megabyte long.
• Each segment is divided into pages, which are 4096 bytes long.
1.5.2 PowerPC Architecture (cont’d)

•Registers
• There are 32 general purpose registers in the PowerPC architecture,
designated GPR0 through GPR31.
• Each register is 64 bits long.
• Floating-point operations can be performed in the floating-point unit, which
contains 32 64-bit floating-point registers, and a state and control register.
• 32-bit conditional registers, this register is divided into eight 4-bit subfields,
named CR0 through CR7.
• Link Register (LR), and Count Register (CR) used by some branch
instructions
1.5.2 PowerPC Architecture (cont’d)

•Data Formats
• Provides storage space for integers, floating point numbers, and characters.
• Integers can be 8-, 16-, 32-, or 64-bit binary values, and both positive and
negative signed and unsigned integers are supported; negative numbers are
represented as 2's complement.
• There are two different floating-point data formats.
• The single-precision format is 32 bits long. 23 bits of floating-point value and 8-bits
exponent.
• The double-precision format is 64 bits long. 52 bits of floating-point value and 11-bits
exponent.
• Characters are stored one per byte, using 8-bit ASCII codes.
1.5.2 PowerPC Architecture (cont’d)

•Instruction Formats
• There are seven basic instruction formats in the PowerPC architecture,
some of which have subformats.
• All formats are 32 bits long.
• Instructions must be aligned to the start of a byte boundary (i.e., a byte
address that is a multiple of 4).
• The first 6 bits of the instruction word always specify the opcode; some
instruction formats also have an additional “extended opcode” fields.
1.5.2 PowerPC Architecture (cont’d)

•Addressing Modes
• Immediate mode: operand value may be specified as part of the instruction
• Register direct mode: operand value in the register
• Load and store operations use one of the following three addressing modes
Mode Target address calculation
Register indirect TA=(register)
Register indirect with index TA=(register-1) + (register-2)
Register indirect with immediate index TA=(register) + displacement (16bits, signed)
1.5.2 PowerPC Architecture (cont’d)
• Branch instructions use one of the following three addressing modes

Mode Target address calculation

Absolute TA = actual address
Relative TA = current instruction address + displacement (25 bits, signed)
Link Register TA = (LR)
Count Register TA = (CR)
1.5.2 PowerPC Architecture (cont’d)

•Instruction Set
• Approximately 200 machine instructions
• Instructions are executed using a pipeline approach.
• “branch prediction” used to speed execution
1.5.2 PowerPC Architecture (cont’d)

•Inputs and outputs

• 2 different methods for performing I/O
• The segments in the virtual address space are mapped onto an external
address space (typically an I/O bus), called direct-store segments.
• A reference to an address that is not in a direct-store segment represents a
normal virtual memory access.
1.5.3 Cray T3E Architecture

•The T3E series of supercomputers was announced by Cray

Research, Inc., near the end of 1995.
•T3E is a massively parallel processing (MPP) system
•T3E system contains a large number of processing elements (PE),
arranged in a three-dimensional network Interconnect

•Each PE consists of a DEC Alpha EV5 RISC

network

microprocessor, local memory, and performance-

accelerating control logic, A T3E may contain 16 Processing element
node
to 2048 PEs
1.5.3 Cray T3E Architecture (cont’d)

•Memory
• Each processing unit has its own local memory, with a capacity ranging
from 64M bytes to 2G bytes.
• System memory is physically dispersed in each PE.
• Memory within each processing element consists of 8-bit bytes, all
addresses used are byte addresses. Two consecutive bytes from a word; four
consecutive bytes from a longword, eight consecutive bytes from a
quadword.
1.5.3 Cray T3E Architecture (cont’d)

•Registers
• The Alpha architecture contains 32 general-purpose registers, numbered
from R0 to R31; R31 usually stores the value 0.
• Each general-purpose register is 64 bits long.
• There are also 32 floating-point registers, numbered from F0 to F31; F31
normally stores the value 0. Each floating-point register is 64 bits long.
• 64-bit registers, such as program counters PC and serval other state and
control registers.
1.5.3 Cray T3E Architecture (cont’d)

•Data Formats
• Storage space for integers, floating point numbers, and characters.
• Integers are stored as longwords or quadwords.
• 2's complement is used for negative values.
• There are two different types of floating-point formats in the Alpha
architecture. One group of three formats is included for compatibility with
the VAX architecture. The other group consists of four IEEE standard
formats.
• Characters are stored one per byte, using 8-bit ASCII codes.
1.5.3 Cray T3E Architecture (cont’d)

•Instruction Formats
• There are five basic instruction formats, some of which have subformats.
• All formats are 32 bits long.
• The first six bits of an instruction word always specify the opcode.
• Some instruction formats have an additional “function” field.
1.5.3 Cray T3E Architecture (cont’d)

•Addressing Modes
• Immediate mode: operand value may be specified as part of the instruction
• Register direct mode: operand value in the register
• The only instructions that address memory are load, store, and branch
operations.
• Operands in memory are addressed using one of the following two modes
Mode Target address calculation
PC-relative TA=(PC) + displacement (32 bits, signed)
Register indirect with displacement TA=(register) + displacement (16 bits, signed)
1.5.3 Cray T3E Architecture (cont’d)

•Instruction Set
• Approximately130 machine instructions
• There are no bytes or word load and store instructions.
• Memory access interface does not need to include shift-and-mask
operations.
1.5.3 Cray T3E Architecture (cont’d)

•Inputs and outputs

• Performs I/O through multiple ports into one or more I/O channels.
• These I/O channels can be organized in a number of ways, such as
integrated into the network that interconnects the processing nodes.
• A system may be configured with up to one I/O channel for every eight PEs.
• All channels are accessible and controllable from all PEs.