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3-MICROPROCESSOR BASICS: REGISTERS AND MEMORY
CP216 Introduction to Microprocessors
Spring 2025
CP216 Introduction to Microprocessors PAGE 1 Wednesday, May 14, 2025
Microprocessor Basics
❑ Outlines Ask AI to create a structured note template for these topics!
3 o Instruction Execution Cycles
o Single-Cycled and Pipelined Processors
o The Load/Store Architecture
o Processor Registers
o Memory Hierarchy
o Microprocessor Architecture Technologies
❑ Objectives
o Explain single-cycle microprocessor architecture
o Identify the different Processor Registers and Memory levels.
CP216 Introduction to Microprocessors PAGE 2 Wednesday, May 14, 2025
Microprocessor Basics
Components of a Computer
▪ In order to build a computer, we need to specify its Instruction Set Architecture.
▪ The Instruction Set Architecture shapes the architecture and defines the programmers’ view of :
▪ Instructions (Types/Operations; Size and Formats; Addressing Modes)
▪ Registers (size; count; function)
▪ Memory (Memory size; word size)
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Microprocessor Basics
Instruction Execution Cycles: “Different From Memory Accesses”
▪ A program is made from instructions.
▪ Instructions are the primitive operations that the CPU may execute.
▪ An instruction is represented by a number (called: machine code or instruction word) and stored
in the main memory
▪ Basic job of a CPU: execute lots of instructions.
Fetch
▪ The execution of an instruction requires:
Execute Decode
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Microprocessor Basics
Instruction Execution Cycles
▪ Each instruction may take more than 3 cycles to be completed depending
mainly on the Data Memory access
Single-cycle processor
Pipelined processor
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Microprocessor Basics
Instruction Execution Cycles
▪ Instruction fetch (IF).
▪ Instruction decode/Register fetch (ID).
▪ Execution/Effective address (EX).
▪ Memory access (MEM)
▪ Write-back (WB)
This figure summarizes the cycles as:
▪ Load (5 cycles)
▪ Store (4 cycles)
▪ R-type (4 cycles)
▪ Branch (3 cycles)
▪ Jump (3 cycles) Single Cycle MIPS Instruction Execution Cycles
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Microprocessor Basics
The Load/Store Architecture
▪ In load/store architecture, only load and store ▪ Memory access breakdown:
instructions transfer data between memory and ▪ Load/store instructions: 2 memory accesses each.
registers.
▪ Arithmetic instructions: 1 memory access (instruction fetch only).
▪ Arithmetic instructions operate only on registers.
▪ Execution time ≠ memory access count:
▪ Benefits:
▪ Overlapped execution (like pipelining) can reduce actual
▪ Simplifies instruction design. execution time.
▪ Reduces instruction size, especially with 32-bit memory ▪ RISC architectures are optimized for such overlapping.
addresses.
A comparison of the instruction size when the operands are in registers versus memory.
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Microprocessor Basics
The Load/Store Architecture
▪ Move data into registers first before processing.
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Microprocessor Basics
Microprocessor Architecture
Single-Cycle MIPS
Processor Architecture
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Microprocessor Basics
Microprocessor Architecture
▪ Trace Instruction: 0x400: lw $10, 32 ($5) [format: lw $rt, sign-imm($rs)]
▪ Step1. Fetch instruction from Instruction ▪ Step 2. Read source operand rs ($5) from Register
File (RF)
Memory (IM) using PC value
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Microprocessor Basics
Microprocessor Architecture
▪ Trace Instruction: 0x400: lw $10, 32 ($5) [format: lw $rt, sign-imm($rs)]
▪ Step 3. Sign-extend immediate value (32) ▪ Step 4. Compute target memory address
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Microprocessor Basics
Microprocessor Architecture
▪ Trace Instruction: 0x400: lw $10, 32 ($5) [format: lw $rt, sign-imm($rs)]
▪ Step 5. Read data from Data Memory (DM) ▪ Step 6. Determine address of next instruction PC’
and write it back to target register rt ($10)
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Microprocessor Basics
Microprocessor Architecture
▪ Trace Instruction: 0x404: sw $17, 4($9) [format: sw $rt, sign-imm($rs)]
▪ Step1. Compute the address same as for lw instruction ▪ Step2. Write data in rt ($17) to memory
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Microprocessor Basics
Microprocessor Architecture
▪ Trace Instruction: 0x800: add $16, $17, $18 [format: add $rd, $rs, $rt]
▪ Step1. Read from rs ($17) and rt ($18) ▪ Step2. Write ALUResult to Register File at rd ($16)
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Microprocessor Basics
Processor Registers
▪ Processors contain multiple registers for storing data, instructions, and state information.
▪ Registers are classified into:
• Special-purpose registers examples:
▪ General-purpose registers. • IA-32: Has registers for managing the processor stack.
▪ Special-purpose registers: • Most processors have:
• An instruction register (holds the current instruction).
▪ Some are user-accessible. • A program counter (points to the next instruction).
▪ Others are reserved for system use.
▪ Technology influences the design and function of the register set.
▪ Instruction format (number of addresses) affects register needs:
▪ Stack machines need fewer or no data registers, as the stack serves that role.
▪ Three- and two-address machines may not require internal registers, but using them improves performance by reducing memory
accesses.
▪ RISC machines typically include a large set of registers for efficiency.
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Microprocessor Basics
Memory
▪ Memory: A collection of storage cells together with
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the necessary circuits to transfer information to and
from them.
▪ Random Access Memory (RAM): A memory
organized such that data can be transferred to or
from any cell (or collection of cells) in a time that is
not dependent upon the particular cell selected.
▪ Memory Address: A vector of bits that identifies a
particular memory element (or collection of
elements).
▪ Memory Word: A collection of binary bits whose size
is a typical unit of access for the memory. It is
typically a power of two multiple of bytes (e.g., 1
byte, 2 bytes, 4 bytes, 8 bytes, etc.)
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Microprocessor Basics
Memory
A basic memory system consists of
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1. Address Bus
▪ k address lines are decoded to address 2k words of memory.
2. Data Bus
▪ Each word is n bits.
3. Control Bus
▪ Read and Write are single control lines defining the simplest
of memory operations.
▪ Chip Select (cs) control is used to expand the memory by
adding more chips.
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Microprocessor Basics
Memory Hierarchy
▪ Store everything on disk
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▪ Copy recently accessed (and nearby) items from disk to smaller DRAM memory
▪ Main memory
▪ Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory
▪ Cache memory is part of the CPU and it is the fastest type of memory.
▪ Register: Registers are located inside CPU and hold.
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Microprocessor Basics
Memory Hierarchy
▪ Core i7 Cache
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Memory
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Microprocessor Basics
Microprocessor Architecture Technologies
▪ Harvard Architecture
▪ Von Neumann Architecture ▪ Uses separate buses for instructions and data.
▪ Single memory for both instructions (program ▪ The instruction address bus and instruction bus are
code) and data. used for reading instructions from memory.
▪ Uses the data bus to transfer data and instructions ▪ The address bus and data bus are used for writing
from the memory to the CPU. and reading data to and from memory.
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Microprocessor Basics
Microprocessor Architecture Technologies
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References
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Textbook: James S. Walker, “Computer Organization & Architecture: Themes and Variations.”
1st Ed., Cengage, 2014. ISBN: 9780357694985.
Textbook: Harris and Harris, “Digital Design and Computer Architecture”. 2nd Ed, Morgan
Kaufmann, 2012, ISBN 0123944244.
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