Standard Cell Architecture • Filler cells maintain continuity of wells, rails,

and meet DRC spacing rules when gaps

By Garima Jangid exist.
1. Definition & Role
3. Logical & Drive Variants
A standard cell is a small, pre-designed logic
Cell Function Drive Strength Variants
building block used in ASIC and SoC
INV Inverter INV_X1, INV_X2, INV_X4,
implementation. Each cell is optimized for:
INV_X8
• Area
NAND2 2-input NAND2_X1, NAND2_X2,
• Performance (timing)
NAND NAND2_X4
• Power
• Manufacturability (DFM compliance)
DFF D Flip-Flop DFF_X1, DFF_X2
They form the backbone of semi-custom digital Higher drive → larger transistors → more width →
design, where full custom layout is avoided except more dynamic power.
for memories, analog blocks, or very high-
performance paths. 4. Layout Abutment Rules
• Cells are designed to abut seamlessly.
• N-well and P-well boundaries align.
2. Physical Structure in Detail
• Power rails overlap.
2.1 Cell Height & Track-Based Architecture
• This minimizes dead space and improves
• Cells are characterized by their height,
density.
expressed in "tracks."
• A "track" refers to the pitch of metal routing
tracks. 5. Benefits
• Automation: Enables P&R tools to assemble
• Common architectures:
o 7.5T cell → high density, used in
complex chips.
• Scalability: Easier migration to new nodes.
mobile/low-power.
• Consistency: Predictable timing/power
o 9T cell → taller, allows more routing
resources, used for high- models.
• Manufacturability: DRC-clean by
performance.
• All cells in a library share the same height → construction.
enables row-based placement.
2.2 Power Rails 6. Detailed Cross-Section Example
• At the top: VDD rail (Metal-1).
Metal-2 routing tracks
• At the bottom: VSS/GND rail (Metal-1). -----------------------
• Rails are continuous across a row to ensure Metal-1 routing tracks (pins)
proper power distribution. -----------------------
• Strap cells or tap cells are inserted to VDD rail (Metal-1)
connect these rails to higher metal layers. -----------------------
PMOS transistors (N-well)
2.3 Transistor Placement
-----------------------
• Standard cells use CMOS:
Boundary (contact)
o PMOS in N-well (upper half).
-----------------------
o NMOS in P-substrate (lower half).
NMOS transistors (P-substrate)
• The boundary between PMOS/NMOS is
-----------------------
fixed.
VSS rail (Metal-1)
2.4 Pin Placement
-----------------------
• Input/Output pins are placed on Metal-1,
Silicon substrate
aligned to routing tracks.
• Pin accessibility is crucial for routability;
7. Challenges
poor pin access → congestion.
• At advanced nodes:
2.5 Well Taps and Filler Cells
o Pin accessibility issues.
• Well taps tie wells to VDD/VSS.
o Double/quad patterning constraints.
 o Cell libraries must support multiple o High density → very small cell
voltage domains. height.
o Lithography restrictions (e.g., o Less metal space → routing
FinFET). congestion.
o Poor drive → slower timing.
8. Comparison of Standard Cell Architectures o Typically used in very low-power IoT
(4T, 6T, 7T, 7.5T, 9T, etc.) or simple chips.
In VLSI, standard cell libraries are often described in • Medium Track (7T, 7.5T):
terms of their track height (T). This number o Balanced trade-off between density
indicates how many metal routing tracks fit within and performance.
the cell height and directly affects density, o Most commonly used for mobile
performance, power, and routability. processors and general-purpose
SoCs.
8.1. What does “T” mean? • Large Track (9T, 10.5T):
• T = Track Pitch: The vertical height of a o More transistor width → stronger
single routing track (metal pitch). drive → faster speed.
• Cell Height = T × Track Pitch. o More metal routing tracks → easier
• Example: If metal pitch = 40 nm, a 7.5T cell to close timing.
→ height = 7.5 × 40 nm = 300 nm. o Lower density, higher power.
o Used in high-performance cores
8.2. Architecture Comparison Table (server CPUs, GPUs).
Feature 4T 6T 7T / 9T
7.5T 8.4. Visual Layout Difference (Conceptual)
Cell Very Smal Medium Large 4T: [VDD][PMOS][NMOS][GND]
Height small l 6T: [VDD][PMOS area][NMOS area][routing][GND]
Density Highes High Modera Low 7.5T: [VDD][PMOS+extra routing][NMOS+extra
t te routing][GND]
Performa Poor Bett Good Excellent 9T: [VDD][Wide PMOS][Routing][Wide
nce er NMOS][GND]
Drive Very Low Medium High
Strength low
Leakage Lowes Low Modera Higher
Power t te
Dynamic Very Low Modera High
Power low te
Routing Extre Limit Adequa Plenty
Resources mely ed te
limited
Pin Difficul Hard Good Best
Accessibili t er
ty
Usage Ultra- Low- Mainstr High-
low- pow eam perform
power er SoCs ance
desig CPUs/GP
ns Us
Manufact Older Lega 28nm High-
uring (>180 cy / → 7nm end
Node nm) IoT (FinFET)

8.3. Trade-offs
• Smaller Track (4T, 6T):