Module III

Sequential logic circuits: Distinguish Combinational and Sequential circuits. Flip Flops – SR
latch and flip flop using NAND gate- symbol and truth table, Edge triggering and Level
triggering, JK flip flop – logic symbol and truth table, Asynchronous inputs- Preset and Clear,
JK-Master slave flip flop –logic symbol and truth table, D and T flip flops from JKFF- logic
symbol and truth table Shift registers - Serial in Serial out, Parallel in Parallel out, Serial in
Parallel out, Parallel in Serial out. Applications of Shift Registers - Ring counter, Johnson
counter.

SEQUENTIAL LOGIC CIRCUITS

The sequential circuit is a special type of circuit that has a
series of inputs and outputs. The outputs of the sequential
circuits depend on both the combination of present inputs and
previous outputs. The previous output is treated as the present
state. So, the sequential circuit contains the combinational
circuit and its memory storage elements.

Distinguish Combinational and Sequential circuits

Combinational Circuits Sequential Circuits

The outputs of the combinational circuit The outputs of the sequential circuits depend on
depend only on the present inputs. both present inputs and present state (previous
output).
The feedback path is not present in the The feedback path is present in the sequential
combinational circuit. circuits.
In combinational circuits, memory elements In the sequential circuit, memory elements play
are not required. an important role and require.
The clock signal is not required for The clock signal is required for sequential
combinational circuits. circuits.
The combinational circuit is simple to It is not simple to design a sequential circuit.
design.
Basics of Flip Flop

A flip-flop is a sequential digital electronic circuit having two stable states that can be used to
store one bit of binary data. These stable states are used to store binary data that can be changed
by applying varying inputs. The flip flops are the fundamental building blocks of the digital
system. Flip flops and latches are examples of data storage elements. In the sequential logical
circuit, the flip flop is the basic storage element.

SR latch

An SR Latch has two inputs S and R and two outputs Q

and 𝑄̅ . The state of this latch is determined by the
condition of Q. If Q is 1 the latch is said to be SET and if
Q is 0 the latch is said to be RESET. This SR Latch or Flip flop can be designed either by two
cross-coupled NAND gates or two-cross coupled NOR gates.

When S = 1 and R = 0
NOR gate always gives output 0 when at least one of the inputs is 1.
• When S is applied as 1 the output of gate G2 i.e. 𝑄̅ is 0
irrespective of the condition of second input Q to the gate.
• Now 𝑄 ̅ is the input of gate G1 so both the inputs of G1
become 0. So, the output of G1 is now 1.
• So whatever may be the previous condition of Q, it always
becomes Q = 1 and 𝑄̅ = 0. This is called the SET condition
of the latch.
When S = 0 and R = 1
• When R is applied as 1, the output of gate G1 i.e. Q is 0 irrespective of the condition of
the second input 𝑄̅ to the gate.
• This 0 is then fed back to the input of gate G2. As here S is already 0, both inputs of G2
are 0. Hence the output of G2 i.e. 𝑄̅ will be 1. So, Q = 0 and 𝑄̅ = 1 This is called the
RESET condition of the latch.
When S = 0 and R = 0
• First suppose Q is previously 1.
• Now the inputs of G2 are 0 and 1. So output of G2 i.e. 𝑄 ̅ is 0.
• Now both inputs of G1 are 0. So the output of G1 i.e. Q is 1.
• Now suppose Q is previously 0.
• Now both inputs of G2 are 0. So the output of G2 i.e. 𝑄 ̅ is 1.
• Now the inputs of G1 are 0 and 1. So the output of G1 i.e. Q is 0.
• So it is proved that Q remains the same as it is when S = 0 and also R = 0
When S = 1 and R = 1
• When S is applied as 1 the output of gate G2 i.e. 𝑄 ̅ is 0 irrespective of the condition of
second input Q to the gate.
• When R is applied as 1, the output of gate G1 i.e. Q is 0 irrespective of the condition of
the second input 𝑄̅ to the gate
So, when both S and R are 1, it becomes unpredictable or invalid.

Clock signal

A clock signal is a periodic signal in which ON time

and OFF time need not be the same. When ON time
and OFF time of the clock signal are the same, a
square wave is used to represent the clock signal.
Types of Triggering

These are two types of triggering in sequential circuits:

Level triggering

The logic High and logic Low are the two levels in the clock signal. In level triggering, when the
clock pulse is at a particular level, only then the circuit is activated. There are the following types
of level triggering:

Positive (HIGH) level triggering

In a positive level triggering, the signal with

Logic High occurs. So, in this triggering, the
circuit is operated with such type of clock
signal.

Negative (LOW) level triggering

In negative level triggering, the signal with Logic

Low occurs. So, in this triggering, the circuit is
operated with such type of clock signal.

Edge triggering

In clock signal of edge triggering, two types of transitions occur, i.e., transition either from Logic
Low to Logic High or Logic High to Logic Low.

Based on the transitions of the clock signal, there are the following types of edge triggering:

Positive edge triggering

The transition from Logic Low to Logic High occurs in

the clock signal of positive edge triggering. So, in positive
edge triggering, the circuit is operated with such type of
clock signal

Negative edge triggering

The transition from Logic High to Logic low occurs in the

clock signal of negative edge triggering. So, in negative edge
triggering, the circuit is operated with such type of clock
signal
SR Flip-flop

The SR flip flop stands for "Set-Reset" flip flop. The SR flip
flop is a 1-bit memory bistable device having two inputs, i.e.,
SET and RESET. The SET input 'S' set the device or produce the
output 1, and the RESET input 'R' reset the device or produce the
output 0.

Symbol

Circuit Diagram Truth Table

When S = 0, R = 0
When the clock pulse is applied, the output of NAND gates A and B are 1. For this case, if Q =
0, Q’ = 1, then both the inputs for NAND gate C are 1 and the output thus produced by gate C is
Q+1 =0. The present state output is Q = 0 and the next state output is Q+1 = 0. Thus the state has
no change.
When S = 0, R = 1
When the clock pulse is applied, the output of NAND gates A and B are 1 and 0. The input of
NAND gate D is 0 and the output thus produced by gate D is Q’+1 =1. For this case, whether the
present state is either 0 or 1, it will produce an output 0, which will RESET the flip flop.

When S = 1, R = 0
When the clock pulse is applied, the output from the NAND gate A and B are 0 and 1. The input
of NAND gate C is 0 and the output thus produced by gate C is Q+1 =1. For this case, whether
the present state is either 0 or 1, it will produce an output 1, which will SET the flip flop.

When S = 1, R = 1
When the clock pulse is applied, the output from the NAND gate A and B are 0. The output thus
produced by gate C and D are 1. For this case, it is observed that the next state output Q +1 = 1
and Q’+1 = 1. This is an impossible output because Q and Q’ should be complement with each
other. So it is an indeterminate or invalid state.

D flip flop

It is one of the most widely used flip – flops. It has a clock signal
(Clk) as one input and Data (D) as other. There are two outputs and
these outputs are complement to each other. Here D stands for
“Data” or “Delay”. It is constructed from SR flip flop. The two
inputs (S &R) of the clocked SR flip flop are connected to an
inverter.

If D = 1, then the inputs for the SR flip flop are S = 1, R =0. When you look at the truth table of
SR flip flop, the next state output is logic 1, which will SET the flip flop.

When D = 0, the inputs of SR flip flop will become, S = 0, R = 1. This input combination for the
SR flip lop will produce logic LOW value, which will RESET the flip flop.
JK Flip-Flop
The JK FF is the most popular and is regarded as a universal FF
circuit. The JK FF is simply a gated SR FF designed such that it
avoids the invalid output state that can happen when both inputs S
and R are equal to logic level 1.

Race around condition

In J-K FF, if we make it level triggered, it is very hard to control the toggling of the output Q for
a wider pulse width of clock signal and with J=K= 1 input set. This condition with active level of
clock and J=K= 1 makes output to change continuously ( toggle ) for wider clock width. This
condition is known as race around condition for J-K level trigger latch. This condition makes the
J-K latch less reliable for use since the output is depending on how much it toggles depending on
pulse width of the clock. To avoid this race around condition in JK-latch, one solution is use of J-
K edge triggered FF. But to generate active edge is really tough task. So this edge triggering can
be achieved by Master Slave J-K FF.

Master-Slave J-K FF
Master-slave flip flop is designed using two
separate flip flops. Out of these, one acts as the
master and the other as a slave. The output of the
master J-K flip flop is fed to the input of the slave
J-K flip flop. The output of the slave J-K flip flop is
given as a feedback to the input of the master J-K
flip flop. The input signals J and K are connected to
the gated “master” SR flip flop which “locks” the
input condition while the clock (Clk) input is
“HIGH” at logic level “1”. As the clock input of the
“slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR flip flop
does not toggle. The outputs from the “master” flip flop are only “seen” by the gated “slave” flip
flop when the clock input goes “LOW” to logic level “0”.
T Flip flop
Toggle FF is a JK FF with the J and K input terminals
permanently tied together to make a single input. It has only one
input symbolized by the letter T. If the toggle input is HIGH, the
T flip-flop changes state (toggles) when the clock signal is
applied. If the toggle input is LOW, the T flip-flop holds the
previous state.

Block diagram

Asynchronous inputs- Preset and Clear

The normal data inputs to a flip flop (S, R J, K, D and T) are referred to as
synchronous inputs because they have an effect on the outputs (Q and not-Q) only
with the clock signal transitions.
These extra inputs PRESET and CLEAR are called asynchronous because they can
set or reset the flip-flop regardless of the status of the clock signal. PRESET and
CLEAR are inputs for FFs which are active LOW. PRESET is used to SET Q = 1
while CLEAR is used to set Q=0.

Shift registers
Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store
multiple bits of data, we need multiple flip flops. N flip flops are to be connected in an order to
store n bits of data. A Register is a device which is used to store such information. It is a group
of flip flops connected in series used to store multiple bits of data. A group of flip flops which
is used to store multiple bits of data and the data is moved from one flip flop to another is known
as Shift Register.

Shift registers are basically of 4 types. These are:

1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register

Serial-In Serial-Out Shift Register (SISO) –

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as Serial-In Serial-Out shift register. Since there is only
one output, the data leaves the shift register one bit at a time in a serial pattern, thus the name
Serial-In Serial-Out Shift Register.

Serial-In Parallel-Out shift Register (SIPO)

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as Serial-In Parallel-Out shift register.
The output of the first flip flop is connected to the input of the next flip flop and so on. All
these flip-flops are synchronous with each other since the same clock signal is applied to each
flip flop.
Parallel Input Serial Output (PISO)
In PISO shift register, data is put onto the register in parallel and retrieved from it serially. Here the data
is entered in 1 clock cycle and the output is started from 1st to nth clock cycle for an n-bit word. Shift =
“0” is used for parallel data load while shift = “1” is used for Serial Right Shifting

Parallel-In Parallel-Out Shift Register (PIPO)

The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-Out
shift register.
In this type of register, there are no interconnections between the individual flip-flops since no
serial shifting of the data is required. Data is given as input separately for each flip flop and in
the same way, output also collected individually from each flip flop.
Applications of Shift Registers

Ring counter.
A ring counter is basically a shift register counter in which the output of the first flip flop is
connected to the next flip flop and so on and the output of the last flip flop is again fed back to
the input of the first flip flop, thus the name ring counter. A “PRESET” pulse is applied to the
input of the first flip-flop ( FFA ) before the clock pulses are applied. This then places a single
logic “1” value into the circuit of the ring counter. So on each successive clock pulse, the counter
circulates the same data bit between the four flip-flops

Johnson counter
It is also known as a switch-tail ring counter, walking ring counter, or Johnson counter. It
connects the complement of the output of the last shift register to the input of the first register
and circulates a stream of ones followed by zeros around the ring.