SRM Institute of Science and Technology

Mode of Exam
College of Engineering and Technology
OFFLINE
School of Computing
(Common to all Branches)

DEPARTMENT OF COMPUTING TECHNOLOGIES

SRM Nagar, Kattankulathur – 603203, Chengalpattu District, Tamilnadu

Academic Year: 2023-24 (ODD)

Test: CLAT-1 Date: 18-08-2023

Course Code & Title: 21CSS201T COA Duration: 100 minutes
Year & Sem: II & III SET D Max. Marks: 50

Course Articulation Matrix:

Course
Learning At the end of this course, learners will be PO PO PO PO PO PO PO PO PO PO PO PO
Outcomes able to: 1 2 3 4 5 6 7 8 9 10 11 12
(CLO)
Identify the computer hardware and - - - - - - -
CO-1 how software interacts with computer H M - - -
hardware
Apply Boolean algebra as related to
designing computer logic ,through - - - - - - -
CO-2 H H - - -
simple combinational and sequential
logic circuits

Part – A
(10 x 1 = 10 Marks)
Instructions: Answer all
Q. Question Marks BL CO PO PI
No Code
1. Which of the following is true about Computer Architecture? 1 1 1 2 2.1.2
a) It acts as the interface between hardware and software.
b) Computer Architecture tells us how exactly all the units
in the system are arranged and interconnected.
c) Computer Architecture is concerned with the structure
and behaviour of a computer system as seen by the user.
d) It involves Physical Components

ANS: a)
2 Which among the following is a type of architecture used in the 1 1 1 2 2.1.2
computers nowadays?
a) Microarchitecture
b) Harvard Architecture
c) Von-Neumann Architecture
d) System Design

ANS: c)
3 In which of the following form the computer stores its data in 1 2 1 2 2.1.2
memory?
a) Hexadecimal form
b) Octal form
c) Binary form
d) Decimal form

ANS : c)
4 The two’s complement in binary system is useful for expressing 1 2 1 2 2.1.2
(A) Decimal numbers
(B) Positive numbers
(C) Negative numbers
(D) Binary numbers
 ANS: c)
5 The parity bit is added for the purpose of ___________? 1 3 1 2 2.1.2
(A) Control key
(B) Error detection
(C) Indexing
(D) Coding

ANS: B)

6 Gray codes are used for? 1 2 1 2 2.1.3

a) To count the no of bits changes
b) To rotate a shaft
c) Error correction
d) Error Detection

ANS : c)
7 ASCII codes are required for representing more than ___ 1 1 1 2 2.1.3
characters.
a) 16
b) 8
c) 32
d) 64

ANS: d)
8 Which of the following building block can be used to implement 1 3 1 2 2.1.2
any combinational logic circuit?

a) AND
b) OR
c) NAND
d) XOR

ANS:c)
9 _______ points to the next instructions that are to be fetched 1 2 2 2 2.1.2
from memory.
a) Instruction register
b) Program counter
c) Memory Address Register
d) Memory Data Register
ANS: b)
10 Consider a CPU that has 64- bit, the address of the contents are 1 2 2 1 2.1.2
1000, 1008, 1016, 1024. Now MAR is holding an address is 1008
to fetch the content from the memory. Analyze the operation
and select the following address of the content which is held by
the Program Counter (PC).
a) 1000
b) 1008
c) 1016
d) 1024

ANS: c)
Part – B
( 4 x 4 = 16 Marks)
Instructions: Answer any 4
16 Imagine you're participating in a coding competition, and one 4 2 1 2 2.1.2
of the challenges involves working with binary and gray codes.
In a particular round, you're given the binary code 100110 and
asked to calculate its corresponding gray code. Can you
perform the necessary steps to convert this binary code into a
gray code?

ANS: 110101
17 Convert (6AF)16 to binary and decimal. 4 2 1 2 2.4.1

ANS:

(6AF)16 = (011010101111)2

(6AF)16 = (1711)10

18 Add the numbers 984.6 and 588.3 using BCD Addition method. 4 2 1 2 2.4.1

Carry 11
BCD code for 984.6 : 1001 1000 0100 . 0110
BCD code for 599.3 : 0101 1000 1000 . 0011

Carry 1 1
Addition : 1111 0000 1100 . 1001
If Invalid BCD then add
0110 0110 0110
6:

Addition : 1) 0101 0111 0010 . 1001

0001 0101 0111 0011.1001

So final answer of BCD addition is (1572.9) BCD

19 Imagine you're a computer science professor teaching memory 4 2 2 1 2.1.3

addressing techniques. Covering byte address assignment, you
use visuals to explain different approaches. Illustrate and
explain these approaches with diagrams, aiding students'
understanding of memory organization.

ANS:

Little-Endian:

In little-endian byte order, the least significant byte (LSB) is

stored at the lowest memory address, while the most significant
byte (MSB) is stored at the highest memory address.

Memory Address: | 0 | 1 | 2 | 3 |
Data (4 bytes): | 0x78 | 0x56 | 0x34 | 0x12 |
 The least significant byte (0x12) is stored at the lowest memory
address (0).
The most significant byte (0x78) is stored at the highest
memory address (3).

Big-Endian:

In big-endian byte order, the most significant byte (MSB) is

stored at the lowest memory address, while the least significant
byte (LSB) is stored at the highest memory address.

Memory Address: | 0 | 1 | 2 | 3 |
Data (4 bytes): | 0x12 | 0x34 | 0x56 | 0x78 |

The most significant byte (0x12) is stored at the lowest memory

address (0).
The least significant byte (0x78) is stored at the highest memory
address (3).
20 4 2 2 1 2.1.3

Which part of
the functional
unit of the
computer is
known as
“Brain” ? Justify
your answe
Which part of the functional unit of the computer is known as
“Brain”? Justify your answer

ANS:

The part of the functional unit of the computer that is often

referred to as the "Brain" is the Central Processing Unit
(CPU). The CPU is justified as the brain due to its role in
executing instructions, performing calculations, making
decisions, and coordinating all essential tasks within the
computer. Similar to how the brain processes information, the
CPU manages data flow, controls memory access, and carries
out arithmetic and logic operations. Just as the brain is central
to human decision-making and control, the CPU plays a pivotal
role in the overall functioning and operation of a computer
system.
PART C

( 12 x 2 = 24 Marks)
Instructions: Answer all
21 a) Convert the following. 12 2 1 2 2.4.1
i) Convert Hexadecimal (A4B.59E) to the decimal
form. (3)

ANS:
Decimal equivalent of the hexadecimal number
A4B.59E is approximately 2635.3515625.

ii) Convert Excess-3 (011110100110) to binary (3)

ANS: (110011011011)2.

iii) Convert decimal (325.56)10 to Excess-3. (3)

ANS: (01000011001000110011)XS-3
iv) Convert octal number 292.863 into binary
number.
ANS: (0101001010.1000110011)2
Kindly award marks for this question alone if
student attempted(3 marks)
[OR]
b) i) Mention the two ways of representing signed
numbers. Explain the 1’s and 2’s complement method of
binary subtraction with appropriate examples. (6)

ANS:

Subtraction using 1’s complement: STEPS

1. Obtain 1’s complement of subtrahend
2. Add the result to minuend and call it
intermediate result
3. If carry is generated then answer is positive
and add the carry to Least Significant Digit
(LSD)
4. If there is no carry then answer is negative and
take 1’s complement of intermediate result and
place negative sign to the result.
Example – 1:

Example 2:

Subtraction using 2’s complement: STEPS

1. Obtain 2’s complement of subtrahend
 2.
Add the result to minuend
3.
If carry is generated then answer is positive,
ignore carry and result itself is answer
4. If there is no carry then answer is negative and
take 2’s complement of intermediate result and
place negative sign to the result.
Example 1:

Example 2:

ii) Explain about BCD subtraction depicting both

BORROW and NO BORROW condition. (6)

Binary-Coded Decimal subtraction refers to the process

of subtracting two numbers that are represented in
BCD format. BCD is a binary-encoded representation
of decimal numbers, where each decimal digit is
encoded using a 4-bit binary number. In BCD
representation, each decimal digit (0-9) is represented
by its 4-bit binary equivalent.

Rule: If one 4-bit group needs to take borrow from neighbour,

then subtract 0110 from the group which is receiving borrow.

Example - 1

NO BORROW CONDITION

Example - 2

BORROW CONDITION
22 a) i) Imagine you are a computer systems architect 12 2 2 2 2.4.1
working on designing a new computer system. Your
team is discussing the architecture's components and
their functions. Your colleague asks you to explain the
practical applications of a bus structure in computer
systems. Could you also outline the various types of bus
structures and provide a visual representation of each
type using diagrams? (8)

ANS:

BUS STRUCTURE (2 marks)

A Bus is a collection of wires that connects several
devices. Buses are used to send control signals and data
between the processor and other components. This is to
achieve a reasonable speed of operation. In computer
system all the peripherals are connected to
microprocessor through Bus.

• 23 = 8 i.e. 3 address line is required to select 8 location

• In general 2x = n where x number of address lines (address
bit) and n is number of location
• Address bus : unidirectional : group of wires which carries
address information bits from processor to peripherals
(16,20,24 or more parallel signal lines)
• Data bus: bidirectional : group of wires which carries data
information bit form processor to peripherals and vice –
versa
• Control bus: bidirectional: group of wires which carries
control signals form processor to peripherals and vice –
versa

TYPES (6- each 2 marks with diagram)

Types of Bus structure:

Single bus
Two-bus
Multi-bus

ii) Write the boolean expression for the output

variable Q. (4)
 .
ANS: Q= A.B.C + A.(B’+C’)
[OR]

b) (i) Imagine you are a computer architecture instructor

and you're teaching a group of students about the
fundamental concept of the instruction fetch technique
in a processor. To help them grasp the process better,
you decide to provide a clear visual representation.
Could you illustrate the step-by-step process of the
instruction fetch technique using a well-labeled
diagram?
 (6)
(ii) Imagine you are a computer hardware instructor,
and you're leading a workshop on computer
architecture for a group of enthusiastic students. To
help them grasp the concept of how the processor
communicates with memory in a computer system, you
decide to provide a hands-on explanation. Could you
sketch a diagram that illustrates the connections
between the processor and memory components?
Additionally, explain how data and instructions flow
between these two vital components, highlighting the
significance of this interaction in the overall functioning
of a computer. (6)

 Two registers-MAR (Memory Address Register) and

MDR (Memory Data Register) : To handle the data
transfer between main memory and processor. MAR-
Holds addresses, MDR-Holds data
 Instruction register (IR) : Hold the Instructions that is
currently being executed
 Program counter (PC) : Points to the next instructions
that is to be fetched from memory
 General-purpose Registers: are used for holding data,
intermediate results of operations. They are also known
as scratch-pad registers.

Processor:
The processor consists of the Arithmetic Logic Unit
(ALU) and the Control Unit (CU). The ALU performs
arithmetic and logical operations, while the CU
manages the execution of instructions.

Memory:
Memory components include Random Access Memory
(RAM), Read-Only Memory (ROM), cache, and more.
RAM is used for temporary data storage, while ROM
holds permanent instructions. Cache is a faster, smaller
memory used to store frequently accessed data for
quicker retrieval.

Data Flow:

Instructions:
 The Control Unit fetches instructions from memory. It
sends a memory address to the memory module,
requesting the instruction located at that address.
The instruction is fetched from memory and loaded into
the Instruction Register (IR) within the CU.
The Control Unit decodes the instruction, determining
the operation to be performed.

Data:

To perform operations, the ALU requires data. Data

can be operands for arithmetic operations or values for
logical operations.
The Control Unit provides memory addresses to fetch
data from memory. Similar to fetching instructions, it
sends the memory address to memory and retrieves the
data.
Significance of Interaction:
The interaction between the processor and memory is
crucial to a computer's operation:

Execution of Programs:
Programs consist of a series of instructions stored in
memory. The processor fetches, decodes, and executes
these instructions sequentially. The memory holds the
program's instructions and data, allowing the processor
to work on them.

Data Manipulation:
The processor performs calculations and manipulates
data stored in memory. Data is fetched from memory,
processed in the ALU, and the results are often stored
back in memory.

Performance:
Efficient communication between the processor and
memory is essential for optimal performance. Caches
are used to store frequently accessed data, reducing the
time needed to fetch data from main memory.

*Performance Indicators are available separately for Computer Science and Engineering in AICTE
examination reforms policy.

Course Outcome (CO) and Bloom’s level (BL) Coverage in Questions

Approved by the Audit Professor/Course Coordinator