Synthesis with Design Compiler
Middle End VLSI Design
Table Content
1 Overview about Synthesis
2 Logic Synthesis Input Files
3 Synthesis Flow with Design Compiler
4 How to run Design Compiler Tool
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1. Overview about Synthesis
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1. Overview about Synthesis
⚫ Synthesis
◼ The process which converts an abstract form of desired circuit behavior into a design
implementation in terms of logic gates
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1. Overview about Synthesis
Design RTL description if button1_pressed
if (battery_charge > 10)
turn_on_light();
Technology Specific else
Circuit is obtained prompt_for_recharge();
from independent one Translation
by replacing all
components by real
blocks (standard Technology Independent
cells). This
Circuit
replacement process
is also called
mapping. Technology
Compilation
Independent Circuit is
4x and Optimization
logic circuit which fully
3x
implements function
2x 8x described but is built
Technology Specific from Generic Boolean
1x 2x Circuit Gates.
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2. Logic Synthesis Input Files
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2. Logic Synthesis Input Files
Design RTL
description
Specification Logic Synthesis Logic Circuit
Design
Constraints
Digital Standard
IP cell library
Cell Library
Building Blocks (Library)
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3. Synthesis Flow with Design Compiler
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3. Synthesis Flow with Design Compiler
Set up LIB and
Working Library
Analyze and
Elaborate
Read SDC
Compile
Check Design
Reports and
Outputs
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3. Synthesis Flow with Design Compiler
3.1 Set up LIB and Working Library
• search_path: Specifies where to look for technology and RTL files.
• link_library: Lists .db files describing standard cell libraries under different process corners (FF, SS,
TT).
• target_library: Sets the library DC uses for gate-level mapping.
• symbol_library is left empty since symbol graphics are not needed for synthesis.
Creates a working directory to store analyzed and elaborated design data.
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3. Synthesis Flow with Design Compiler
3.2 Analyze and Elaborate
• analyze: Read RTL and checks syntax and prepares design units.
• elaborate: Builds the complete hierarchical structure of the design.
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3. Synthesis Flow with Design Compiler
3.3 Read SDC
• read_sdc: Load Constraints
SDC (Synthesis Design Constraints) file contains:
• Clock definitions
• Input/output delays
• Timing exceptions (false paths, multicycle paths)
• Load and drive strength settings
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3. Synthesis Flow with Design Compiler
3.4 Compile
Uses compile_ultra for high-effort synthesis with advanced optimizations.
-retime: Allows flip-flop repositioning to improve timing performance.
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3. Synthesis Flow with Design Compiler
3.5 Check Design
Ensures the design is structurally correct (e.g., no unconnected ports, missing modules, etc.).
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3. Synthesis Flow with Design Compiler
3.6 Reports and Outputs
Produces synthesis reports:
•Area report: Cell area usage
•Timing report: Setup/hold slack, critical paths
•Power report: Estimated power consumption
•QoR report: Overall synthesis quality
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3. Synthesis Flow with Design Compiler
3.6 Reports and Outputs
• Verilog Netlist: Gate-level structural netlist.
• SDF (Standard Delay Format): Contains delay data for post-synthesis timing simulation.
• DDC: Binary design database for Formality
• SDC: Re-exported constraints
• Script: Environment setup for Formality
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4. How to run Design Compiler Tool
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4. How to run Design Compiler Tool
Step 1: csh
Step 2: source Documents/run_tools_dc_shell.csh
Step 3: cd Documents/me_labs/lab3
Step 4: dc_shell –f scripts/[Link]
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4. How to run Design Compiler Tool
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4. How to run Design Compiler Tool
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