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Hardware Modeling Using Verilog
Assignment- Week 3
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 12 Total mark: 12 X 1 = 12
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QUESTION 1:
Which of the following statements is/are true for the “assign” statement in Verilog?
a. It implements continuous assignment of the expression specified on the right -
hand side to a “net” type variable specified on the left-hand side.
b. It implements continuous assignment of the expression specified on the right -
hand side to a “reg” type variable specified on the left-hand side.
c. It can be used to assign values to a “reg” type variable in synchronism with a
clock.
d. None of these.
Correct Answer: a
Detailed Solution:
For the “assign” statement, the left-hand side can only be a “net” type variable, and cannot be a
“reg” type variable. It models a continuous assignment, where the right-hand side can be any
expression consisting of “net” and “reg” type variables. It cannot be used to assign values in
synchronism with a clock.
Thus, the correct answer is (a).
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QUESTION 2:
Which of the following are true for the following code segment?
input [3 :0] a;
input [3:0] b;
input sel;
output [3:0] f;
assign f = sel? a : b;
a. One 4-to-1 multiplexer will be generated.
b. Four 2-to-1 multiplexers will be generated.
c. One 4-to-1 and one 2-to-1 multiplexer will be generated.
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d. None of these.
Correct Answer: b
Detailed Solution:
The conditional statement “?” will generate a 2-to-1 multiplexer, with “sel” as the select
input. The variables “a”, “b”, and “f” are all 4-bit vectors; hence, four 2-to-1 multiplexers will be
generated.
The correct answer is (b).
QUESTION 3:
Which of the following constructs will be generating a demultiplexer, where “a,” “b,” and “c”
are variables?
a. assign a = b[c];
b. assign b[c] = a;
c. assign a = b[c] & ~b[~c];
d. assign a = b & ~c
Correct Answer: b
Detailed Solution:
A demultiplexer will be generated if the L HS of an assignment is an array reference with a
variable as index (as in option b).
The correct option is (b).
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QUESTION 4:
What does the following code segment implement?
q1 = ~ (q2 | y);
assign q2 = ~ (x | q1);
a. A 1-bit flip-flop with clocked input.
b. A 2-bit right-shift register.
c. Two NOR gates connected in cascade.
d. A 2-bit comparator.
e. None of these.
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Correct Answer: e
Detailed Solution:
The first NOR will have “y” and “q2” as inputs and give “q1” as output. The second NOR will
have “x” and “q1” as inputs and give “q2” as output. This corresponds to a pair of cross-coupled
NOR gates are used to build a one-bit latch.
The correct answer is (e).
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QUESTION 5:
Which of the following is/are true for the “initial” procedural block in Verilog test benches?
a. It specifies a procedural block that is executed repeatedly.
b. It specifies a procedural block that can be used for synthesis.
c. It specifies a procedural block that is executed only once.
d. None of these.
Correct Answer: c
Detailed Solution:
The “initial” block is used only in test benches, and cannot be used to write a module for
synthesis. It is executed only once during simulation, and is typically used to apply input
stimulus to the module under test.
The correct option is (c).
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QUESTION 6:
What will be the time period of the repetitive signal “stim” generated by the following code
segment?
initial stim = 1’b0;
always #7 stim = ~stim;
a. 0
b. 7
c. 14
d. None of these.
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Correct Answer: c
Detailed Solution:
The “initial” block initializes the “stim” signal to 0 at time 0. The “always” block toggles “stim”
with a delay of 7 time units. Clearly, the period of the clock is 2 x 7 = 14 time units.
Hence, the correct option is (c).
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QUESTION 7:
Which of the following event expressions can be used to specify a procedural block that will
execute whenever there is a change in the state of the signal “clk”?
a. always @(posedge clk)
b. always @(negedge clk)
c. always @(clk=0 or clk=1)
d. always @(clk)
e. None of these.
Correct Answer: d
Detailed Solution:
Options (a) and (b) specify edge-triggered execution with respect to the signal “clk”. Option (c)
is not valid. Option (d) specifies the event expression that is true whenever “clk” changes state.
Thus, option (d) is correct.
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QUESTION 8:
Which of the following is true for the following module?
module guess (a, b);
input [1:0] b;
output reg a;
always @(b)
begin
if (b == 2’b00) a = 1’b1;
else if (b == 2’b11) a = 1’b1;
else a = 1’b0;
end
endmodule
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a. A combinational circuit implementing an XOR function will be generated.
b. A combinational circuit implementing an AND function will be generated.
c. A latch will be generated for the output “a.”
d. None of these.
Correct Answer: a
Detailed Solution:
Assignment to variable “a” is specified for all values of the input “b,” and hence a combinational
circuit will be generated. “a” is assigned 0 if “b” is neither 00 nor 11. Hence, it implements the
XNOR function.
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QUESTION 9:
In which of the following case(s), the synthesis tool will infer a sequential circuit from the
description of an always block?
a. Every branch of a conditional statement defines all the outputs.
b. Every branch of a case statement defines all outputs.
c. Some branches of a case statement do not have defined outputs.
d. Some branches of conditional statements do not have defined outputs.
e. None of these.
Correct Answer: c, d
Detailed Solution:
The synthesis tool will generate a sequential circuit (latch or register) when the outputs are not
defined for every branch of a conditional or case statement.
The correct options are (c) and (d).
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QUESTION 10:
Consider the following code segment:
reg [0:7] a, b, c, d;
initial begin
#4 a = 10; b = 8; c = 2; d = 15;
#4 a = 4; b = a; c = b; d = c;
end
What will be the values of variables a, b, c, and d after a time interval of 10 units?
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a. a = 10, b = 8, c = 2 and d = 15.
b. a = 4, b = 8, c = 2 and d = 15.
c. a = 4, b = 4, c = 4 and d = 4.
d. None of these.
Correct Answer: c
Detailed Solution:
Since the initial block uses blocking assignments, the values of variables after a time interval of
4 units will be a = 10, b = 8, c = 2, and d = 15, and after a time interval of 8 units, all variables
will be updated to the value 4. The values will not change any further till time 10.
Thus, option (c) is correct.
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QUESTION 11:
Given the following Verilog code:
reg clk;
integer y;
initial clk = 1’b0;
always #5 clk = ~clk;
initial
begin
y = 2435;
while (y >= 45) #5 y = y >>1;
end
The while loop will be iterated _______________ number of time.
Correct Answer: 6
Detailed Solution:
The while loop executes as long as y >= 45. On each iteration, y is halved using right shift.
Starting from 2435, it takes 6 right shifts to drop below 45.
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QUESTION 12:
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Given the following Verilog code:
integer x, y;
reg clk;
always #5 clk = ~clk;
initial
begin
#5 clk = 1’b0; x = 0;
#3 y = 12;
end
initial
begin
#5 y =7;
Repeat (y)
#5 x = x + y;
end
The final value of x will be _______________.
Correct Answer: 49
Detailed Solution:
The variable y is updated to 7 before entering the repeat loop. The loop runs 7 times, adding 7 to
x each time. Therefore, x = 0 + 7×7 = 49.
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