VERIFICATION OF DDR5 MEMORY CONTROLLER

Cache memory

●​ Cache memory is a small amount of very fast memory that is built into the CPU.
●​ It acts like a buffer between the CPU and RAM.
●​ Data which is frequently required by the CPU is provided by cache.
●​ Access instructions and data from RAM one at a time, whole blocks of
instructions and data that are in use by the CPU are copied into the cache
memory, along with the associated memory addresses.
●​ If the CPU needs to access a memory address it first checks the cache memory
to see if there is a match. If there is then it access the contents of the cache
version rather than the version stored in RAM.
●​ Without cache memory the CPU would waste clock cycles waiting while data and
instructions were exchanged with the much slower RAM.
●​ There are different levels of cache.
●​ L1 cache is introduced inside the CPU itself. And they operate at the same speed
as that of the CPU.
●​ L1 size- 2-64 KB. - L1 is divided into instruction cache and data cache
●​ L2 cache is either placed inside or outside the CPU. If outside it is connected
using a very high speed bus to CPU.
●​ L2 size- 256-512 KB -L2 is slower than L1
●​ L3 placed outside CPU and size is 1-8MB
 ●​ When CPU needs some data, it will look into L1 then L2 and last L3.
●​ If the CPU finds the data in cache, it is called cache hit. If not found, called cache
miss.
●​ For a cache miss, the cache allocates a new entry and copies data from main
memory, then the request is fulfilled from the contents of the cache.
●​ The performance of cache memory is frequently measured in terms of a quantity
called Hit ratio.
●​ Hit ratio = hit / (hit + miss) = no. of hits/total accesses
●​ cache holds copies of recently accessed data such as a web page and pictures
on web pages.
●​ It keeps this data ready to "swap" onto your screen within fractions of a second.
●​ So, instead of requiring your computer to go to the original web page the cache
simply offers you the latest copy from your own hard drive.
●​ This caching-and-swapping speeds up page viewing because the next time you
request that page, it is accessed from the cache on the computer instead of from
the distant Web server.

DDR comes under which memory?

DDR comes under primary memory

●​ Holds only those data and instructions on which the computer is currently
working.
●​ It has a limited capacity and data is lost when power is switched off.
●​ The data and instruction required to be processed resides in the main memory.
●​ It is divided into two subcategories RAM and ROM.
●​ Faster than secondary memories.
●​ A computer cannot run without the primary memory.
Difference between SRAM and DRAM?

Criteria SRAM DRAM

Definition SRAM, or Static random-access DRAM, or Dynamic random-access

memory, is a specific type of memory, is a type of RAM that stores
semiconductor memory. It uses each bit of data within a separate
bistable latching circuitry to store capacitor in an integrated circuit (IC).
data. It is static, meaning it doesn't
need to be refreshed periodically to
function.

Typical Uses SRAM is generally used in the L3 and DRAM is used as the primary memory
L2 cache units in the CPU. in computers (for instance, DDR3).

Size The storage capacity of SRAM DRAM usually has a capacity of 1 GB

typically ranges from 1 MB to 16 MB. to 2 GB, commonly found in
smartphones and tablets. In most
laptops, it can store up to 4 GB to 16
GB.

Position in Device SRAM is located on the processor or DRAM is found on the device's
between the processor and the main motherboard.
memory of a device.

Storage Capacity SRAM generally has a smaller The storage capacity of DRAM is
storage size. relatively larger.

Speed SRAM, being an on-chip memory, has DRAM, being an off-chip memory, has
less access time than DRAM, making a longer access time than SRAM,
it faster. making it slower.

Cost SRAM is more expensive and less DRAM is relatively cheaper and more
 costlier than DRAM. cost-effective.

Density SRAM is less dense and less DRAM is denser compared to SRAM.
common.

Number of Transistors SRAM requires six transistors for a A single transistor can form a
single block of memory. memory block in DRAM.

Design and Build The construction and design of The design of DRAM is simpler,
SRAM are complex due to the use of making it easier to implement. The
multiple transistors. capacity of a DRAM module can be
six times more than an SRAM
module with the same number of
transistors.

Power Consumption SRAM operates on the principle of DRAM consumes more power
constant current change through compared to SRAM.
switches, with no charges like DRAM.

Charge Leakage SRAM does not experience any DRAM uses a capacitor that
charge leakage. generates a leakage current,
making it dynamic. Due to the
presence of a dielectric current in
the capacitor, DRAM requires a
power refresh circuitry.

Simplicity The modules of SRAM are simpler DRAMs are more complex
compared to those of DRAM, compared to SRAMs.
allowing for easy-to-build interfaces
for memory access.
Advantage SRAM consumes less power and DRAM has a low manufacturing
provides fast access speed. cost and greater memory capacity.

Disadvantage SRAM has less memory capacity DRAM consumes more power and
and a higher manufacturing cost. has a slower access speed.
Difference between sdram and ddr?

ZQ calibration?
ZQ Calibration is related to the data pins DQ. To understand what ZQ calibration does
and why it is required, we need to first look at the circuit behind each DQ pin.
Remember, the DQ pin is bidirectional. It is responsible for sending data back during
reads and receiving data during writes.

Now, if you look within a DRAM, the circuit behind every DQ pin is made up of a set of
parallel 240Ω resistor legs, as shown in Figure 4. Because of the nature of CMOS
devices, these resistors are never exactly 240Ω. The resistance is even affected due to
voltage and temperature changes. So, they are made tunable.

In order to tune these resistors to exactly 240Ω, each DRAM has

●​ a special block called DQ calibration control block and

●​ a ZQ pin to which an external precision (+/- 1%) 240Ω resistor is connected.

This external precision resistor is the "reference" and it remains at 240Ω at all
temperatures. When a ZQCL command is issued during initialization, this DQ calibration
control block gets enabled and it produces a tuning value. This value is then copied
over to each DQ's internal circuitry.

The 240Ω resistor leg within a DQ circuit is a type of resistor called "Poly Silicon
Resistor" and is, typically, slightly larger than 240Ω (Poly silicon resistor is a type of
resistor that is compatible with CMOS technology). There are number of p-channel
devices that are connected in parallel to this poly-resistor so that it can be tuned exactly
to 240Ω.

The figure below zooms into one 240Ω leg of the DQ circuit and shows 5 p-channel
devices connected to the poly-resistor. These little transistors are set based on input
VOH[0:4].

Now, the circuit connected to the DQ calibration control block is essentially a resistor
divider circuit with one of the resistors being the poly and the other is the precision
240Ω. When a ZQCL command is issued during initialization, this DQ calibration control
block is enabled and an internal comparator within the DQ calibration control block
tunes the p-channel devices using VOH[0:4] until the voltage is exactly VDDq/2 (A
classic resistor divider). At this point the calibration has been complete and the VOH
values are transferred all the DQ pins.

Having a bank of parallel 240Ω resistors allows you to tune the drive strength (for
READs) and termination resistance (for WRITEs). Every PCB layout is different so this
tuning capability is required to improve signal integrity, maximize the signal's eye-size
and allow the DRAM to operate at high-speeds.

The signal drive strength from the DRAM can be controlled by setting mode register
MR1[2:1]. The termination can be controlled using a combination of RTT_NOM,
RTT_WR & RTT_PARK in mode registers MR1, 2 & 5 respectively.
ODT?

On-die termination (ODT) is the technology where the termination resistor for
impedance matching in transmission lines is located inside a semiconductor chip
instead of on a printed circuit board (PCB).

Although the termination resistors on the motherboard reduce some reflections on the
signal lines, they are unable to prevent reflections resulting from the stub lines that
connect to the components on the module card (e.g. DRAM module). A signal
propagating from the controller to the components encounters an impedance
discontinuity at the stub leading to the components on the module. Th ected onto the
signal line, thereby introducing unwanted noise into the signal. In addition, on-die
termination can reduce the number of resistor elements and complex wiring on the
motherboard. Accordingly, the system design can be simpler and cost-effective.

●​ With DDR, excess signal noise was eliminated by resistors built into the
motherboard, but DDR2 has the terminating resistors built into each memory
chip.
●​ On-Die Termination for both memory and controller in DDR2 improve signaling
and reduces system cost.
●​ ODT is a new function that has been added to DDR2 SDRAM.
●​ It reduces signal reflection by including a termination resistance in the DRAM
Chip
●​ Signals propagating from the Memory controller to the DRAM Memory module
some reflections will cause because of impedance mismatch of transmission line
this makes distortion and data loss.
●​ By reducing signal reflection noise and for higher signal quality, faster data
transfers on-die termination is implemented
●​ Motherboard termination doesn’t reduce signal reflections, in the operating
frequency range
●​ Termination is located inside the chips that is why it called as On Die Termination
●​ DRAM controller can use ODT to set the termination resistance ON and OFF
simultaneously for each data I/O pin signal (DQ) as well as differential data
strobe signals (DQS, /DQS, RDQS and /RDQS) and write data mask signal
(DM).
 ●​ DRAM controller manages the on-die termination resistance through a
programmable configuration register or Extended Mode Register set(EMRS)
which resides in DRAM

When using ODT termination resistance for each DRAM chip can be switched ON/OFF

●​ when several DRAM chips exist on the same bus, signals transmitted to the
DRAM can be terminated.
●​ As a result, DRAM currently being accessed is less likely to be affected by
reflected signals from other DRAM.
●​ That’s we need ON/OFF feature in On die termination Setting of ODT Value (Rtt)
●​ DDR2 SDRAM can use the ODT control pin to set the termination resistance
simultaneously to each pin (DQ, DQS, /DQS, RDQS, and /RDQS) ON and OFF.
●​ ODT ON/OFF in power-down mode, active mode, standby mode
1.​ ODT (control pin input is at high level) : When ODT is set to ON during
power-down mode, then the internal termination resistor (Rtt) is set to ON.
2.​ ODT (control pin input is at low level): When ODT is set to OFF during
power-down mode, then the internal termination resistor (Rtt) is set to OFF.
●​ ODT is not supported during self-refresh mode.
Write and read in DDR4/5?

READ

●​ The first step is an ACT command. The value on the address bus at this time
indicates the row address.
●​ In the second step a RDA (Read with Auto-Precharge) is issued. The value on
the address bus during at this time is the column address.
●​ The RDA command tells the DRAM to automatically PRECHARGEs the bank
after the read is complete

WRITE

●​ The first step activates a row

●​ Then 2 WRITE commands are issued. The first one to address COL and second
one to COL+8.
●​ The second write operation does not need an ACT before it because the row we
intend to write to is already active in the Sense Amps
●​ Also note that the first command is a plain WR, so this leaves the row active. The
second command is a WRA which de-activates the row after the write completes.
Refresh mechanism?
Simplifying a little bit, think of DRAM as being a 2D array of memory cells1. Each cell in
the array is a minuscule capacitor.

Along one edge of that array, we have a set of sense amps. There's one sense amp for
each cell along that dimension. For either a refresh cycle or a normal read, we activate
an entire row (or column, if you prefer to look at it the other direction). When we do that,
we read the charge from that row (column) of capacitors into the sense amps. In doing
that, we've drained (at least most of) the charge out of the capacitors that make up the
memory cells themselves.

That will typically give somewhere in the range of a few hundred to a few thousand bits
of data that are sitting in the sense amps. We can then read some of that data out of the
sense amps to do to the outside world (if this was a read cycle) or we can just write it
back to the memory cells (if it was a write cycle). Or, in the case of a refresh cycle, we
read the data from the cells into the sense amps, then turn around and write it back out
from the sense amps to the cells.

●​ DRAM is a type of RAM that stores each bit of data in memory cell, consisting of
a tiny capacitor and transistor are paired to create a memory cell
●​ The capacitor can either be charged or discharged, these 2 states represents bit
0 and bit 1
●​ One of the problem in DRAM is, it is constructed with capacitors, they do not hold
their charge indefinitely, because of capacitor leakage property
●​ It would not be acceptable for the memory to lose its data
 ●​ To overcome this problem, it requires an external memory refresh ckt required i.e
periodically reading information from memory cell and immediately rewriting the
read information to the same area without modification of information
●​ Each bit of memory data is stored as presence or absence of an electric charge
on capacitor chip
●​ Cells are refreshed using the contents of sense amplifiers
●​ Refreshing is the responsibility of sense amplifiers

OCD?
DDR2 uses Off-Chip Driver calibration to improve the tracking accuracy between the
Data and the Data Strobes. The OCD calibration circuit is used to set the driver’s
impedance and voltage levels for DDR2 during the memory initialization process. It is
significant for the following reasons:
●​ OCD improves signal quality by minimising Data Strobe (DQS) to Data (DQ)
skews.
●​ It enhances signal quality by minimising Overshooting and Undershooting
problems.
●​ It absorbs process variations from each DRAM supplier by IO driver voltage
calibration.

Fly_by topology
 ●​ The advantage of fly-by- topology is that it supports higher frequency operation,
reduces the quantity and length of stubs and consequently improves signal
integrity and timing on heavily loaded signals.
●​ Topology improves signal quality, but generates a difference in flight time
between DQ signal and CMD/ADD/CLK signals.
●​ Therefore, the controller must adjust the output timing of each signal. To this end,
DDR3 is provided

DQ and DQS?
1.​ Data strobe is the clock signal for the data lines. Each data byte has their
own strobe
2.​ It is a bidirectional signal. It is transmitted by the same component as the
data signals. By the memory controller on write and the by the memory on
read commands.
3.​ Control and address signals are unidirectional and clocked by the CLK
signal. DQS runs the same speed as CLK but they are not synchronized.

Let's imagine time of flight for all signals is 1ns.

Situation with only one clk that is transmitted by the controller:

-During write there is no problem. Data signals can be clocked to the CLK signal and
everything is fine. If traces are length matched you can use timing tolerances tighter
than the time of flight.
-During read there is a problem. The controller must first transmit the clock to memory,
where it arrives 1 ns later. Then the memory sends data bits to the controller and this
takes another nanosecond. There is 2 ns skew, which limits how fast you can transmit.

When the same component that sends the data sends the clock, it is all synchronized.
Data can be transmitted even faster than what is the time of flight

Write and Read Levelling?

DDR3 follows fly-by topology. If a controller is connected to a number of DRAMs, clock
and control signals will be common to every DRAMs whereas data and data strobe
signals will be different for each of DRAMs according to their own specification.

So clock,command and address signals are routed to each DRAM through daisy chain
topology. These signals are first given to DDR1 and then to DDR2 and follows. These
signals are connected to DDRs using a small [Link] stub length should be as small
as possible. There will be a parallel termination resistor used at the last DDR. For
termination resistor we need a voltage which is half of ddr supply voltage. Ie, 1.5/2.

There will be a time difference between clock and data signals when it reaches ddr bcz
of the difference in the routing methods. Data and data strobe might reach earlier than
clock. Since DDR is a synchronous device this may lead to timing issues. Data and
strobe signals must be reached only after the rising/falling edge of clock.

Levelling is introduced to avoid this scenario. Write levelling is a process in which data
signal is delayed a little according to the clock so that the synchronization is maintained
between the clock and strobe signal. So a delay called DQS delay is introduced so that
the data strobe signal should arrive only after clock and hence the synchronization is
maintained properly.
Differential signaling?
When a signal is transmitted through a single wire, surrounding electrical interference
acts on it and can potentially modify the signal levels, causing the signal to be detected
incorrectly (a 1 getting detected as 0 and vice versa).

In differential signaling, each signal is transmitted using a differential pair—the signal

carried by one wire is the same level as the one carried by the other wire, but in opposite
polarity. The signal at the receiving end is interpreted as the difference between the two
lines that make up the differential pair.

If interference acts on the differential pair, it modifies both the lines similarly, but does
not affect the difference between the lines. This makes differential signaling immune to
electrical interference.

Differential clock in DDR

Differential clock is mainly used for reducing the Noise immunity. So in that sense we can
use the differential clock in the DDR side, because most of the time the DDR is working at
high frequency. Noises come into picture when we are working with high frequencies.

When we are using a differential clock there will be two io ports for the same signal (one
positive and one negative), one is the inversion of the other. so the when one is at level high
, then the other will be at level low, the data is sampled only when both the clock signals are
at exact opposite condition, which will reduce the immunity.

How to convert single clock to differential pair in DDR

Normally we will use a differential op amp to create a differential signal as shown below

In DDR, Both the CDC857 and the CDCV850 devices can be used to convert
single-ended clock signals into differential clock signals. Choice between these two
depends on the application.

The CDC857 and the CDCV850 devices are PLL-based differential clock drivers with a
maximum operational frequency of 167 MHz. These devices have been designed to
support a double-data-rate (DDR) specification and, therefore, they have higher
immunity against incoupling common mode noise. However, they require a differential
clock input signal.

Initialization process of DDR

Power-up and initialization is a fixed well-defined sequence of steps. Typically,

when the system is powered up and the controller in the ASIC/FPGA/Processor
is removed out of reset, it automatically performs the power-up and initialization
sequence. Here's a super-simplified version of what the controller does. For
exact details refer to section 3.3 in the JESD79-49A specification.

1.​ Apply power to the DRAM

2.​ De-assert RESET and activate ClockEnable CKE
3.​ Enable clocks CK_t/CK_c
4.​ Issue MRS commands and load the Mode Registers [The mode
registers are loaded in a specific sequence]
5.​ Perform ZQ Calibration [ZQCL]
6.​ Bring the DRAM into IDLE state

At this point the DRAMs on the DIMM module understand what frequency they
have to operate at, what the CAS Latency (CL), CAS Write Latency (CWL) and few
other timing parameters are.

here are 4 steps to be completed before the DRAM can be used

1.​ Power-up and initialization

2.​ ZQ Calibration
3.​ Vref DQ Calibration
4.​ Read/Write Training

Once this is done system is officially in IDLE and operational. You may need to
enable periodic calibration depending upon the conditions in which your device is
deployed.

(1) Apply power first to VDD, then to VDDQ.

(2) Keep the clock enable signal (CKE) low in order to guarantee that DQ and
DQS pins will be in the

high impedance state

(3) After all power supply and reference voltages are stable, and the clock is
stable, wait 200µs before

applying an executable command.

(4) Once the 200µs delay has been satisfied, a device deselect command
(DESL) or no operation

command (NOP) must be applied and CKE must be made high.

(5) Precharge all banks (the precharge all banks command (PALL) is
recommended).

(6) Enable DLL by the extended mode register set command (EMRS).

(7) Then reset DLL by the mode register set command (MRS) with A8 high.

(8) 200 cycles are required between DLL reset and any read command.

(9) After Precharging all the banks again, input two or more CBR (auto) refresh
commands (REF).

(10)Input the mode register set command (MRS) to program the operating
parameters

Difference b/w self and auto refresh?

Self refresh is a low power mode in which the DRAM maintains the refreshes internally
so that the MC, PHY, and memory interface can be idle.

Self Refresh:-​
The self-refresh operation deactivates the clock to reduce the power consumption of the
device, and it automatically executes a refresh operation by using the internal refresh
counter. The self-refresh mode is effective when not accessing the device for a long
time although the data must be held.

Auto Refresh:-​
Auto refresh is a command that refreshes DRAM. When the auto refresh command is
input, a row address is selected and refresh is executed. To hold the data, auto refresh
must be executed the number of times corresponding to the number of row addresses
within the stipulated time for the refresh cycle (tREF). (In the case of 8,192/64 ms, auto
refresh must be performed 8,192 times within 64 ms.)​
When auto refresh ends, the device automatically goes into the idle status.

self-refresh mode is nothing but just a standby mode, so that data is not lost when
external clock is not there.. it is purely to save power consumption..​
Auto-refresh mode auto refreshing of data happens every pre-defined time intervals..
usually a command is there to enter self refreshing mode.​
After the SELF REFRESH command is registered, all the inputs to the SDRAM become
“Don’t Care” with the exception of clock signal, which must remain LOW.

DLL

A Delay Locked Loop (DLL) is an electronic circuit that is used to align the phase of an
output signal with the phase of a reference signal by controlling the delay of the output
signal. Unlike a Phase Locked Loop (PLL), which operates by adjusting the frequency
and phase of the output signal, a DLL focuses on adjusting the delay of the signal to
achieve synchronization.

The main components of a DLL include a delay line, a phase detector, a loop filter, and
a voltage-controlled delay oscillator. The delay line consists of a series of delay
elements that introduce controllable delays to the signal passing through it. The phase
detector compares the phase difference between the reference signal and the delayed
output signal and generates an error signal based on the phase difference. The loop
filter processes the error signal to obtain a suitable control voltage. The
voltage-controlled delay element adjusts the delay of the output signal based on the
control voltage.

The operation of a DLL can be divided into several stages. Initially, the delay line
introduces a fixed delay to the output signal, creating a delayed version of the reference
signal. The phase detector then compares the phases of the reference signal and the
delayed output signal and produces an error signal proportional to the phase difference.
The error signal is filtered by the loop filter to obtain a smooth control voltage.
The control voltage is then fed into the voltage-controlled delay element, which adjusts
the delay of the output signal. By adjusting the delay, the output signal gradually aligns
its phase with the reference signal. The feedback loop continuously monitors the phase
difference and adjusts the delay until the output signal is locked in phase with the
reference signal.

DLLs are commonly used in applications where precise phase alignment is required,
such as in clock and data recovery circuits, high-speed data transmission systems, and
memory interfaces. They are particularly useful in scenarios where the reference signal
and the output signal may experience variations in phase due to noise, temperature
changes, or manufacturing process variations.

One advantage of DLLs is their ability to achieve fast phase alignment. Since DLLs
focus solely on adjusting the delay, they can quickly align the phase of the output signal
with the reference signal. This makes DLLs suitable for high-speed applications where
rapid synchronization is crucial.

In summary, a Delay Locked Loop is an electronic circuit that aligns the phase of an
output signal with the phase of a reference signal by controlling the delay of the output
signal. It consists of a delay line, a phase detector, a loop filter, and a voltage-controlled
delay element. By adjusting the delay, the DLL ensures that the output signal is
synchronized with the reference signal. DLLs are widely used in applications where
precise phase alignment is required, and they offer fast phase alignment capabilities,
making them suitable for high-speed systems.

A Delay Locked Loop (DLL) is a circuit that operates by adjusting the delay of an output
signal to achieve phase alignment with a reference signal. It consists of several key
components that work together to ensure synchronization.

The fundamental element of a DLL is the delay line, which is a chain of delay elements
that introduce controllable delays to the output signal. These delay elements can be
simple buffers or more complex circuits designed to provide precise and adjustable
delays. The delay line creates a series of delayed versions of the output signal, which
are then compared to the reference signal.
The phase detector is responsible for comparing the phase difference between the
reference signal and the delayed output signals. It generates an error signal that
represents the phase difference. The phase detector can take various forms, such as a
XOR gate, a phase frequency detector (PFD), or a analog-to-digital converter (ADC),
depending on the specific application requirements.

The error signal from the phase detector is then fed into a loop filter. The loop filter
processes and filters the error signal to obtain a control voltage that is suitable for
adjusting the delay of the output signal. The loop filter typically includes a low-pass filter
to remove high-frequency noise and fluctuations from the error signal, resulting in a
stable control voltage.

The control voltage is applied to a voltage-controlled delay element, which adjusts the
delay of the output signal based on the control voltage. The voltage-controlled delay
element can be implemented using various techniques, such as adjustable delay lines,
switched capacitor circuits, or digitally controlled delay elements. By varying the control
voltage, the delay of the output signal is adjusted to align its phase with the reference
signal.

The feedback loop continuously monitors the phase difference between the reference
and output signals. If there is a phase difference, the phase detector generates an error
signal, which is filtered and used to adjust the control voltage. The voltage-controlled
delay element then modifies the delay of the output signal accordingly. This iterative
process continues until the phase difference is minimized, and the output signal is
locked in phase with the reference signal.

DLLs offer several advantages in phase alignment applications. They are particularly
useful in scenarios where precise phase alignment is required, especially in high-speed
data transmission systems. DLLs have fast response times, allowing them to rapidly
achieve phase synchronization. They also provide robust performance, compensating
for variations in process, voltage, and temperature.

In summary, a Delay Locked Loop operates by adjusting the delay of an output signal to
achieve phase alignment with a reference signal. The delay line provides controllable
delays, and the phase detector compares the phases of the reference and delayed
output signals to generate an error signal. The loop filter processes the error signal to
obtain a control voltage, which is used by the voltage-controlled delay element to adjust
 the delay of the output signal. The feedback loop continuously monitors and adjusts the
delay until phase synchronization is achieved. DLLs are widely used in applications that
require precise phase alignment and offer fast response times and robust performance.

Parameter SDRAM DDR1 DDR2 DDR3 DDR4 DDR5

Clock rate (MHz) 1066 1600 3600

Voltage 3.3 2.6 1.8 1.5 1.2 1.1

Transfer rate(gb/s) 1.3 3.2 6.4 14.9 25.6 51.2

BW(mb/s) 17066 25600 57600

Data rate(MT/s) 166 400800 800 1600 5100 6400

Channels 1 1 2

Banks per group 8 4 4

Bank group 1 4(x4,x8) 8(x4,x8)

2(x16) 4(x16)

Burst length 8 8 16

pins 240 288 288

prefetch 1 2 4 8 8 16
VERIFICATION
Memory Controller

●​ Driver will act as memory controller

●​ Driver will take chip id, randomly generated user address and data from
sequencer
●​ Driver first start operating at POWER_ON state and will go to RESET state
●​ It will stay in RESET state for 20ns.
●​ At 20ns, Drive address 0F00 in [Link] for disabling reset and move to IDLE
●​ In IDLE state init task is called.
●​ From 20 to 70 ns no operation is performed.
●​ At 70005ps In init task, will set odt=1,cs_n=1,DM_n=0,ten=1,mir=0 and send
these values to interface and cai, lbdq, lbdqs, rfu, dnu, TDQS_t, TDQS_c,
DQS_t, QS_c, DQSL_c, DQSL_t, DQSU_t, DQSU_c will set to XX and send to
interface.
●​ At 70205ps ie, 20 clk cycles, init_to_activate task will be called.
●​ In init_to_activate task, odt=0,ten=x,mir=x
●​ Then we will convert the user address from packet to ba,bg,row and column
●​ row=user_address[16:0]
●​ column=user_addess[26:17];
●​ ba=user_address[28:27];
●​ bg=user_address[31:29]
●​ On the next clk, we will sent the activate command to address bus [Link].
●​ Set cs_n=0 and sent [Link]={chip_id,bg,ba,row[3:0],0,0}
●​ On the same clk, but at at next edge of clk(pos or neg), seet cs_n=1 and
[Link]={1,row[16:4]}
●​ After 6.5 clks, sent cs_n=0 and [Link]={chip_id,bg,ba,wr/rd}
●​ If wr → 6’b101001 and if rw → 6’b011101
●​ On the same clk cycle , but at next edge drive the column address to interface.
●​ If wr → [Link]={chip_id[2],0110,column[9:2],0,0}
●​ If rd → [Link]={chip_id[2],0010,column[9:2],0,0}
●​ After 9 clk cycles start DQS_c and DQS_t and on the next edge start driving data
to [Link].
●​ Generate DQS_t and DQS_c such that which are complementary to each other
and synchronized with ck_t and ck_c respectively.
●​ Data is randomly generated in a queue of size BL_MAX=16 bits
●​ In driver, data is pop_front () and sent to [Link]
●​ Pop_front is repeated BL_MAX/2=8 times, where each time two pop_front are
performed on posedges of both ck_t and ck_c.So in these 8 times, we will get
total 16 set of data.
●​ The same data queue from packet is used for the CRC generation also.
●​ Use 32*2 equation for CRC generation
●​ In order to create CRC bit, we need to store the entire queue contents to an
internal register and if we directly assign the queue data and shift it, we will get
our LSB as MSB.
●​ Ie, we are popping front and sending to [Link]. If we are directly shifting and
assigning the queue contents to a register means the
●​ Inorder to avoid this, first we will reverse the first entry in the queue(first
pop_front data) will come as MSB in internal reg data. To avoid this condition we
will reverse the queue first and then assign to internal reg.(we have to get the
first sent [Link] at LSB itself to get the correct CRC)
●​ Using this internal register, we will generate CRC 7 bit and sent it on the vif on
[Link] pin at 9th clock as last data.
●​ After sending CRC, on the next edge of clk(pos or neg) set DQS_t, DQS_c,
CS_n, DM_n,TQDS_t,TDQS_c, ca,odt,cai,dq to x.
Memory Model

●​ The memory is an associative array. Each entry in the array is [max burst
length*dq bits]=16*8=128 bits
●​ So 2^128 addresses are possible
●​ Total number of banks=bg*bank per bg=8*4=32
●​ So 2^128 address are divided among 32 banks.
●​ Each bank contains (2^128)/32=2^123 addresses.

Start operation when reset is disabled

●​ Decode row address

Use one flag and set that flag=1 on the first clk and flag=0 on the next clock.

Sent this flag as an argument in the decode address task. Other argument in the
decode task will be the [Link]

When flag=0
bg=[Link] [10:8]
ba=[Link] [7:6]
row[3:0]=[Link] [5:2]
When flag=1
​ row[16:4]=[Link][12:0]

1.​ Decode column address

—— Create a task in which one flag is added in argument
When flag=0
Chip id=[Link] [13:11]
bg=[Link] [10:8]
ba=[Link] [7:6]
read/write=[Link] [5:0]
101001→ write
011101→read
 When flag=1
Chip id=[13] vif
Column [9:3]=[Link] [8:3]

bg from both column and address is same

Final address={bg,ba,row,column}
Final address will sent to pkt.user_address

WRITE
●​ To get write data,
1.​ Take [Link] and sent to [Link]
2.​ Sent it to a 16 bit variable dq_in from [Link]
3.​ Set a counter dqs_cntr from 0 to 15 and each time dq_in to a register
dq_reg_in and then right shift it to 8 bits
4.​ Repeat this operation for 8 times and in each time twice(ck_t and ck_c)
5.​ So total 8*8*2=128 shifts we will get and on last repeat , when
dqs_cntr=15 (for the 8th time ), we will get all 16 set of data in dq_reg_in
6.​ Perform write operation in the memory declared in memory module ie,
mem[addr_final]=dq_reg_in
7.​ On the next cycle, take the last 7 bits from [Link] which is the CRC from
MC.
8.​ Calculate CRC locally in MM, using the dq_reg_in and compare it with
CRC received from MC
9.​ Save the dq_reg_in to a ref_data for comparison at scb.

READ
●​ To get read data
1.​ dq_reg_in=mem[addr_final]
2.​ Dq_reg_in now contains all 16 sets of data.
3.​ Save it to ref_data for comparison purpose
4.​ Perform >>8 operation and take out the data and put it in pkt. And sent to
mailbox to scb
5.​ Repeat this 8 times, and in each time twice(ck_t and ck_c).
6.​ Total we will get 16 set of data
MONITOR
●​ First check the [Link] to identify whether write operation or read operation.
●​ For this wait(cs_n==0) → wait(cs_n==1) → wait(cs_n==0)
●​ Because when first cs_n==0, we will get ba,bg,lower row address.
​ When cs==1, we will get higher row address
When second cs==0 we will get ba,bg,wr/rd
●​ Take the [Link] (write data for write operation, read data for read operation and
assign it to MSB of pkt.ref_data.
●​ Right Shift pkt.ref_data 8 times
●​ Repeat this step for 8 times, and two times in each repeat. So tatal 16 set of data
●​ Because of right shift 8 times in each repeat total 8*8*2 shifts i.e., 64 shifts and
we will get the first taken [Link] at the LSB.

SCOREBOARD
●​ Two mailboxes created one for mon to scb(pkt2) and other for mm to scb(pkt1).
●​ A temporary memory is used in scoreboard to store and retrieve the write data
from MM
●​ In MM, the write data is stored in a ref_data register.
●​ In SCB, we will take that ref_data, store it and retrieve it at address
pkt.user_addr based on the write and read command. This write/read command
is decoded at MM and sent to pkt at MM.
●​ A compare task is defined at base packet, which is called at SCB.
●​ This compare task will compare the ref_data from the monitor (read data out) and
data at the scb temp memory(write data at the MM).
●​ The SCB temp mem data is passed as an argument in the compare task .
●​ pkt2(mon to scb) will call that compare task

​
TESTCASES

1.​ Random
●​ data=random
●​ address=random
●​ Burst length=16
●​ Number of transactions=1
●​ Single write and single read.

2.​ Increment data – random address

○​ data=incrementing
○​ address=random
○​ Number of transactions=20
○​ Burst length=16
○​ First data is generated randomly and next 15 data are incremented from
the previous value

3.​ Decrement data – random address

○​ data=decrementing
○​ address=random
○​ Number of transactions=20
○​ Burst length=16
○​ First data is generated randomly and next 15 data are decremented from
the previous value

4.​ half data – random address

 ○​ data=An array of 16 values where 8 values are valid and rest are don't
cares
○​ address=random
○​ Number of transactions=20
○​ Burst length=16

5.​ Constant data – random address

○​ data=constant
○​ address=random
○​ Number of transactions=20
○​ Burst length=16
○​ Data held constant for all 16 bursts and 20 transactions

6.​ Increment address - increment data

○​ data=incrementing
○​ address=incrementing
○​ Number of transactions=20
○​ Burst length=16
○​ First address is generated randomly and next 15 address are incremented
from the previous value
7.​ Decrement address - random data
○​ data=random
○​ address=Decrementing
○​ Number of transactions=20
○​ Burst length=16
○​ First address is generated randomly and next 15 address generated by
decrementing from the previous value
8.​ constant address - random data
○​ data=constant
○​ address=incrementing
○​ Number of transactions=20
○​ Burst length=16
○​ Address is kept constant throughout the 20 transactions
 DDR5
DDR5 is a high-speed dynamic random-access memory. The 8Gb density is internally
configured as:

• x4/x8 devices: 16 banks (8 bank group with 2 banks for each bank group)

• x16 devices: 8 banks (4 bank group with 2 banks for each bank group)

Worked on x16 devices. Ie, 8 banks and 2 banks for each bank group.

A single READ or WRITE operation consists of a single 16n-bit wide, eight clock data
transfer at the internal core and 16 corresponding n-bit wide, one-half clock cycle data
transfers at the I/O pins.

READ and WRITE operations are burst-oriented, start at a selected location, and
continue for a burst length of 16 (BL16) or a chopped burst of eight (BC8) in a
programmed sequence.

4 modes: BC8 on-the-fly (OTF), fixed BL16, fixed BL32 (optional), or BL32 OTF
(optional) mode if enabled in the mode register.

Used 64 Gb addressing. Where

​ ​ Configuration : 8gbx8

​ ​ Bank groups: 8 – 3 bits: BG0-2

​ ​ Banks/BG : 4 – 2 bits : BA0-1

​ ​ Total banks : 32
​ ​ Row : R0-R17

​ ​ Column : C0-C9

​ ​ Chip id : CID0-CID2

​ ​ Page size :1KB( 2 power column bits)

C0 and C1 are controlled internally by the burst logic. As shown in the Command Truth
Table, C0 and C1 states are not selectable by any column access burst command such
that the burst would be reordered.

Default MR values:
●​ Burst length → MR0 → 00b → BL16
●​ Read Latency = CAS Latency → MR0 → 26 clk cycles

which is the number of clock cycles it takes for the DRAM to access
a specific set of data in a column. A lower CAS latency means that
the DRAM can access the data faster for the same frequency

●​ Write Latency = CAS Write Latency → Fixed based on CL

●​ Read to precharge delay → Rtp → 12 clk cycles

●​ INIT0 → Powerup to Reset → max=20ns

●​ INIT1 → Wait at reset → min=200us
●​ INIT2 → CS_n=0 at the last portion of Reset state. INIT2 is the point from which
CS_n=0 to Reset disable → 10ns
●​ INIT3 → wait at init state → 4ms
●​ INIT5 → After initialization state, NOP must be issued for min of INIT5 to
conclude the exit of initialization process → 3 clk cycles

Mode Registers:

●​ MRs are 256 byte wide

 ●​ MRs are selectable by 8 address bits as part of MRW and MRR access
commands

MR Read:

●​ Mode register address operands MA[7:0] enable selection of one of 256 mode
regs.
●​ CA[12:5]=MRA[7:0]
●​ MR contents are available on second 8 bits of burst and are repeated across all
DQs after CL following the MRR command
●​ Every odd DQ bits has its contents inverted.
●​ When CRC enabled, MRR o/p will come with BL18(BL16+2CRC). But host has
the option to consider 17th and 18th bit dontcares for MRR handling

MR Write

●​ Mode register address is contained in CA[12:5]=MRA[7:0] when CS_n=0

●​ MR contents is contained in CA[7:0]=OP[7:0] when CS_n=1

TIMING PARAMETERS
TRRDS -> Active bank A row to active bank B row command → 5 clk cycles

TRRDL → Active bank A row to active same bank row → 9 clk cycles

TFAW → After 4 repeated active commands, give delay → 14 clk cycles

TREFI → Average time between two refresh commands → 10 clk cycles

TRP → Precharge to refresh command → 5 clk cycles

TRFC → refresh to any valid command → 12 clk cycles

CL(CAS Latency) → Delay between the issue of internal READ command and the
availability of the first data byte on the DQ pin → 18 clk cycle

AL(Additive Latency) → Device allows a read command to be issued immediately after

the ACT command. The command is held for a period of AL before it is issued inside
the device. This increases speed and bandwidth → 12 clk cycle

RL=CL
TRC → active to active/auto refresh command time → 55000ps

TRCD → active to read/write command time → 15000ps

TWTR → write to read command time → 7500ps

TRPA → precharge all time period → 17500ps

CL_TIME → Minimum CAS Latency→ 15000ps

TCCDS → Bank access to different bank groups → 3 clk cyle

TCCDL → Bank access to same bank group →6 clk cycle

Two cycle commands

●​ ACT,WRP,WRPA,MRW,MRR,WR,WRA,RD,RDA are two cycle commands

●​ The device wont execute these two cycle commands if CS_n=0 on the second
clk cycle.
●​ ACT, WRP, WRPA and MRW are 2-cycle commands without associated ODT
control requirements. The device does not execute these 2-cycle commands if
CS_n is LOW on the second cycle (command cancel).
●​ Command cancel timing=8 clk → After CS_n=0, on the next clk cycle CS_n
should be high. If CS_n is not high, then that command is considered as
canceled and device will wait for 8 clk cycles to process the next valid command

PRECHARGE

●​ Precharge deactivates an open row in a particular bank or the open rows in all
banks
●​ Banks will be available for a subsequent row activation for TRP after precharge is
issued.
●​ After the bank has been precharged, it is in the idle state and must be activated
again prior to any read/write command
●​ Precharge period is determined by the last precharge command issued to that
bank
●​ A precharge command to a bank is allowed if there is no open row in that bank or
the previously opened row is already in the precharge process.
●​ If CA=0 for second half of the read/write command, auto precharge function
engages.
●​ If auto precharge is enabled, then during read cycle, precharge operation is
partially or completely hidden during burst. RAS lockout circuit internally delays
the precharge operation until array restoration operation completes.
●​ For write, the autoprecharge operation doesnt begin until the last data of burst
write properly stored in the mem array.

Three modes of precharge

●​ PRECHARGE (PREpb): applies precharge to a specific bank defined by

BA[1:0] (if applicable) in a specific bank group defined by BG[2:0].
●​ PRECHARGE ALL (PREab): applies precharge to all banks in all bank
groups.
●​ PRECHARGE SAME BANK (PREsb): applies precharge to a specific
bank defined by BA[1:0] in all bank groups.
●​ For precharge all, we will give the CID as input on CA
●​ For Precharge , we will give CID, BG and BA as input on CA
●​ For precharge same bank, we will give CID and BA as inputs on CA
​ ​

​ ​