USN 202EC003

Ph.D./M.S. (Engg.) by Research Degree Examination, Aug./Sep. 2023

Time: 3 hrs. Max. Marks: 100

Note: Answer any FIVE full questions, choosing ONE full question from each module.
2. Any revealing of identification, appeal to evaluator and /or equations written eg, 42+8 = 50, will be treated as malpractice.

Module-1
1 a. Explain the structure of n-type MOS device with substrate connection. (10 Marks)
b. Discuss the MOS trans conductance as a function of overdrive and drain current. (05 Marks)
c. For the arrangement shown in Fig.Q.1(c) plot the trans conductance as a function of VDS.
(05 Marks)
Important Note : 1. On completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.

Fig.Q.1(c)

OR
2 a. Explain the subthreshold conduction in MOSFET with voltage limitations. (10 Marks)
b. Explain the CS stage with source degeneration and its effect on drain current and trans
conductance. (10 Marks)

Module-2
3 a. Discuss the common-gate stage input-output characteristic curves. (10 Marks)
b. Explain the source follower with its input output characteristics. (05 Marks)
c. Explain how source follower is implemented using an NMOS transistor as current source.
(05 Marks)

OR
4 a. Discuss the common-mode input-output characteristics of a differential pair. (10 Marks)
b. Explain the effect of connecting MOS loads to a differential pair. (10 Marks)

Module-3
5 a. Sketch VX and VY as a function of IREf for the circuit shown in Fig.Q.5(a). Calculate the
value of IREf if it requires 0.5V to operate as current source. (10 Marks)

Fig.Q.5(a)
b. Explain the common-mode properties of differential pair with active current mirror.
(10 Marks)

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OR
6 a. Discuss the performance parameters of an OpAmp. (05 Marks)
b. The following circuit shown in Fig.Q.6(b) is designed for normal gain of 10. Determine
minimum value of A1 for the gain error of 1%. (05 Marks)

Fig.Q.6(b)
c. Explain the Gain Boosting in OpAmp. (10 Marks)

Module-4
7 a. Explain the conceptual topology for common-mode feedback. (05 Marks)
b. Explain common mode feed back using source followers. (05 Marks)
c. Calculate the low-frequency PSRR of the feed back circuit shown in Fig.Q.7(c). (10 Marks)

Fig.Q.7(c)

OR
8 a. Illustrate an implementation utilizing an XOR gate as the phase detector. (05 Marks)
b. A cellular telephone incorporates a 900-MHz PLL to generate the carrier frequencies. If
WLPF = 2 (20kHz) and the output frequency is to be changed from 901MHz to 9012MHz,
how long does the PLL output frequency take to settle within 100Hz of its final value?
(05 Marks)
c. Explain the skew reduction using PLL. (10 Marks)

Module-5
9 a. Explain current-steering DAC using binary weighted current sources. (08 Marks)
b. Show the value of output voltage at the end of each cycle for a 6-hot cyclic DAC with the
input value of D5D4D3D2D1D0 = 110101. Assume VREF = 5V. (07 Marks)
c. What is the largest value of output voltage from an 8 hit DAC that provides 1.0V for the
digital input value of 00110010? (05 Marks)

OR
10 a. Explain the operation of a Flash ADC. (10 Marks)
b. Discuss the operation of single slope ADC with timing diagrams. (10 Marks)

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