Verilog Traffic Light Controller Module

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Verilog Traffic Light Controller Module

Uploaded by

patilsharvari108

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Available Formats

Download as TXT, PDF, TXT or read online on Scribd

module traffic_light (

input clk,
input reset,
output reg red,
output reg yellow,
output reg green
);

// State encoding using parameters

parameter S_RED = 2'b00,
S_GREEN = 2'b01,
S_YELLOW = 2'b10;

reg [1:0] current_state, next_state;

reg [3:0] counter;

// State register
always @(posedge clk or posedge reset) begin
if (reset)
current_state <= S_RED;
else
current_state <= next_state;
end

// Counter for timing control

always @(posedge clk or posedge reset) begin
if (reset)
counter <= 0;
else if (counter == 4)
counter <= 0;
else
counter <= counter + 1;
end

// Next state logic

always @(*) begin
case (current_state)
S_RED:
next_state = (counter == 4) ? S_GREEN : S_RED;
S_GREEN:
next_state = (counter == 4) ? S_YELLOW : S_GREEN;
S_YELLOW:
next_state = (counter == 2) ? S_RED : S_YELLOW;
default:
next_state = S_RED;
endcase
end

// Output logic (Moore machine: depends only on state)

always @(*) begin
red = 0;
yellow = 0;
green = 0;

case (current_state)
S_RED: red = 1;
S_GREEN: green = 1;
S_YELLOW: yellow = 1;
endcase
end

endmodule

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Verilog Traffic Light Controller Module

Uploaded by

Verilog Traffic Light Controller Module

Uploaded by

module traffic_light (

// State encoding using parameters

reg [1:0] current_state, next_state;

// Counter for timing control

// Next state logic

// Output logic (Moore machine: depends only on state)

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