Department of Electrical
Engineering
National Institute of Technology,
Srinagar
Microprocessors
Credits: 4 Course code: EET-352
L:3 T:1 P:0
Course Evaluation Scheme
Mid-Semester Continuous End-Semester
(26 marks) Assessment (24 marks) (50 marks)
Tutorial/
assignments (8)
Quiz/Presentation (8)
Attendance/Class response
(8)
[Link] (6th Semester) Course Incharge: Dr. Zahid Afzal
Logical Group Instruction Set
• The instructions of this group perform AND, OR, EXOR operations, compare, rotate or take
complement of data in register or memory.
• The process of performing logic operations through the software instructions is slightly
different from the hardware logic.
• Logic operations are performed in relation to the contents of the accumulator.
• Logic operations simulate eight 2-input gates (or inverters).
• The Sign, Zero (and Parity) flags are modified to reflect the status of the operation. The carry
flag is reset. However, the NOT operation does not affect any flags.
• After a logic operation has been performed, the answer is placed in the accumulator replacing
the original contents of the accumulator.
• The logic operations cannot be performed directly with the contents of two registers.
• The individual bits in the accumulator can be set or reset using logic instructions.
1. ANA R: (AND register with accumulator)
Symbolic form: [A] [A] ^ [R] it means that content of register "R" is
ANDed with the content of accumulator and result is placed in the accumulator.
1-byte instruction
Register addressing mode
Machine cycle(1)-opcode fetch
MC = 1
4 T - states
All flags are affected and
AC = 1, CY = 0
2. ANA M: (AND memory with accumulator)
1-byte instruction
Indirect addressing mode
Machine cycle(2)-1 opcode fetch + 1 MEMR
4 T + 3 T = 7 T-states
All flags are affected and
AC = 1, CY = 0
3. ANI data: (AND immediate data with accumulator)
Symbolic form: [A] [A] ^ [data]
2-byte instruction
Immediate addressing mode
Machine cycle(2)-1 opcode fetch + 1 MEMR
4 T + 3 T = 7 T-states
All flags are affected and
AC = 1, CY = 0
Data Masking with logic AND
To mask the Least Significant Data (LSD) "ANI (FO) H" instruction is performed.
e.g. [A] [27H] and ANI (FO) H operation is performed then
[A] [20H], we can say LSD would be masked.
To mask the most significant data (MSD), ANI (OF) H instruction is performed.
e.g. [A] [27H] and if ANI (OF) H operation is performed then,
[A] [07H], we can say 'MSD' would be masked.
4. ORA R (OR register with accumulator)
Symbolic form: [A] [A] v [R]
1-byte instruction
Register addressing
Machine cycle(1)-opcode fetch
4-states
All flags are affected and
CY = 0, AC = 0
5. ORA M (OR memory with accumulator)
Symbolic form: [A] [A] v [M]
1-byte instruction
Indirect addressing mode
Machine cycle(2)-opcode fetch + 1 MEMR
7T-states = 4 T + 3 T
CY = 0, AC = 0
6. ORI Data (OR immediate data with accumulator)
Symbolic form: [A] [A] V [ data ]
2-byte instruction
Immediate addressing mode
Machine cycle(2)-opcode fetch + 1 MEMR
7 T-states = 4 T + 3 T
CY = 0, AC = 0
7. XRA R (EXOR register with accumulator)
Symbolic form: [A] [A] [R]
1-byte instruction
Register mode
Machine cycle(1)-opcode fetch
4T-states
All flags are affected
AC = 0, CY = 0
8. XRA M (EXOR memory with accumulator)
Symbolic form: [A] [A] [M]
1-byte instruction
Indirect addressing mode
Machine cycle(2)-opcode fetch + 1 MEMR
7 T -states = 4 T + 3 T
All flags are affected and
AC = 0, CY = 0
9. XRI Data (EXOR immediate data with accumulator)
Symbolic form: [A] [A] [data]
2-byte instruction
Immediate addressing mode
Machine cycle(2)-opcode fetch +1 MEMR
4T + 3T = 7T-states
All flags are affected and
AC = 0, CY = 0
10. CMA: (Complement the accumulator)
Symbolic form: [A] [A]
1-byte instruction
Implied/ Implicit addressing mode
1 opcode fetch
Machine cycle(1)-opcode fetch
4T-states
No flags are affected
To clear or reset the content of accumulator (A) with minimum no. of T-states, we use
either "XRA A" or "SUB A" instruction set.
e.g. Let [A] [F3H], and now XRA A operation is performed then,
11. CMP R: (Compare register with accumulator)
During this instruction, the content of register 'R' is subtracted from the content of
accumulator 'A' and all flags are set according to the result of SUB. But the result is
discarded and accumulator content remains unchanged.
CY Z Result
1-byte instruction
Register addressing mode
Machine cycle(1)-opcode fetch
4 T-states
All flags are affected
12. CMP M: (Compare memory with accumulator)
1-byte instruction
Indirect addressing mode
Machine cycle(1)-opcode fetch + 1 MEMR
4 T + 3 T = 7 T states
All flags are affected
CY Z Result
13. CPI Data: (Compare immediate Data with accumulator)
2-byte instruction
Immediate addressing mode
Machine cycle(1)-opcode fetch + 1 MEMR
4 T + 3 T = 7 T states
All flags are affected
14. CMC: (Compliment the carry status )
Symbolic form: [CS] [CS]
Machine cycle(1)-opcode fetch
4T-states
No flags are affected except carry flag.
15. STC: (Set carry status )
Symbolic form: [CS] 1
Machine cycle(1)-opcode fetch
4T-states
No flags are affected except carry flag.
16. RLC: (Rotate accumulator left)
Symbolic form: [An+1] [An]
[Ao] [A7]
[CS] [A7]
The content of the accumulator is rotated left by one bit. The seventh bit of
the accumulator is moved to carry bit as well as to the zero bit of the
accumulator.
17. RAL: (Rotate accumulator left through carry)
Symbolic form: [An+1] [An]
[CS] [A7]
[Ao] [CS]
The content of the accumulator is rotated left by one bit through carry. The
seventh bit of the accumulator is moved to carry and the carry bit is moved to
the zero bit of the accumulator.
18. RRC: (Rotate accumulator right )
Symbolic form: [An] [An+1]
[A7] [Ao]
[CS] [Ao]
The content of the accumulator is rotated right by one bit. The zero bit of the
accumulator is moved to the seventh bit as well as to carry bit.
19. RAR: (Rotate accumulator right through carry)
Symbolic form: [An] [An+1]
[CS] [Ao]
[A7] [CS]
The content of the accumulator is rotated right one bit through carry. The zero bit
of the accumulator is moved to carry, and the carry bit to the seventh bit of the
accumulator.
Following points are common for the instructions set RLC, RRC, RAL and RAR:
• 1-byte instructions
• Implied/ Implicit addressing mode
• Machine cycle(1)-opcode fetch
• 4 T-state’s
• Only carry flag (CY) is affected.