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Sequential Circuit Analysis and Timing

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3 views3 pages

Sequential Circuit Analysis and Timing

Uploaded by

luckymeenaa2431
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

EO 102

Tutorial-6
Q1. A sequential circuit using D flip-flop and logic gates is shown in the figure, where X
and Y are the inputs and Z is the output. The circuit is _______.

Q2. The following binary values were applied to the X and Y inputs of the NAND latch
shown in the figure in the sequence indicated below:
(a) X=0, Y=1;
(b) X=0, Y=0;
(c) X=1, Y=1.
The corresponding stable P, Q outputs will be ______.

Q3. Consider the given circuit

In this circuit, at what condition does the output toggle?

Q4. In the circuit shown, plot the timing diagram of the output for the given inputs.
Q5. Consider the D-latch shown in the figure, which is transparent when its clock input CK
is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50 %
duty cycle and CLK2 is a one-fifth period delayed version of CLK 1. The duty cycle at
the output of the latch is _____.

Q6. What is the maximum count value of the counter shown below:
Q7. Five JK flip-flops are cascaded to form the circuit shown in figure. Clock pulses at a
frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at
Q3 is _____.

Q8. What is the maximum count value of the counter shown below:

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