Harvard Architecture

 Separate Memory for Data and Instructions:

 Program Memory (Instruction Memory): Stores instructions that the CPU will
execute.
 Data Memory: Stores the data used by the program.

This means that both the CPU can fetch instructions and read/write data simultaneously,
improving performance.

 Separate Buses:

 Harvard architecture has separate buses for data and instructions. One bus handles the
transfer of instructions, and another handles data. This allows for parallelism, as the
CPU can fetch data and instructions at the same time.

 Speed and Efficiency:

 Because of the parallelism (instructions and data are accessed at the same time), it can
lead to faster execution, especially in high-speed processing tasks, like DSP (Digital
Signal Processing).

 Hardware Complexity:

 The design of Harvard architecture tends to be more complex because of the need for
separate storage and access mechanisms for both instructions and data.





In a normal computer that follows von Neumann architecture, instructions,

and data both are stored in the same memory. So same buses are used to
fetch instructions and data. This means the CPU cannot do both things
together (read the instruction and read/write data). So, to overcome this
problem, Harvard architecture was introduced.
 Structure of Harvard Architecture

Structure of Harvard Architecture

Buses
Buses are used as signal pathways. In Harvard architecture, there are
separate buses for both instruction and data. Types of Buses:
 Data Bus: It carries data among the main memory system, processor,
and I/O devices.
 Data Address Bus: It carries the address of data from the processor to
the main memory system.
 Instruction Bus: It carries instructions among the main memory system,
processor, and I/O devices.
 Instruction Address Bus: It carries the address of instructions from the
processor to the main memory system.
Von Neumann architecture
.

A von Neumann architecture

scheme
The von Neumann architecture—also known as the von Neumann
model or Princeton architecture—

 central arithmetic unit to perform arithmetic operations;

 a central control unit to sequence operations performed by the machine;
 memory that stores data and instructions;
 an "outside recording medium" to store input to and output from the machine;
 input and output mechanisms to transfer data between the memory and the
outside recording medium.

The Von Neumann Architecture is a computer architecture model that forms the basis for
most modern computers. It was proposed by the Hungarian-American mathematician and
computer scientist John von Neumann in the 1940s. The architecture is based on the concept
of storing both data and instructions in the same memory space. Here are the key components
and concepts:

1. Central Processing Unit (CPU):

 Arithmetic Logic Unit (ALU): Performs arithmetic operations (addition, subtraction,

etc.) and logical operations (comparisons, AND, OR, etc.).
 Control Unit (CU): Directs the operation of the processor. It fetches instructions
from memory, decodes them, and executes them.
 Registers: Small, fast storage locations within the CPU. Registers temporarily hold
data being processed by the ALU.

2. Memory:

 Primary Memory (RAM): Stores both the program (set of instructions) and data.
This is a shared space, meaning instructions and data are stored in the same memory.
 Secondary Storage (e.g., Hard Drives, SSDs): For long-term storage, though not
part of the Von Neumann architecture directly, it plays an important role in modern
systems.
 3. Input/Output (I/O):

 This is the mechanism through which data enters (input) and leaves (output) the
system. Devices like keyboards, mice, displays, and printers interact through I/O
channels.

4. Bus:

 Data Bus: Carries data between the components (CPU, memory, etc.).
 Address Bus: Carries the address location of where the data should be stored or
fetched from memory.
 Control Bus: Carries control signals that coordinate operations across the system.

Key Concepts of Von Neumann Architecture:

 Stored-Program Concept: Programs (instructions) and data are both stored in the
same memory space, making the system flexible and programmable.
 Sequential Execution: Instructions are fetched, decoded, and executed in a sequential
manner unless explicitly altered by control flow instructions (like jumps or loops).
 Fetch-Decode-Execute Cycle: This cycle is the heart of any Von Neumann system.
The control unit fetches an instruction from memory, decodes it, and then executes it.

 RISC VS CISC
Feature RISC CISC
Instruction Set Simple, few instructions Complex, many instructions
Instruction
Fixed length Variable length
Length
Can be multiple cycles per
Cycle Time Typically 1 cycle per instruction
instruction
Pipelining Easier to implement More difficult due to complexity
More compact code (due to
Memory Usage Can be larger due to more instructions
complex instructions)
Registers More registers Fewer registers
Better for certain applications, Better for certain tasks due to
Performance
especially when pipelining complex instructions
Examples ARM, MIPS, RISC-V Intel x86, AMD64


RISC CISC

1. RISC is a reduced instruction set. CISC is a complex instruction set.

2. The number of instructions is less as compared to The number of instructions is more as compared to
CISC. RISC.

3. The addressing modes are less. The addressing modes are more.
4. It works in a fixed instruction format. It works in a variable instruction format.

5. The RISC consumes low power. The CISC consumes high power.

6. The RISC processors are highly pipelined. The CISC processors are less pipelined.

7. It optimizes the performance by focusing on It optimizes the performance by focusing on

software. hardware.

8. Requires more RAM. Requires less RAM.

ChatGPT said:
Concept of Pipelining (in Computer Architecture)

Pipelining is a technique used in the design of modern processors and digital systems to
improve the throughput (i.e., the number of instructions processed per unit time) of the
system.

🧠 Definition:

Pipelining is a method where multiple instruction steps are overlapped in execution. It's
similar to an assembly line in a factory, where different stages of production are handled
simultaneously.

🔧 How It Works:

An instruction in a CPU typically goes through these stages:

1. Fetch – Get the instruction from memory

2. Decode – Interpret the instruction
3. Execute – Perform the operation
4. Memory Access – Read/write data from/to memory
5. Write Back – Write the result back to the register

In a non-pipelined CPU, each instruction goes through all stages before the next one starts.

In a pipelined CPU:

 While instruction 1 is in the Decode stage,

 Instruction 2 is in the Fetch stage, and
  Instruction 0 is in the Execute stage, etc.

So multiple instructions are in different stages at the same time.

📈 Benefits:

 Increases CPU throughput

 Makes more efficient use of CPU resources
 Improves performance without increasing clock speed

📉 Drawbacks / Challenges:

 Hazards (problems that can arise in pipelines):

o Data Hazards – Instructions depend on each other’s results
o Control Hazards – Caused by branching (e.g., if-else)
o Structural Hazards – Hardware resources are insufficient
 Requires more complex control logic

🧪 Real-world Analogy:

Think of a car wash with 5 stages: Soaping, Scrubbing, Rinsing, Drying, and Polishing.
Instead of waiting for one car to complete all 5 stages, you start washing the next car as soon
as the first car moves to stage 2.

📌 Summary Table:
Feature Non-Pipelined Pipelined

Instruction Flow One at a time Overlapped, multiple at once

Speed Slower Faster

Efficiency Lower Higher

Complexity Simpler More complex