Assignment
Fundamentals of Electronics (ECE_1072)
Note : Answer all questions
Submission deadline : 17th April, 2025
Q No Questions COs BL
1 A Si diode carries a current of 25mA when it is forward biased with 1 3
0.4V at 27oC. If the temperature is increased by 5 oC, Determine the
dynamic resistance with a ∆VD=0.01V.
2 A transformer supplies a full wave centre tapped rectifier employing 2 4
diodes with forward voltage drop of 0.4V and forward resistance of
9Ω. The Primary voltage of the transformer is 120V, 50Hz and the
turns ratio is 5:2. The load resistance is 450Ω.
i. Determine the value of the dc output voltage if there are no
filters used.
ii. Design a capacitor filter, If full wave bridge rectifier is used
to maintain 15% more average output voltage obtained
using centre tapped rectifier in part a.
iii. Compute ripple factor with the designed capacitor filter
3 For a Zener voltage regulator, RS = 500Ω and Vi = 30V. Determine 2 3
the minimum and maximum values of RL so that zener diode
remains in ON state, given that IZK = 2mA, PZK=20mW and PZM =
0.1W.
4 With a circuit diagram, explain MOSFET amplifier and provide the 2 3
expressions for the voltage gain. Also, for the circuit shown below,
calculate the voltage gain if ID = 2 mA, µnCox = 100 µA/V2
5 Draw the circuit diagrams of integrator and differentiator using Op- 3 3
amp and derive the expressions for the output voltage of these
circuits.
6 For the non-inverting Op-amp comparator, VINV = 2 V, VNON-INV 3 3
= 5sin314t V and ±VSAT = ±10 V. Draw the circuit and sketch the
output waveform with all the labels with respect to input
7 There are three voltage sources V1, V2, V3. It is required to obtain 3 4
the sum of these signals without the change in magnitude and sign.
Design a suitable op-amp circuit and explain its operation.
8 Use the concept of common mode signals and explain how noise 3 4
can be eliminated at the output of an op amp.
9 In a certain application, four inputs A, B, C, D are fed to a logic 4 3
circuit, producing an output Z which controls a relay. Z = 1 for the
input states (ABCD): 0000, 0011, 0101, 0110, 1011 and 1110. The
states 1000 and 1001 do not occur and Z = 0 for the remaining input
states.
i. Obtain truth table for Z.
ii. Use Karnaugh map to find a minimal SOP and implement
the same using NAND gates only.
10 Design a 16:1 multiplexer using a 2:1 multiplexers. 4 3
11 Sketch the logic circuit of 3 bit up counter using negative edge 5 3
triggered JK flip-flops with timing diagram.
12 Differentiate between sequential & combinational circuits. 5 3
Consider a serial input data 11100101 fed to a 4-bit shift register
circuit from LSB. What will be the output for SISO operation after
6th clock pulse? How many clock pulses are required to shift MSB
bit to the output? Also, draw the circuit diagram.
13 In this alarm system, the alarm bell will sound only while the door 5 4
is open, or a weight is placed on the pressure mat. If someone who
has stepped onto the mat moves off it, or an open door is closed, the
alarm bell will stop ringing. A D-type flip-flop could be
incorporated into the logic circuit so that the alarm bell would
continue to sound after a person closed the door or moved off the
pressure mat. Explain how this could be achieved. Answer the
following:
a) why a D-type flip-flop would be suitable for this task
b) where the D-type flip-flop would need to be inserted into the
circuit
c) what additional input the D-type flip-flop would need.