Chapter 5.

Program Control Instructions

In this chapter, we will discuss the program
control instructions.
They include: JMP and subroutines.

5.1. Flag Control Instructions

These instructions affect the state of the flags.
The following table shows these instructions.
Mnemonic Meaning Format Operation Flags
affected
CLC Clear CF CLC (CF) ← 0 CF
STC Set CF STC (CF) ← 1 CF
CMC Complement CF CMC (CF) ← (CF) CF
CLI Clear IF CLI (IF) ← 0 IF
STI Set IF STI (IF) ← 1 IF
CLD Clear DF CLD (DF) ← 0 DF
STD Set DF STD (DF) ← 1 DF

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 5.2. Jump Instructions
It is used to skip over sections of
a program to any part of the
program.
The jump alters the execution
path of instructions in the
program.
Program execution is not
intended to return to the next
sequential instruction after the
jump instruction.
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5.2. Jump Instructions

CS and IP keep track of the next instruction to be
executed.
The jump instruction involves altering the contents
of these registers (CS and IP).
Thus, execution continues at an address other than
that of the next sequential instruction.
There are two different types of jump instructions:
Unconditional
Conditional

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 5.2. Jump Instructions
In an unconditional jump,
No status requirements or conditions are imposed for
the jump to occur.
As the instruction is executed, the jump takes place to
change the execution sequence.
In a conditional jump,
If the status conditions exist, the jump instruction is
executed.
Otherwise, execution continues with the next sequential
instruction of the program.
The conditions depends on the status flags such as CF,
PF, OF, SF, ZF.
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5.2.1. Unconditional Jump

The unconditional jump instruction is given as:
M n em o n ic M ean in g F orm at O p eratio n F lags
affected
JM P U n con d itio n al JM P O p eran d Ju m p is initiated to th e N on e
ju m p ad d ress sp ecified b y th e
op era n d

The allowed operands are:

Operands
Short-Label
Near-Label
Far-Label
Memory Pointer 16
Register Pointer 16
Memory Pointer 32

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 5.2.1. Unconditional Jump
There are two basic kinds of
unconditional jumps:

Intrasegment (Short and Near jump)

Intersegment (Far jump)

5.2.1. Unconditional Jump

Intrasegment jump is limited to addresses within
the current code segment.
It is achieved by modifying the value of IP only.
It is divided into short and near.

Intersegment jump is used to addresses outside

the current code segment.
This type is achieved by modifying the value in
CS and IP registers.

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 5.2.1. Unconditional Jump
Short jump allows jumps or branches to memory
locations within +127 and –128 bytes from
memory location following the jump.
Near jump allows jumps or branches to memory
locations within +32K and –32K bytes from
memory location following the jump.

5.2.1. Unconditional Jump

Example: What is the content of the IP register after the
JMP instruction?
a) JMP $04
Before Execution: CS = 1000H, IP = 0002H
After the execution of JMP:
New IP = IP + 04H = 0006H

b) JMP 200DH
Before Execution: CS = 1000H, IP = 200BH
After the execution of JMP: New IP = 200DH

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 5.2.1. Unconditional Jump
Example: What is the content of the IP register after the
JMP instruction?
c) JMP A300:0127
Before Execution: CS = 1000H, IP = 0002H
After the execution of JMP:
New CS = A300H, New IP = 0127H

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5.2.1. Unconditional Jump

Example: What is the content of the IP register after the
JMP instruction?
d) JMP [BX]
CS = 0CDEH, BX = 1000H, DS = 1000H
IP = 0102H
Address Contents
11002 F2
11001 02
11000 00

After the execution of JMP:

New IP = 0200H
PA = CS×10+IP=0CDE0+0200=0CFE0H
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 5.2.1. Unconditional Jump
Example: What is the content of the IP register after the
JMP instruction?
d) JMP DWORD PTR[BX]
CS = 0CDEH, BX = 1000H, DS = 1000H
IP = 0102H
Address Contents
11000 00
11001 02
11002 10
11003 0A

After the execution of JMP:

New IP = 0200H, New CS = 0A10H

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5.2.1. Program Memory

Addressing Modes
These modes are used with the JMP and CALL
instructions.
They can be divided into:
Direct JMP 0200H; JMP A000H:0100H
Relative JMP $4
Indirect JMP BX; JMP WORD PTR [BX];
JMP DWORD PTR [BX]

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 5.2.2. Conditional Jump
The conditional jump instruction is given as:
Mnemonic Meaning Format Operation Flags
affected
Jcc conditional Jcc Operand If the specified condition cc is None
jump true the jump to the address
specified by the operand is
initiated; Otherwise the next
instruction is executed.

Conditional jumps are all short jumps.

The range of the jump is always within +127 to –
128 bytes from the address of the next instruction.

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5.2.2. Conditional Jump

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 5.2.2. Conditional Jump
A list of conditional jump is given as:
Opcode Condition Tested Function
JA/JNBE CF = 0 and ZF = 0 Jumps above/jumps not below or equal to
JAE/JNB CF = 0 Jumps above or equal to/jumps not below
JB/JNAE CF = 1 Jumps below/jumps not above or equal to
JBE/JNA CF = 1 or ZF = 1 Jumps below or equal to/jumps not above
JC CF = 1 Jumps carry set
JE/JZ ZF = 1 Jumps equal/ jumps 0
JG/JNLE OF = ZF and SF Jumps greater/jumps not less than or equal to
JGE/JNL SF = OF Jumps greater than or equal to/jumps not less than
JL/JNGE SF = OF Jumps less than/jumps not greater than or equal to
JLE/JNG Z = 1 or S = 0 Jumps less than or equal to/jumps not greater than
JNC CF = 0 Jumps no carry
JNE/JNZ ZF = 0 Jumps not equal to/jumps not 0
JNO OF = 0 Jumps no overflow
JNP/JPO SF = 0 Jumps no parity/jumps parity odd
JNS PF = 0 Jumps no sign (positive)
JO OF = 1 Jumps on overflow
JP/JPE PF = 1 Jump parity/jumps parity even
JS SF = 1 Jumps sign (negative)
JCXZ CX = 0 Jumps if CX = 0
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5.2.2. Conditional Jump

Example 1: Trace the following program
CMP AX,BX ;The result of AX-BX affects the flags
JB DIFF2 ;Jump if Below (CF = 1)
DIFF1 MOV DX,AX ;DX = AX
SUB DX,BX ;DX = DX-BX affects the CF
JMP DONE
DIFF2 MOV DX,BX ;DX = BX
SUB DX,AX ;DX = DX – AX affects the CF.
DONE NOP
This program tests whether AX < BX or not.
If AX > BX, DX = AX – BX
If AX < BX, DX = BX – AX
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 5.2.2. Conditional Jump
Example 1: Trace the following program
SCAN MOV DI,OFFSET TABLE ;Load DI by the address
MOV CX,100 ;Load counter CX = 100
MOV AL, 0AH ;Load AL by 0AH
CLD ;Select auto increment.
REPNE SCASB ;Search for the byte 0
JCXZ NOT_FOUND

This program scans a table of 100 bytes for a 0AH.

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5.3. Loop Instructions

There are two different types of loop instructions:
Unconditional
Conditional loop.

The unconditional loop (LOOP) instruction is a

combination of the conditional jump and the
decrement of CX instructions.
It will decrement the contents of register CX.
If CX is not 0, jump to the label associated with loop.
If CX becomes a 0, the next sequential instruction in
the program is executed.

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 5.3. Loop Instructions
The conditional loop instructions include
LOOPE/LOOPZ, LOOPNE/LOOPNZ.

They work as LOOP instruction except that they

check for two conditions: the contents of both CX
and ZF flag.
If CX is not 0 and the ZF condition is satisfied, jump to
the label associated with loop.
If CX becomes 0 or the ZF condition is not satisfied,
the next sequential instruction in the program is
executed.

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5.3. Loop Instructions

The following table shows the loop instructions
Mnemonic Meaning Format Operation Flags
affected
LOOP Loop LOOP Short-label (CX) ← (CX) – 1 None
Jump is initiated to location
defined by short label if (CX) ≠ 0;
Otherwise, execute next sequential
instruction
LOOPE/ Loop while LOOPE/LOOPZ Short-label (CX) ← (CX) – 1 None
LOOPZ equal/Loop Jump to location defined by short
while zero label if (CX)≠≠0 and (ZF) = 1;
Otherwise, execute next sequential
instruction
LOOPNE/ Loop while LOOPNE/LOOPNZ Short- (CX) ← (CX) – 1 None
LOOPNZ not equal/ label Jump to location defined by short
Loop while label if (CX) ≠ 0 and (ZF) = 0;
not zero Otherwise, execute next sequential
instruction

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 5.3. Loop Instructions
Example 1: Trace the following program:
MOV CX, 05 ;Load the counter CX = 5
MOV DX, 00 ;Load DX by zero
AGAIN NOP ;No operation (Just Waiting)
INC DX ;Increment DX by 1
LOOP AGAIN ;Go to AGAIN until CX = 0.

This program increment the value of DX five time

DX = 5 and CX = 0.

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5.3. Loop Instructions

Example 2: Trace the following program:
MOV DL,05 ;Load DL by 05H
MOV AX,0A00H ;Load AX by 0A00H
MOV DS,AX ;Initialize the DS =AX
MOV SI,01FFH ;Initialize SI by 01FFH
MOV CX, 0FH ;Load CX = 15
AGAIN INC SI ;Increment SI by 1
CMP [SI],DL ;[SI]-DL affect the ZF
LOOPNE AGAIN ;Repeat this comparison
loop until CX=0 or ZF=1.

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 5.3. Loop Instructions
It compares a block of data pointed by SI to DL.
The data stored at the memory location starting at address
DS:0200 are: 4, 6, 3, 9, 5, 6, D, F, 9, BA, AB, 32, E9, 4C,
F7, 80,..
The length of the blocks is 15 numbers.
1st loop: compare 4 and 5, ZF = 0, SI = 0200, CX = 0E
2nd loop: compare 6 and 5, ZF = 0, SI = 0201, CX = 0D
3rd loop: compare 3 and 5, ZF = 0, SI = 0202, CX = 0C
4th loop: compare 9 and 5, ZF = 0, SI = 0203, CX = 0B
5th loop: compare 5 and 5, ZF = 1, SI = 0204, CX = 0A
The loop is terminated.

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5.4. Subroutines
The subroutine is a very important part of any
computer’s software architecture.
It is a group of instructions that performs a given task.
It is used many times by the program but need to be
stored once in the memory.
This saves memory space and makes the task of
programming much simpler because it takes less time
to code a program.
The disadvantage of a subroutine is that the computer
takes a small additional time to link to the subroutine
(CALL) and return from it (RET).

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 5.4. Subroutines
The stack is used to store the return address so that
the subroutine may return to the program at the
point after the CALL instruction in the program.
The subroutine is called a procedure as it would be
in a higher-level language.
There are two basic instructions: CALL and RET.

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5.4. Subroutines
These instructions are as shown:
Mnemonic Meaning Format Operation Flags
affected
CALL Call CALL Execution continues from the address of None
subroutine Operand the subroutine specified by the operand.
Information required to return back to
the main program such as IP and CS is
saved on the stack.
RET Return RET or Return to the main program by restoring None
RET IP (and CS for far-procedure). If
operand operand is present, it is added to the
content of SP.

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 5.4. Subroutines
The operands of the CALL are as shown:
Operands
Near-procedure
Far-procedure
Memory pointer (16 bits)
Register pointer (16 bits)
Memory pointer (32 bits)

The operands of the RET are as shown:

Operands
None
Displacement (16 bits)

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5.4. Subroutines
CALL instruction transfers the flow of a program
to a procedure.
CALLs differ from JUMPs because they save the
contents of IP on the stack if the CALL is near or
IP and CS on the stack if it is far.
They are divided into:
Near CALL
Far CALL

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 5.4. Subroutines
The operand of the near CALL instruction is 2
bytes presenting the offset location of the near
procedure.
It causes the jump to the subroutine.
It also pushes the IP register onto the stack.
Because the IP register contains the address of the
next instruction to be executed.

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5.4. Subroutines
The operand of the far CALL instruction is 4 bytes.
2 bytes present the IP of the subroutine and 2 bytes
presents the new code segment (CS) value for the
subroutine.
It causes the jump to the subroutine.
It also pushes both the IP and the CS registers onto
the stack.
Because the IP and CS registers contain the address
of the next instruction to be executed, the return
address is pushed onto the stack.
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 5.4. Subroutines
RET instruction removes either a 16-bit number (near
return) from the stack and places it in the IP or a 32-
bit number (far return) and places it in IP and CS.
When IP or IP and CS are changed, the location is
changed to the address of the instruction that
immediately follows the most recent CALL to a
procedure.
There is another form of the RET instruction. This
form allows a number added to the contents of the
stack pointer (SP) after the return address is removed
from the stack.
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5.4. Subroutines
PROC is used to indicate the start of a procedure
(subroutine), the name of the procedure and the type
of CALL and RET instructions used by the assembler.
The name of the subroutine can be any valid assembly
language name.
The type can be near (intrasegment) or far
(intersegment) depending on whether the procedure is
located within the code segment or some distance
from it.
ENDP is used to indicate the end of the procedure and
the name of that procedure.

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 5.4. Subroutines
Example 1: What is the result of executing:
CALL 1002H
Before execution:
CS = 1000H, IP = 0003H,
SS = A000H, SP = 0000H

After the execution:

CS = 1000H, IP = 1002H,
SS = A000H, SP = FFFEH

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5.4. Subroutines
What is the result of executing the following
a) RET
Before execution:
CS=1000H, IP = 1006H, SS = A000H, SP = FFFEH
After the execution:
CS=1000H, IP = 0003H, SS = A000H, SP = 0000H

b) RET 4
It adds a 4 to the SP after removing IP from the
stack.

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 5.4. Subroutines
Example 3: Trace the following program:
MOV SI, OFFSET COMPUTE ;Load SI by the compute
CALL [SI] ;Call procedure addressed by SI
…
Compute PROC NEAR ;Procedure is of type near call
PUSH DX ;Push DX to the stack
MOV DX,AX ;Move AX to DX
IN AX, DATA ;Load AX by the input port DATA
OUT PORT,AX ;Output [AX] to the output port PORT
MOV AX, DX ;Restore the content of [AX]
POP DX ;Pop [DX] from the stack
RET ;Return to the next instruction
COMPUTE ENDP ;End the procedure

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5.5. Interrupts
An interrupt can be:
Hardware-generated subroutine call(externally derived)
Software-generated subroutine call (internally derived).
It interrupts the program currently executing by
calling the interrupt service subroutine.
Software interrupt are special types of call
instructions in the 8086/8088 microprocessor.

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 5.5 Interrupts
Some address locations have dedicated functions
or reserved.
FFFFFH
FFFFCH Reserved For future use
Dedicated For functions such
FFFF0H as storage of the
hardware reset jump
Open for instructions.
general Use

0007FH
Reserved For Interrupt
00014H
Dedicated
00000H
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5.5.1. Interrupt Vectors

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 5.5.1. Interrupt Vectors
An interrupt vector is a 4-byte number stored in the first
1024 bytes of the memory (00000H-003FFH).
There are 256 interrupt vectors.
They are used for either hardware or software.
Each vector contains the address of the interrupt service
subroutine, called interrupt.
The first 2 bytes of the vector contain the number that is
loaded into IP register and the next 2 bytes contain the
number that is loaded into the CS register in response to an
interrupt.

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5.5.1. Interrupt Vectors

The interrupt vector map is as shown:
Number Address Function
0 0H-3H Divide error
1 4H-7H Single step
2 8H-BH NMI (hardware interrupt)
3 CH-FH Breakpoint
4 10H-13H Interrupt on overflow
5-31 14H-7FH Reserved for future use
32-255 80H-3FFH User interrupts

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 5.5.2. Interrupt Instructions
The 8086/8088 has three different interrupt
instructions available to the programmer:
INT, INTO and INT3.
There are 256 different software interrupt (INT)
instructions available to the programmer.
Each INT instruction has a numeric operand
whose values ranges from 0 to 255.
Each instruction is 2 bytes long, except INT3 that
is 1-byte software interrupt instruction.

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5.5.2. Interrupt Instructions

The INT 3 is a 1-byte long instruction.
Vector number 3 is called breakpoint interrupt.
It is easy for the programmer to inset a 1-byte
instruction at any point in the software.
The software at the INT 3 interrupt service
subroutine displays all the registers and waits.
It can be used to debug a faulty program.

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 5.5.2. Interrupt Instructions
Interrupt on overflow (INTO) is a conditional interrupt
instruction.
If the overflow flag (OF) is set and the INTO instruction is
encountered in a program, the subroutine whose address is
stored at vector 4 will be called.
IF OF is clear and INTO instruction is encountered, no
interrupt will be called.
The INTO instruction is most widely used following
signed arithmetic to detect overflow error condition.
It appears after every addition and subtraction.

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5.5.2. Interrupt Instructions

A software interrupt instruction (INT N) is executed as
1) It pushes the flags onto the stack.
2) It clears the I and T flags.
3) It pushes CS onto the stack.
4) It fetches the new CS location from the vector table.
5) It pushes IP onto the stack.
6) It fetches the new IP location from the vector table.
7) It jumps to this new location.

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 5.5.2. Interrupt Instructions
The interrupt return instruction (IRET) is used
with the software or hardware interrupt.
IRET is executed as follows:
1) It pops stack data into IP.
2) It pops stack data back into CS.
3) It pops stack data back into the flags.
Whenever the IRET pops the flag back into the
flag register, the prior contents of IF and TF are
restored.

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5.5.2. Interrupt Instructions

Example: Write an interrupt that add the contents of DI, SI,
BP and BX and save the result in AX. Each time this
function is required, an INT 50 instruction is used to call it.
ADDEM: ADD AX,BX
ADD AX,SI
ADD AX,DI
ADD AX,BP
IRET
;Set up vector address
ORG 000C8H ;Set the program at address 200=C8H
DD ADDEM

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 5.5.3. Interrupt Control
There are two instructions used to control the
hardware interrupt structure:
Set interrupt flag (STI)
Clear interrupt flag (CLI).
When the IF = 0, the INTR pin is disabled.
When the IF = 1, INTR is enabled.

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5.6. Miscellaneous Instructions

These instructions provide control of the carry bit, sample
the TEST pin and perform various other functions.
Most of these instructions are used in hardware control.
These instructions include:
Controlling the Carry Flag Bit (CF)
WAIT
HLT
NOP
LOCK Prefix
ESC

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 5.6.1. WAIT
WAIT instruction tests the hardware pin TEST
This pin is used to test a variety of external
hardware events.
If this pin is a logic 1, the 8086/8088 will become
idle and wait for it to become a logic 0.

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5.6.2. HLT
HLT stops the execution of software.
There are only two ways to execute a halt:
By interrupt
By a hardware system reset.

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 5.6.3. NOP
When the microprocessor encounters a NOP, it takes 3
clocking periods to execute.
NOP is used in time delay software.
In machine language programs, it is advisable for the
programmer to leave patch areas every 50 bytes in case the
program needs modification in the future.
These patch areas normally contain NOP instructions so
that the program’s operation will not affected by these
patch areas.

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Co-processor

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 [Link] Prefix
The LOCK prefix is a byte placed before any
8086/8088 instruction to inhibit external
coprocessor in the system from gaining access to
system buses.

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5.6.5. ESC
ESC is an opcode for an external coprocessor.
ESC passes information to the 8087 arithmetic
coprocessor.
Whenever the escape instruction is executed, the
8086/8088 performs a NOP and the external
coprocessor receives a 6-bit opcode encoded in the
ESC instruction.
The ESC instruction accesses a memory location so
that the coprocessor can read or write data if
necessary.

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