Digital Design
1. What is the SOP expression for A= B in a 2-bit magnitude comparator?
a. (A1 ⊙ B1).(A0 ⊙ B1)
b. (A1 ⊙ B1)⊙(A0 ⊙ B1)
c. (A1 ⊙ B1)+(A0 ⊙ B1)
d. None of these
2. The following block diagram is implemented with 3-input NAND gates only
(Din = input variable signal). Without using extra hardware, the minimum
number of NAND gates required:
a. 8
b. 10
c. 12
d. 14
3. Only 2 input NAND gates are used to implement the target circuit. The
correct statement(s) is/are:
a. To implement half adder, minimum number of NAND gates
required are 5
b. To implement full adder, minimum number of NAND gates
required are 9
c. Minimum 2 NAND gates are required to implement carry function in
full adder when sum function is available with NAND gates
d. 1 NAND gate is needed to implement the carry function in half
order when the sum function is available with NAND gates.
4. Consider the following diagram, a seven segment display used to display the
target BCD. ‘x’ is the input and Fa to Fg are outputs connected to the
respective segments of the seven segment display. The circuit is designed to
produce only 2 digits according to the ‘x’ as given below. The minimum
number of logic gates required to design the circuit.
a. One NOT gate
b. One OR gate
c. One OR gate and one NOT gate
d. None of these
5. The following 4 variable k-map is used to derive the SOP expression for
f(A, B, C, D). the minimum number of essential prime implicants and
minimum number of terms present in the final minimized expression?
a. 2, 4
b. 2, 2
c. 2, 3
d. 3, 3
6. The following circuit with two 4x1 MUXes and a 2x1 MUX used to
implement a boolean function. Which of set of values of (x0 x1 x2 x3 x4 x5
x6 x7) will realize the boolean function: f(A B C) = A’ + A’C’ + AB’C
a. (1 1 0 0 1 1 1 0)
b. (1 1 0 0 1 1 0 1)
c. (1 1 0 1 1 1 0 0)
d. (0 0 1 1 0 1 1 1)
7. A 3 variable function is implemented with 2 x 1 MUXes only: the function
delivers high output when one or more input signals are high. The minimum
number of MUXes required?
a. 1
b. 2
c. 3
d. 4
8. Only 2 input NAND gates are used to implement the target circuit. The
correct statement(s) in the following is/are:
a. To implement Half adder, minimum number of NAND gates is 5.
b. To implement Full adder, the minimum number of NAND gates is
9.
c. One more NAND gate is sufficient to implement the carry
function in Half adder when sum is available with NAND gates.
d. None of these
9. The shift register shown below is initially loaded with the bit pattern 1001.
Sequentially the shift register is clocked and with each clock pulse the
pattern gets shifted by one bit position to right. With each shift the bit at
serial input is pushed to the MSB. the correct statement(s) are:
a. The content of the shift register will be 1001 after 14 clocks.
b. The content of the shift register will be 1011 after 4 clocks.
c. The content of the shift register will be 1001 after 6 clocks.
d. It acts as a MOD-7 Counter.
10.The below Asynchronous 4-bit counter: all J and K inputs are ‘1’. The
present state output Q3Q2Q1Q0 = 1101, the output after 35 clocks will be:
a. 0000
b. 1010
c. 1011
d. 0001
11.The fCLK = 320 KHz and output frequency is 20 KHz, the value of ‘K’ is?
a. 2
b. 4
c. 8
d. 16
12.The produce of propagation delay and power dissipation is used to represent:
a. Noise margin
b. Fan-in
c. Fan-out
d. Figure of merit
13.A ROM is used to store the result of two 8-bit unsigned data additions. The
minimum size of ROM required in (K Bits):
a. 12
b. 64
c. 576
d. 9
SOLN: One Operand size = 8 bits, operation = addition
● After adding two 8-bit number, longest resultant = 9 bits
● Address size = combination of inputs = 8 + 8 bits
● Data bus size = 9 bits
● ROM Size = 216 x 9 bits = 64K x 9 bits = 576 K bits
14.A 256 bit DRAM, the number of rows = 4 x (number of columns). Refresh
operation takes 100ns for one row. Total amount of time needed to refresh
entire chip (in ns):
a. 25600
b. 3200
c. 800
d. 6400
15.CMOS circuit is used to implement f(A B C D) = (A’ + B’) + (B’ + C’) +
(C’ + D’). assume that only uncomplemented inputs are available. The
minimum number of FETs (both P and N channel) required?
a. 7
b. 9
c. 8
d. 4
16.Minimum number of 2 input NOR gates required to implement the function
(f) given by the logic circuit shown below:
a. 2
b. 4
c. 5
d. 8
17.Consider the standard boolean function as given: f(A B C D) = m(0, 1, 2, 3,
4, 5, 9, 11, 13, 15) + d(6, 7). The minimized expression in negative logic is:
a. A’D
b. AD’
c. A + D
d. A’ + D
18.Consider the boolean function f(a, b, c, d) = a ⊙ b, which of the following
is/are suitable boolean expressions in the canonical form:
a. f(a, b, c) = m(0, 1, 2, 3, 12, 13, 14, 15)
b. f(a, b, c) = m(4, 5, 6, 7, 8, 9, 10, 11)
c. f(a, b, c) = M(0, 1, 2, 3, 12, 13, 14, 15)
d. f(a, b, c) = M(4, 5, 6, 7, 8, 9, 10, 11)
19.Express the given function f(a, b, c) = a + bc in canonical POS form:
a. M(3, 4, 6, 7)
b. m(0, 1, 2)
c. M(0, 1, 2)
d. m(3, 4, 6, 7)
20.The circuit shown represents a boolean function. How many minterms are
there in the expression;
a. 2
b. 5
c. 3
d. 6
21.In a IEEE 754 single precision floating point representation the exponent
value of 255 and mantissa not equal to 0 indicates that:
a. Infinite number
b. Denormalized number
c. Not a number
d. None of these
SOLN:
In IEEE 754 single precision floating-point representation:
● The exponent field is 8 bits.
● The mantissa (fraction) is 23 bits.
● The exponent value of 255 (i.e., all bits are 1) has special meanings
depending on the mantissa:
Cases:
● Exponent = 255, Mantissa = 0 → Infinity (+∞ or −∞)
● Exponent = 255, Mantissa ≠ 0 → Not a Number (NaN)
22.An X, Y flip flop is designed using T flip flop. Which of the following can
be the boolean function for the input of T of the T flip flop. Given the truth
table of X-Y flip flop:
a. T = X + Y
b. T = X’Qn + Qn’
c. T = X’Qn’ + Y’Qn
d. None of these
23.The following sequential has Q0Q1 = 00. Then MOD of the above counter is:
a. 1
b. 2
c. 3
d. 4
24.A and B are 8 bit registers used to represent the value in 2’s complement.
The operation: (A + B) is performed on the stored data. The arithmetical
overflow occurs for the data:
a. A = 7F16, B = 4516
b. A = 8F16, B = 7F16
c. A = FF16, B = FE16
d. A = 8F16, B = 8F16
25.A device with data transfer rate 50KBPS is connected to the processor in
programmed IO method. Let the interrupt overhead take 5us. Let the transfer
time between CPU and interfacing register is negligible. The minimum
performance gain of operating the device under interrupt driven mode over
operating it under programmed IO mode is:
a. 1
b. 2
c. 3
d. 4
26.Choose the correct statement(s) for the boolean expression
f(a, b, c) = a’b’c + a’bc’+ ab’c’ + abc
a. It is a self dual function
b. It is not a neutral function because it has 2n-1 terms
c. It is a neutral expression
d. It is not consisting of any mutually exclusive term (minterms)
27.Value of ‘F’ for EN = 0 and EN = 1 respectively
a. 0, 0
b. A’, 0
c. A, A’
d. 0, A
28.The propagation delay of all logic gates is 2ns. Initially, A = B = 0, at time t
= t0 both are changed to 1, 1. Then the delay required to produce a stable
output is:
a. 2ns
b. 4ns
c. 6ns
d. 8ns
29.The operation of the circuit shown:
a. Multiplexer
b. Encoder
c. Decoder
d. None of these
Solution continued in the next image:
30.In the logic circuit, select the correct answer(s) using the codes given below:
a. The output Z = 0 for odd number of 1’s at the input x, y, c
b. The output Z = 1 for odd number of 1’s at the input x, y, c
c. The output ‘Z’ can produce difference output of a full substractor
d. Z = 0 for all values of x, y, c