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VLSI Design Exam Questions - BITS Hyderabad

The document outlines the structure and requirements for a comprehensive exam on Analog and Digital VLSI Design at the Birla Institute of Science and Technology, Hyderabad Campus. It includes specific instructions for answering questions, assumptions to be made, and a series of problems related to NMOS and PMOS transistors, circuit design, and logic circuit analysis. The exam covers topics such as current sources, small signal voltage gain, gate design, and circuit identification.

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f20230318
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26 views2 pages

VLSI Design Exam Questions - BITS Hyderabad

The document outlines the structure and requirements for a comprehensive exam on Analog and Digital VLSI Design at the Birla Institute of Science and Technology, Hyderabad Campus. It includes specific instructions for answering questions, assumptions to be made, and a series of problems related to NMOS and PMOS transistors, circuit design, and logic circuit analysis. The exam covers topics such as current sources, small signal voltage gain, gate design, and circuit identification.

Uploaded by

f20230318
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Birla Institute of Science and Technology, Hyderabad Campus

Analog and Digital VLSI Design, Comprehensive Exam Part-B (CLOSED BOOK)
Max. Marks: 50 Max. Time: 105 Min

1. Neglect Velocity saturation, body effect and other second order effects unless explicitly mentioned in the question paper
2. Assume wire delay as zero and Ignore clock skew
3. No marks for writing formulae
[Link] parts of a question has to be answered together
----------------------------------------------------------------------------------------------------------------------------------------------
[Link] the current source shown in the below Fig., dimensions of NMOS transistors M1 and M2 are (W/L) 1 =2, (W/L)2 =10,
VDD= 2.5V, µnCox =100µA/V2, Vtn =0.5V. Ignore channel length, body effect and other second order effects. Assume that M2
is in saturation.
(a) Find the value of RREF such that IREF=100µA. 4M
(b) Find the value of R1 that gives IOUT = 40µA? Assume VG1 = 1.2V and RREF = 20KΩ. 4M
(c) Find the lowest output voltage V OUT for which the circuit in the figure still acts as a current source for a given V G2=
1.2V. 2M

2. A MOS Amplifier shown below has (W/L)1 = 10, (W/L)2 = 20, (W/L)3 =10, IBIAS = 50µA, VDD= 2.5 V, µnCox = 100 µA/ V2,
µpCox = 100 µA/V2, Vtn= Vtp = 0.5V, λn = |λp| = 0.05 V-1 , ɤ=0. Note M1 is NMOS while M2 and M3 are PMOS
transistors. Assume M1 and M2 transistors are in saturation.
(a) Find the current in transistor M1 (Ignore the effect of channel length modulation and body effect) 4M
(b) The small signal voltage gain Av. Consider effect of channel length modulation while ignoring body effect
6M

3. (i) Design XOR and XNOR gate using DCVSL logic gate using least number of transistors 5M
(ii) Design an optimized 3-bit minority circuit using K-Map (output is `1` when majority inputs are 0). Implement the
obtained logic in the dynamic CMOS logic. Assume normal and complement inputs are available. 5M
Page 1-2
4. The figure below is a logic circuit where CK denotes clock.

(a) Is the circuit combinational or sequential? 2M


(b) Is the circuit synchronous or asynchronous? 2M
(c) Identify the circuit and briefly mention its operation? 4M
(d) Complete the below-mentioned table (Assume initially Qm and Qs to be zero) (Write the answers by drawing a Table
as shown below) 4M
C D Qm Qs
K
1 1
0 0
1 0
0 1

[Link] below shows two circuits. The inverter shown in the circuits are realized using Static CMOS logic. Write the
Boolean logic equation for X, Y, G and H. Answers without steps will not be awarded any marks. 10M

*** Page 2-2

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