Cadence-Based Design of a
Biopotential Amplifier with ADC
Integration for EMG Signal
Acquisition and PCB Realization
N Srinath 11022070
Ashwin G P 110122021
Specification Table
Parameter Value Unit Comments
Total Gain ~600 V/V From HPF × INA × LPF × Final Stage
~44.8 dB Log-scaled gain
Bandwidth ~20 – 418 Hz Set by HPF (20 Hz) and LPF (418 Hz) cutoff frequencies
Center Frequency ~250 Hz Frequency with peak system gain
Input Signal Amplitude 0.1 – 5 mV (peak-to-peak) Typical surface EMG signal range
Input Signal Frequency 20 – 500 Hz EMG signal spectrum (dominant content between 50–150 Hz)
High-Pass Filter (HPF) Cutoff = 20 Hz R = 150 kΩ, C = 53 nF
Low-Pass Filter (LPF) Cutoff = 418 Hz R = 80.6 kΩ, C = 4.7 nF
Instrumentation Amp Gain 11 V/V Mid-stage amplification
Post-Gain Stage 54 V/V Final amplifier stage after filtering
Common-Mode Rejection > 80 dB Typical for good-quality instrumentation amplifiers (e.g., INA128)
Power Supply ±5 or ±12 Volts Depends on op-amp and INA used
Current Consumption < 10 mA Depends on op-amp and system load
Output Signal Amplitude Up to 1.5 Vpp Suitable for driving an ADC input
Schematic
EMG input
Instrumentation Amplifier
Analog output
Precision Rectifier with HPF Inverting LPF
Inverting Amplifier
DAC
ADC
01
Function
An instrumentation amplifier (INA) with a
gain of 11 is used to accurately amplify
low-level EMG signals while maintaining
high input impedance and excellent noise
rejection.
This configuration ensures that weak
muscle signals are amplified cleanly
without distortion before further filtering
and processing.
03
Function
A precision rectifier combined with a high-
pass filter with a cutoff frequency around
22.6 Hz is used to convert the bipolar EMG
signals into unipolar signals while
removing very low-frequency noise such
as muscle artifacts and DC offsets.
This filtering ensures stable and clean
signal conditioning for accurate envelope
detection and subsequent processing.
03
Function
An inverting low-pass filter with a
cutoff frequency of 418 Hz is followed
by an inverting amplifier stage with a
gain of 20.
This configuration effectively attenuates
high-frequency noise while amplifying
the filtered EMG signal, ensuring a clean
output suitable for ADC input.
03
AC - Magnitude
PRECISION RECTIFIER
LPF
INVERTING
03
AC - Phase
03
AC Analysis - Explain
1. INA Output
Magnitude: ~1 mV input amplified to ~11 mV.
Phase: ~0°, showing minimal distortion.
Clean differential amplification.
[Link] + Precision Rectifier
Magnitude: Below 20 Hz attenuated; output is unipolar.
Phase: Sharp shift near cutoff due to HPF.
Note: Filters muscle artifacts and removes DC.
[Link] Output
Magnitude: Stable up to 418 Hz; rolls off beyond.
Phase: Lag increases near cutoff.
Attenuates high-frequency noise.
[Link] Output
Magnitude: Up to ~1.5 V from original mV-level input.
Phase: Shows bandpass behavior.
Full gain and clean bandwidth achieved. 03
Transient Analysis
INA
PRECISION
RECTIFIER
LPF
Transient Analysis - EMG based signal
ADC - Specification
Parameter Specification
Resolution 7 bits
Number of Output Levels 128
Input Voltage Range 0.5 mV – 5 mV
Amplification Factor 600
ADC Input Voltage Range 0 V – 3.3 V
Output Code Range 0 to 127 (7-bit binary)
Reference Voltage Range 0 V to 3.3 V
LSB Size (Resolution Step) 25.78 mV
Output Format Digital (7-bit binary)
Power Supply Voltage 3.3 V
Input Signal Type Single-ended analog
Output Signal Type Digital (CMOS compatible)
Transient Analysis - EMG based signal
ADC INPUT SIGNAL
Transient Analysis - EMG based signal
DIGITAL SIGNALS FROM ADC
Transient Analysis - EMG based signal
ADC INPUT SIGNAL vs DAC OUTPUT SIGNAL
ADC input
DAC output
ADC and DAC
Type: Flash ADC (also known as parallel ADC).
Conversion Method: Direct quantization of the analog input voltage into a 7-bit digital value at each clock
edge — no iterative or feedback process involved.
Speed: Very fast conversion, characteristic of flash ADCs, since it doesn't require multiple clock cycles.
Output Format: 7 separate digital output lines (out6 to out0), each representing one bit of the converted
value.
Trigger Mechanism: Conversion is triggered on a specific clock edge (rising or falling), based on the dir
parameter.
Behavioral Modeling: Implements quantization using arithmetic rather than comparator arrays — suitable
for simulation but abstracted from physical comparator implementation.
Resolution: 7-bit resolution, meaning 128 discrete output levels (2^7 = 128).
Application Use: Ideal for modeling high-speed data conversion in analog-mixed signal simulation
environments.
ADC - Veriloga Code
`include "[Link]"
// 7-bit Analog to Digital Converter (ADC) with separate output lines
// Internal variables
integer result;
module adc (
analog begin
out6, out5, out4, out3, out2, out1, out0, // 7 separate output lines
@(cross(V(clk)-thresh, dir) or initial_step) begin
in, clk
); // Quantize input voltage to 7 bits
result = levels * ((V(in) - vmin)) / (vmax - vmin);
// Parameters if (result > levels-1)
parameter real vmin = 0.0; // Minimum input voltage (V) result = levels-1;
parameter real vmax = 1.0 from (vmin:inf); // Maximum input voltage (V) else if (result < 0)
parameter real td = 0 from [0:inf); // Delay from clock edge to output (s) result = 0;
parameter real tt = 0 from [0:inf); // Transition time of output (s) end
parameter real vdd = 5; // Voltage level of logic 1 (V) // Assign each bit to a separate output
parameter real vss = 0; // Voltage level of logic 0 (V) V(out6) <+ transition((result & (1<<6)) ? vdd : vss, td, tt);
parameter real thresh = (vdd+vss)/2; // Logic threshold level (V) V(out5) <+ transition((result & (1<<5)) ? vdd : vss, td, tt);
parameter integer dir = +1 from [-1:1] exclude 0; // 1=rising, -1=falling V(out4) <+ transition((result & (1<<4)) ? vdd : vss, td, tt);
V(out3) <+ transition((result & (1<<3)) ? vdd : vss, td, tt);
// Local parameters
V(out2) <+ transition((result & (1<<2)) ? vdd : vss, td, tt);
localparam integer bits = 7;
V(out1) <+ transition((result & (1<<1)) ? vdd : vss, td, tt);
localparam integer levels = 1<<bits; // 128 levels for 7 bits
V(out0) <+ transition((result & (1<<0)) ? vdd : vss, td, tt);
// Port declarations end
input in, clk; endmodule
output out6, out5, out4, out3, out2, out1, out0;
voltage in, clk;
voltage out6, out5, out4, out3, out2, out1, out0;
DAC - Veriloga Code
`include "[Link]" // Internal variables
integer value;
// 7-bit Digital to Analog Converter (DAC) with separate input lines
real analog_out;
localparam integer bits = 7;
module dac (
localparam integer levels = 1 << bits; // 128 levels
out, // Analog output
in6, in5, in4, in3, in2, in1, in0 // 7 separate digital inputs
); analog begin
// Convert 7-bit digital input to integer value based on threshold
// Parameters value = 0;
parameter real vmin = 0.0; // Minimum analog output (V) value = value + ((V(in6) > thresh) ? (1<<6) : 0);
parameter real vmax = 1.0 from (vmin:inf); // Maximum analog output (V) value = value + ((V(in5) > thresh) ? (1<<5) : 0);
parameter real td = 0 from [0:inf); // Delay before analog output responds (s) value = value + ((V(in4) > thresh) ? (1<<4) : 0);
parameter real tt = 0 from [0:inf); // Transition time (s) value = value + ((V(in3) > thresh) ? (1<<3) : 0);
parameter real vdd = 5; // Logic 1 voltage level (V) value = value + ((V(in2) > thresh) ? (1<<2) : 0);
parameter real vss = 0; // Logic 0 voltage level (V) value = value + ((V(in1) > thresh) ? (1<<1) : 0);
parameter real thresh = (vdd + vss)/2; // Logic threshold level (V) value = value + ((V(in0) > thresh) ? (1<<0) : 0);
// Port declarations
// Map digital value to analog voltage
input in6, in5, in4, in3, in2, in1, in0;
analog_out = vmin + (vmax - vmin) * value / (levels - 1);
output out;
voltage in6, in5, in4, in3, in2, in1, in0;
voltage out; // Output analog voltage with transition behavior
V(out) <+ transition(analog_out, td, tt);
end
endmodule
KiCad Schematic
Function
DECOUPLING CAPACITORS
These capacitors are connected
between the power supply rails (+5V)
and ground, close to the op-amp ICs.
Noise Removal: They filter out high-
frequency noise or voltage spikes from
the power supply, ensuring that the op-
amps receive a clean and stable voltage.
03
Function
INSTRUMENATION AMPLIFIER
U5A , U5B(TLV9062 Op Amp)
Buffers the EMG signal from the electrodes,
presenting high input impedance.
INA accurately amplifies low-level EMG
signals while maintaining high input
impedance and excellent noise rejection.
The op-amps in feedback ensure better
CMRR enhancing the signal.
03
Function
PRECISION RECTIFIER + HPF
A precision rectifier combined with a high-
pass filter to convert the bipolar EMG
signals into unipolar signals while removing
very low-frequency noise such as muscle
artifacts and DC offsets.
This filtering ensures stable and clean
signal conditioning for accurate envelope
detection and subsequent processing.
03
Function
SALLEN-KEY INVERTING LOW-PASS FILTER
The Sallen-Key low-pass filter in ensures
that only the relevant muscle activity
frequencies are passed to the next stage,
while unwanted high-frequency noise is
effectively suppressed, resulting in a clean
and usable EMG signal for analysis and
processing.
03
Function
ADC - ADS1115IDGS
The ADC (Analog-to-Digital Converter)
converts the processed analog EMG signal
into a digital format.
This digital data can then be read and
analyzed by a microcontroller or computer
for further processing, display, or storage.
It enables precise, real-time monitoring
and analysis of muscle activity in digital
systems.
03
PCB Design
3D VIEW
03
PCB Design
Two layers of copper were used with vias in between to rout the connections efficiently.
FRONT COPPER BACK COPPER
Data Captured in Analog
Observation
Commercial EMG Amplifier Output (Green Graph):
The green waveform, captured after ADC, shows clear and well-defined EMG signals, indicating high
amplification, effective filtering, and strong noise rejection in the commercial amplifier.
Custom PCB Amplifier Output (Red Graph):
The red waveform from our PCB amplifier shows weaker EMG signals, likely due to lower gain or limited
filtering, making the signal less distinct compared to the commercial system.
Conclusion:
The comparison highlights the need to improve gain and signal conditioning in our design to achieve
signal clarity suitable for research or commercial use.
To support this comparison, key performance metrics were calculated and reviewed — revealing that
the current system performs at a moderate level with room for improvement.
Performance of System
Common Mode Rejection Ratio (CMRR): 85 dB
Signal-to-Noise Ratio (SNR): ~20 dB
Practical Bandwidth: 15 Hz – 400 Hz
Practical Gain at 50% Potentiometer Setting: 500×
Input-Referred Noise: 50µV RMS
Limitations
SMD Soldering Quality
Some surface-mount components are extremely small and may not be soldered properly, which can lead to
unreliable connections and unpredictable behavior.
Excessive Component Count
The use of many ICs increased complexity. A simplified design using fewer analog components with digital
filtering (e.g., via microcontroller or DSP) could achieve similar performance with cleaner hardware.
Not Yet Research-Grade
While the system performs basic EMG acquisition, it currently lacks the stability and precision required for
high-quality research use. Further improvements are needed in signal fidelity and noise performance.
High Power Consumption
The current design consumes more power than necessary due to the number of active components. Future
revisions should aim to optimize for efficiency and reduce unnecessary circuitry.
Conclusion
Theoretical Study & Design Insights:
As part of the design process, various types of amplifier configurations—such as instrumentation,
differential, and operational amplifiers—were studied in depth to understand their suitability for biomedical
signal processing, particularly in handling low-amplitude, high-impedance signals like EMG.
Cadence-Based Design & Simulation:
An EMG amplifier with integrated ADC was designed and simulated using Cadence tools to accurately
acquire and condition biopotential signals such as EMG. Key design parameters like gain, bandwidth, input
impedance, and noise performance were carefully considered.
Hardware Implementation & Testing:
A corresponding PCB was developed based on the Cadence design, assembled, and thoroughly tested. The
analog output was analyzed and compared against a commercial EMG amplifier to evaluate signal quality,
gain accuracy, and ADC performance.
Conclusion & Future Scope:
The current design demonstrates functional signal acquisition, but further optimization in gain stages,
filtering, and noise rejection is required. With such improvements, the system can be refined for reliable use
in research labs or commercial biomedical devices.