Gate Level Modelling
❑ Gate primitives
❑ Instantiation of primitives
❑ Examples
❑ Gate delay
Gate Types
❑ Available as primitives in Verilog
❑ Instantiate like module except that
they are predefined in Verilog
❑ No need to have separate module
Gate Primitivies
and or xor
nand nor xnor
and a1 (out,in1,in2);
Gate instantiation
// basic gate instantiations
and a1 (out,in1,in2);
nand na1 (out,in1,in2);
or or1 (out,in1,in2);
nor nor1 (out,in1,in2);
xor x1 (out,in1,in2);
xnor nx1 (out,in1,in2);
// More than two inputs 3 input nand gate
nand na1_3inp (out,in1,in2,in3);
// Gate instantiation without instance name
and ( out,in1,in2); // legal gate instantiation
Gate Truth Tables
and i2 0 1 X Z
i1
0 0 0 0 0
1 0 1 X X
X 0 X X X
Z 0 X X x
nand i2 0 1 X Z
i1
0 1 1 1 1
1 1 1 X X
X 1 X X X
Z 1 X X x
Gate Truth Tables
Or 0 1 X Z
0 0 1 X 1
1 1 1 1 1
X X 1 X X
Z X 1 X X
Nor 0 1 X Z
0 1 0 X 1
1 0 0 0 0
X X 0 X X
Z X 0 X X
Gate Truth Tables
Xor 0 1 X Z
0 0 1 X X
1 1 0 X X
X X X X X
Z X X X X
Xnor 0 1 X Z
0 1 0 X X
1 0 1 X X
X X X X X
Z X X X X
Buf/ Not Gate
buf not
Gate Instantiation of Buf / Not gate
// basicgate instantiations
buf b1 ( Out1 , In);
not n1 ( Out1 , In);
// More than two outputs
buf b1_2out ( Out1 , Out2 , In);
// Gate instantiation with out instance name
not (Out1 , In);// legal gate instantiation
buf / not gates
Truth Tables
BUF IN OUT NOT IN OUT
0 0 0 1
1 1 1 0
X X X X
Z X Z X
bufif/notif
bufif1 notif1
bufif0 notif0
bufif/notif Truth Table
Bufif1 ctrl 0 1 X Z
in
0 Z 0 L L
1 Z 1 H H
X Z X X X
Z X X X X
Bufif0 ctrl 0 1 X Z
in
0 0 Z L L
1 1 Z H H
X X Z X X
Z X Z X X
bufif/notif Truth Table
notif1 ctrl 0 1 X Z
in
0 Z 1 H H
1 Z 0 L L
X Z X X X
Z Z X X X
Notif0 ctrl 0 1 X Z
in
0 1 Z H H
1 0 Z L L
X Z Z X X
Z X Z X X
Gate instantiation of bufif /
notif Gate
// instantiation of Bufif Gates
bufif1 b1 ( Out , in, ctrl1);
bufif1 b1 ( Out , in, ctrl1);
// instantiation of Notif Gates
notif1 b1 ( Out , in, ctrl1);
notif1 b1 ( Out , in, ctrl1);
❑ 1-bit Half adder
module adder (sum, carry, a, b);
input a, b;
output sum, carry;
xor G1 (sum, a,b);
and G2 (carry, a,b);
endmodule
❑ 4X1 Mux
❑ 2X1 Mux using buf
Design 2x1 Multiplexer using
bufif0 and bufif1
❑ wor
❑ wand
Example 1: 4x1 Multiplexer
Example 1: 4x1 Multiplexer
Example 1: 4x1 Multiplexer
// Module 4-to-1 multiplexer. Port list is taken directly from the I/O diagram
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
// Internal wire declarations
wire s1n, s0n;
wire y0, y1, y2, y3;
What happens if the input I is declared as vector
// Gate instantiations
Synthesis results/serial data
// Create s1n and s0n signals
not (s1n, s1);
not (s0n, s0);
// 3-input and gates instantiated
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
// 4-input or gate instantiated
or (out, y0, y1, y2, y3);
endmodule
Time Directive
❑ `timescale time-unit/time-precision
❑ `timescale 1ns/100 ps
❑ 1 Time unit = 1 ns
❑ Time precision is 100ps (0.1 ns)
❑ 10.512ns is interpreted as 10.5ns
Gate Level Modeling
❑ Gate Delays
❑ Rise Delay
❑ Fall Delay
❑ Turn-off Delay
Gate Delays
❑ Rise Delay
❑ Gate output transition to a 1 from
another value
Gate Delays
❑ Fall Delay
❑ Gate output transition to a 0 from
another value
Gate Delays
❑ Turn-off Delay
❑ Gate output transition to a high
impedance value from another value
Gate Delay
//Delay of delay_time for all transitions
and #(delay_time) a1(out, i1, i2);
//Rise and Fall Delay specification.
and #(rise_val, fall_val) a2(out, i1, i2);
//Rise, Fall and turn-off Delay specification
bufif0 #(rise_val, fall_val, turnoff_val) b1(out, in, control);
Gate Delay
and #(5) a1(out, i1, i2); //Delay of 5 for all transitions
and #(4,6) a2(out, i1, i2); //Rise = 4, Fall = 6
bufif0 #(3,4,5) b1(out, in, control);//Rise = 3, Fall = 4, Turn-off = 5
Gate Delays
❑ Min/Typ/Max Value
Gate Delays
// one delay
and #(4:5:6) al(out, i1, i2);
//if +mindelays, delay=4
//if +type delay, delay=5
//if +maxdelays, delay=6
Gate Delays
// Two delays
and #(3:4:5, 5:6:7) a2(out, i1, i2);
//if +mindelays, rise=3, fall=5, turn-off = min(3,5)
//if +typedelays, rise=4, fall=6, turn-off = min(4,6)
//if +maxdelays, rise=5, fall=7, turn-off = min(5,7)
Gate Delays
// Three delays
and #(2:3:4, 3:4:5, 4:5:6) a3(out,
i1, i2);
// if +mindelays, rise=2, fall=3, turn-off = 4
// if +typedelays, rise=3, fall=4, turn-off = 5
// if +maxdelays, rise=4, fall=5, turn-off = 6
Delay Example
Delay Example Cont..
//Define a simple combination module called D
module D (out, a, b, c);
//I/O port declarations
output out;
input a, b, c;
//Internal nets
wire e;
// Instantiate primitive gates to build the circuit
and #(5) a1(e, a, b); // Delay of 5 on gate a1
or #(4) o1(out, e, c); //Dealy of 4 on gate o1
endmodule
Stimulus for Module D with
Delay
//stimulus (top-level module)
module stimulus;
//Declare variables
reg A, B, C;
wire OUT;
//Instantiate the uut
D di (OUT, A, B, C);
//stimulus the inputs. Finish the simulation at 40 time units.
initial
begin
A=1’b0; B= 1’b0; C= 1’b0;
#10 A=1’b1; B= 1’b1; C= 1’b1;
#10 A=1’b1; B= 1’b0; C= 1’b0
#20 $finish;
end
endmodule
Waveform for Delay
Simulation
A=1’b0; B= 1’b0; C= 1’b0;
#10 A=1’b1; B= 1’b1; C= 1’b1;
#10 A=1’b1; B= 1’b0; C= 1’b0
Specified Delay
❑ Rise/Fall/Turnoff delay types (cont’d)
❑ If no delay specified
❑ Default value is zero
❑ If only one value specified
❑ It is used for all three delays
❑ If two values specified
❑ They refer respectively to rise and fall delays
❑ Turn-off delay is the minimum of the two
Specified Delay
❑ Min/Typ/Max Values
❑ Another level of delay control in Verilog
❑ Each of rise/fall/turnoff delays can have
min/typ/max values
not #(min:typ:max, min:typ:max, min:typ:max) n(out,in)
❑ Only one of Min/Typ/Max values can be used in the
entire simulation run
❑ It is specified at start of simulation, and depends
on the simulator used
❑ ModelSim options
ModelSim> vsim +mindelays
ModelSim> vsim +typdelays
ModelSim> vsim +maxdelays
❑ Typ delay is the default
Gate Delay: ASIC &
simulation delay
❑ Significance
❑ ASIC : Technology specific delay
❑ Verilog: Simulation Oriented
Module Instantiation
Structural Modelling
Port Connection
❑ Connections between signals
specified in the module instantiations
and the port in the module definition
❑ Connection by position
❑ Connection by name
Dr. Vaishali H. Dhare
Port Connection
❑ Connection by position
parent_mod
Dr. Vaishali H. Dhare
Port Connection
❑ Connection by Name
parent_mod
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Port Connection Rules
❑ Inputs
❑ Outputs
❑ Inouts
❑ Width Matching
❑ No. of ports, unconnected
Dr. Vaishali H. Dhare
Port Connection Rules
❑ Internal, external
Internal External top
Dr. Vaishali H. Dhare
Port Connection Rules
module fulladder(sum,
module Top;
cout, a,b, cin);
reg [3:0]A,B;
input [3:0] a,b;
reg C_IN;
output sum, cout;
reg [3:0]SUM;
--
wire [3:0] C_OUT;
--
fulladder fa0(SUM[0],C_OUT[0],A[0],B[0],C_IN);
endmodule
endmodule
Illegal connection because output port sum in module
fulladder is connected to a register variable SUM in module
Top.
Dr. Vaishali H. Dhare
Example 2: 4-bit Ripple Carry
Full Adder
❑ 1-bit full adder
Example 2: 4-bit Ripple Carry
Full Adder
// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);
// I/O port declarations
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, c1, c2;
// Instantiate logic gate primitives
xor (s1, a, b);
and (c1, a, b);
xor(sum, s1, c_in);
and (c2, s1, c_in);
or (c_out, c2, c1);
endmodule
Example 2: 4-bit Ripple Carry
Full Adder
❑ 4-bit Ripple Carry Full Adder
Example 2: 4-bit Ripple Carry
Full
// Define a 4-bit full adder
Adder
module fulladd4(sum, c_out, a, b, c_in);
// I/O port declarations
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;
// Internal nets
wire c1, c2, c3;
// Instantiate four 1-bit full adders.
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);
endmodule
1 2
Dr. Vaishali H. Dhare
1. D flip-flop
// module DFF with asynchronous reset
module DFF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
always @(posedge reset or negedge clk)
if (reset)
q = 1'b0;
else
q = d;
endmodule
Dr. Vaishali H. Dhare
2. T flip-flop
module TFF(q,clk,reset);
output q;
input clk, reset;
wire d;
DFF dff0(q,d,clk,reset);
not n1(d, q); // not is a Verilog provided primitive.
endmodule
Dr. Vaishali H. Dhare
Instances
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module TFF are created.
TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
TFF tff2(q[2],q[1], reset);
TFF tff3(q[3],q[2], reset);
endmodule
Dr. Vaishali H. Dhare
Array Instances
wire [ 7: 0 ] OUT , IN1, IN2 ;
// basic gate instantiations.
nand n_gate [7 : 0 ] ( OUT, IN1 , IN2) ;
// This is equivalent to the following 8 instantiations
nand n_gate0 (OUT[0], IN1[0] , IN2[0]) ;
nand n_gate1 (OUT[1], IN1[1] , IN2[1]) ;
nand n_gate2 (OUT[2], IN1[2] , IN2[2]) ;
nand n_gate3 (OUT[3], IN1[3] , IN2[3]) ;
nand n_gate4 (OUT[4], IN1[4] , IN2[4]) ;
nand n_gate5 (OUT[5], IN1[5] , IN2[5]) ;
nand n_gate6 (OUT[6], IN1[6] , IN2[6]) ;
nand n_gate7 (OUT[7], IN1[7] , IN2[7]) ;