ICSSR-RP-2021-304

31st August 2021 04:43:00

INDIAN COUNCIL OF SOCIAL SCIENCE RESEARCH

Research Programme

Security: Internal Security,

External Security, Borders,
Board Discipline
Cyber Security, Energy
Security

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I. Personal Information

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1. Name of the Applicant Kamaraj A

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Department of ECE, Mepco Schlenk Engineering
College, Sivakasi - 626005, Tamilnadu, India

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9865588214
2. Address for Communication :

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kamarajvlsi@[Link]
Tamil Nadu
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626005
116/57, 2 nd Oorani Street, Kovilpatti
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3. Permanent Address : Tamil Nadu

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628501
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4. Date of Birth (DD/MM/YYYY) : 10/03/1982, Age: 39 years 5

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5(a). Mother’s Name : Jeyamani A

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5(b). Mobile Number : 8508268268

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5(c). Email Id :
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6(a). Father’s Name : Arunachalam

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6(b). Mobile Number : 8508268268

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6(c). Email Id :
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Designation: Associate Professor

Name: Mepco Schlenk Engineering College, Sivakasi
Address: Department of ECE, Mepco Schlenk
Engineering College, Sivakasi - 626005, Tamilnadu,
7. Employer Details :
India
Mobile Number: 9865588214
Email: kamarajvlsi@[Link]
Website: [Link]
Category:OBC, Gender: Male,Person with Benchmark
9. Indicate your category :
Disability: No
10. Whether received any financial
No
assistance from ICSSR
11. Whether received any
assistance/project from any other
No
institution e.g. UGC, ICAR, CSIR, ICPR,
ICHR, etc. :

II. Educational Qualifications

Year of
Name of Degree Name of the University % of marks Disciplines

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Passing

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Master's Anna University 2006 80 VLSI Design

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M Phil

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Ph D. Anna University 2020 NA Reversible Logic

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Post-Doctoral
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III-Research Experience of the Project Director
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Brief Detail (Title and

Number
supporting Institution)
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Projects Completed (Maximum 5) 0 NA

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Ongoing projects, if any (with

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0 NA
completion date)
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Fellowships 0 NA
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Ph.D Guidance NA
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0
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[Link] Guidance 0 NA
Papers in Journals, Edited Books/Reports Published, etc.(Details of up to best 5) :
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 Is the
Journal
Scopus
Name of the Journal, Month, Year and
Sl Indexed
Title of the Article Place of Publication and Volume of Publication
No. and UGC
Frequency with Page Nos.
CARE
list?
(Yes/No)
Multi-Port Memory Design Informacije Midem-
in Quantum Cellular Journal of Microelectronics May 2021, Vol. 51, pp.
1. Yes
Automata Using Logical Electronic Components 49-61
Crossing and Materials, Slovenia

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A comprehensive review on

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accuracy in ultrasonic flow
October 2020, Vol. 10,

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2. measurement using AIP Advances, USA Yes
pp.105221-105221
reconfigurable systems and

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deep learning approaches
Design of integrated
Microprocessors and May 2019, Vol. 69, pp.

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3. reversible fault-tolerant Yes

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Microsystems 16-23
arithmetic and logic unit ie
Informacije Midem-
Design of Fault-Tolerant
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Journal of Microelectronics July 2018, Vol. 48, pp.
4. Reversible Floating Point Yes
Electronic Components 169-179
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Division
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and Materials, Slovenia

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Design of fault-tolerant
Journal of National Science
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reversible Vedic multiplier January 2020, Vol. 47,

5. Foundation Sri Lanka , Sri Yes
in quantum cellular pp. 371-382
Lanka
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automata
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Fault Tolerance in
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Reversible Logic Circuits Computing and May 2021, Vol. 39, pp.
6. Yes
and Quantum Cost Informatics, Slovakia 1099-1116
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Optimization
Realization and
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Optimization of Quantum Journal of Computational

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May 2020, Vol. 5, pp.

7. Equivalent Circuits of and Theoretical Yes
2080-2084
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Reversible Combinational Nanoscience, USA

Circuits
Low Cost Child Abduction Indian Journal of Public
December 2018, Vol. 9,
8. Prevention with RFID Health Research & No
pp. 371-375
Technology Development, India
9.
10.
Participation in Research Projects(also with capacity Best 3).
Nil
Any other important Academic Achievement (approx. 100 words)
Having 15 years of Teaching experience for UG and PG Students. Have taught Linear Integrated
Circuits, VLSI Design, Computer Architecture and Low Power VLSI. Ph.D. research in
Reversible Logic based arithmetic unit design.
IV Affiliation Details
Name of the affiliating institution
Mepco Schlenk Engineering College
Department of ECE, Mepco Schlenk Engineering
Postal address of affiliating institution :
College, Sivakasi 626005 , Tamil Nadu , 626005
Phone Number 9865588214
kamarajvlsi@[Link];

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Email ID

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kamarajvlsi@[Link]

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Website [Link]

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Type of affiliating institution :

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V Details of Project Co-Directors (if any, Maximum 3)

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Name and Address with contact details
Present Position Institution
Mobile No/email ID ie
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G. Indumathi, Professor, Department of
ECE, Mepco Schlenk Engineering Mepco Schlenk Engineering
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College, Sivakasi 626005, 9443867990, College

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gindhu@[Link]
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VI Project Proposal
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(i) Title of the Project Proposal :

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Machine Learning based Power Analysis Attack evaluation of Cryptosystems using FPGA for
Cyber Security
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(ii) Abstract (approx. 200 words)

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Security in modern communication systems is the greatest need in the current scenario. A
mathematically highly secure algorithm runs on a cryptographic chip on these communication
devices, but their secret private data can be at risk due to side-channel leakage information. One
such possible leakage based attack is a side-channel power analysis attack. This proposed research
focuses on retrieving secret-key information, by performing machine-learning-based analysis on
leaked power-consumption signals, from Field Programmable Gate Array (FPGA)
implementation of the elliptic-curve algorithm captured from a Kintex-7 FPGA chip while the
elliptic-curve cryptography (ECC) algorithm is running on it. In this methodology capturing the
power analysis data, preparing an input dataset and Support Vector Machine (SVM) based
machine-learning analysis to classify the secret-key bits are properly formulated using the specific
algorithms and procedure. The classification process of SVM can be improved by adopting
Principle Component Analysis (PCA) as a pre-processing filter, which removes input noises.
Research results will reveal how pre-processing filters improve the classification accuracy in the

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communication prototype environment and show how various signal properties can provide

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accurate secret classification with a smaller feature dataset.

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(iii) Introduction of the Proposed Study (approx. 400 words)

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Nowadays data manipulation on a voluminous amount of information is very common in almost

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all applications. Mobile phones and embedded systems running with many applications, which are

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accessing almost all the details stored in the mobile/device without the knowledge of the user. In
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addition to that, Internet of Things (IoT) based data collection and data manipulation is also
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common in the present modern era. In such scenarios protecting the sensitive and secured data
against the attacks, especially in defence, satellite communication and navigation is very crucial.
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Attacks involved in multiple parts of the security system are difficult to predict and model those
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attacks. Wide-ranging security in a cipher system requires due understanding and cooperation
among software developers and hardware engineers. The cryptographic primitive has two
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significant views: one is an abstract mathematical object (called Cryptanalysis) and the other is
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programs that run on a processor in the given environment with specific characteristics (relates
Physical Security). Physical attacks in cryptographic systems capture the secret parameters
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involved during the crypto-computation process. These attacks are more harmful than classical
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cryptanalysis and they have to be looked into very earnestly. Generally, the physical attacks are
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classified into two major categories: 1) Invasive (de-packaging the chip) and Non-invasive (Time,
Power, EMF, etc…); 2) Active (tamper the device function) and Passive (observe the device
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function). Apart from that on the leakage of information of the chip, attacks can be grouped as, 1.
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Probing attacks 2. Fault Induction attacks 3. Timing attacks 4. Power analysis attacks 5.
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Electromagnetic analysis attacks Among them, the last three are categorized as ‘side-channel
attacks’ (SCA), in which the physical information leaking from various sources or channels is
captured [1].
(iv) Major Research Works Reviewed: 1) International and 2) [Link] less than 15 to
20 important works (approx. 400 words) :
Side-channel Power analysis based research work has been started in 1999 [2], where Simple
power analysis (SPA) and differential power analysis (DPA) were performed on 50 different
products. In [3] Kocher explained the SPA and DPA for Advanced Encryption Standard
(AES-128). Additionally, it has stated about the correlation power analysis, which is a variant of
DPA. The elliptic curve digital signature algorithm (ECDSA) running on an iOS mobile phone
(iPhone) has been attacked by using an improvised magnetic probe [4], whose cost is very cheap.
SPA and DPA based side-channel attacks were done on Elliptic curve cryptography [5], RSA [6]
and DES [7]. The results proved that all these algorithms are prone to various types of side-
channel attacks [5-8]. Mutual information analysis [9], algebraic side-channel attack analysis [10],
normalized inter-class variance [11] optimal linear transforms [12] and frequency selective
filtering [13] are the additional statistical, mathematical approaches that are proposed to improve
the side-channel attack analysis process. The improved double-and-add-always (DAA) algorithm
can reduce the frequency of memory access; thereby statistical timing analysis will not have the

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clue to decrypt the private key [13]. The effectiveness of DPA can be reduced by introducing

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noises in the power traces to misalign it. But, the Principle component analysis (PCA) removes the
noises present in the traces and it helps the attacker to effectively retrieve the secret information

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with a lesser number of traces [14, 15]. The relationship between cryptography and machine
learning is seeded in [16]. Recently, this concept has been enhanced with many emerging machine

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learning algorithms. Among the machine learning algorithms, the support vector machine (SVM)

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algorithm is popularly used for this purpose and it can reveal the secret key with very few power
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traces [17, 18]. The combination of PCA and Machine learning algorithms (Autoencoder,
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Random Forest, Multilayer Perceptron, LSTM and Convolutional neural network) [20] recovers
the masked AES secret information with higher accuracy of up to 90% [19, 20, 21]. But notably,
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when the number of traces for the training set is increased beyond a certain level, the classification
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is providing inconsistent results [19]. In addition to SVM, the Decision tree classification
algorithm also performs well for the DPA attack [22]. In [23] four classifiers (Random Forest,
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Support Vector Machine, Naïve Bayes and Multilayer Perceptron) are used for secret key
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identification. Among them, it is observed that SVM is providing better results in combination
with PCA based pre-processing [23]. Generally, side-channel power attack has been evaluated on
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programmable devices such as FPGAs and Microcontrollers. Nowadays FPGAs are available with
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more sophisticated features. The vulnerability of FPGAs against the power analysis was initiated
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in [7, 8] for ECC. Thereafter, Spartan-3 [18], Artix-7 [13], Virtex-5 [21] and Kintex-7 are used
for implementing the cryptography algorithms for side-channel power analysis attacks. Amongst
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them, the SASEBO GII board (with Virtex-5 FPGA) [3, 22] has been specially designed for side-
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channel attack analysis [24]. In addition, from the literature reviews, it is found that many
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countermeasure methods were proposed against the power analysis attack. They are balancing
hamming weights, leakage reduction [3], introducing noises, blinding, masking [16, 17], parallel
load instructions and reducing memory access [13]. Security of algorithms depends on secured
communication systems developed using those algorithms. Among the most known symmetric
algorithms, AES is used in many [Link] view of the same, popularly adopted asymmetric
encryption is RSA and ECC [25]. Most of the commercial security needed applications are
developed using ECC cryptoprocessor [26, 27]. The security of the ECC can be improved by
double-and-add-always, modular addition/subtraction [25] and Montgomery multiplication [26]
operations.
(v) Identification of Research Gap (approx. 300 words) :
Key Observations: • Asymmetric encryption is having better security than symmetric. In that,
ECC has good private key security with modular hardware architectures. • DPA reveals more
secret information than SPA. • The efficiency of the nonintrusive power analysis attack can be
improved with the combination of pre-processing (PCA) and Machine learning algorithms (SVM,
RF, CNN). • The SCA analysis using FPGAs are popular in recent years. Among the
cryptographic algorithms, asymmetric algorithms such as RSA, ECC, Diffie-Hellman ensures
better security. In that, ECC has faster key generation, competent security with a lesser number of
key bits and less time complexity. The security of the ECC can be further improved by
incorporating modular arithmetic architectures. For active power analysis attacks, DPA reveals
secret data more effectively against the countermeasures. The effectiveness of the DPA can be
further improved by adopting signal conditioning methods. One such methodology which could
remove the noises present in the signal is Principal Component Analysis (PCA). Moreover, the
emerging machine learning algorithms such as SVM, RF and CNN are capable of effectively

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classifying the signals. Hence in this proposal, it is decided to evaluate FPGA based

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implementation of robust ECC architecture. Also, it is planned to incorporate DPA based analysis
with pre-processing (PCA) and machine learning algorithms to extract the secret data information.

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Finally, the extracted secret data will be validated.
(vi) Objectives of the Proposed Study (approx. 100-150 words):

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• To design and implement the ECC Crypto Processor in FPGA. • To develop a Nonintrusive
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Power analysis attack in ECC Crypto Processor to record the power traces. • To identify the secret
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key of the ECC Crypto Processor using Differential Power Analysis (DPA) and Machine
Learning. • Validate the Power analysis attack. A highly automated secured ECC Crypto processor
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has to be designed with modulo arithmetic operations. The designed Crypto processor has to be
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converted into software codes and to be implemented in SAKURA-X (SASEBO GIII) FPGA
board. Thereafter, the power traces are to be recorded without harming the device (non-intrusive
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manner) while the crypto-computations running on the FPGA device. The recorded power traces
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are then applied with statistical DPA and machine learning algorithms to extract the secret key
information. The obtained secret key has to be evaluated against the correct key to ensure the
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robustness of the Crypto processor against SCA.

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(vii) Major Research Question/Hypotheses (approx. 150-200 words):

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The Indian Computer Emergency Response Team (CERT-In) observed over 6.07 lakh cyber
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security incidents in the first six months of 2021, of which about 12,000 incidents were related to
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government organizations. It has been observed that attackers are compromising computer systems
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located in different parts of the world and use masquerading techniques and hidden servers to hide
the identity of actual systems from which the attacks are being launched. The government is
operating many centres for analyzing and generating necessary awareness of existing and potential
cyber security threats. Even after that, we are observing many kinds of security attacks. This
research hypothesizes that, if attacks are implicated under various security parts of the system,
then they are complicated to observe and mock-up them. Out of all attacks, cryptographic physical
attacks are more detrimental than other traditional cryptanalysis and need some intense actions.
The research goal is framed by following the research hypothesis by using a fast key generating
method like ECC with a lesser number of key bits and analyzing the attack detection by
differential power analysis.
(viii) Proposed methodology for the research work (approx. 400 words)
The ECC core design, gets a point on the ECC curve in Jacobian coordinates P(X,Y,Z) and find
the point Q(X,Y,Z)=kxP. The system controller releases necessary control signals to produce the
desired output Q. The hardware architecture consists of modular point doubling and modular point
addition. Attack Experimental Setup Hardware In this proposal, we are considering the SAKURA-
X board, which has Xilinx Kintex-7 FPGA for side-channel power analysis. We have to acquire
N=100 traces for the randomly selected ECC points from set M and for each point Spt=10 traces
are to be captured. Hence, a total SN=14,000 traces are to be collected, where each trace has
10,000 sampling points. Software It is necessary to develop a code using programming languages
to analyze the collected power traces. An automated standalone application or C# applications
provided by the SAKURA can be used. The software to be developed has three major parts:
control unit, data unit and configuration unit. Attack Methodology In this proposed attack method,
it is planned to capture the power consumed in the FPGA (Kintex-7) during the double-and-add-
always algorithm. In this analysis, it is decided to attack the LSB three bits of the nibble. In order

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to achieve this, random 31 bytes fixed key is selected and the value of the last byte is changed in

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ascending order from 2^1 to (2^4) – 1. Analysis In the analysis process, machine learning
classification will be used. The process has two major steps, 1. Training data set preparation and 2.

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Classification using machine learning For the above process, it is decided to consider the signal
properties such as Mean of Absolute Value, Kurtosis, Median PSD, Frequency Ratio and Median

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Amplitude Spectrum. Also, SVM based classification in combination with PCA would be used for

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classification. Validation Process: It is important to validate the model against the existence of
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bias, after training with a machine-learning classification algorithm. For this, the k-fold cross-
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validation mechanism is applied for validation. In the k-fold cross-validation, a hold-out method is
to be used in which the model has to be trained k times, using k-1 subsets of the training data, and
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an error is estimated for the testing portion to analyze the performance of the model. The process
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is to be repeated k times to get better validation accuracy.

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ix) Innovation/Path-breaking aspects of the Proposed Research

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As discussed in the Research work review section the ECC is an effective asymmetric encryption
algorithm in terms of security with a small key size. To improve its security level against power
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analysis attacks, we are adopting double-and-add-always (DAA), modular arithmetic and

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Montgomery multiplication. Double-and-Add-Always algorithm The normal point multiplication

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is susceptible to side-channel attacks. In order to make it SCA resistant, additional countermeasure

has to be appended in it. The simple and efficient methodology is double-and-add-always [29]
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against power attacks. In a double-and-add method, the number of ones (hamming weight)
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determines the number of addition operations, while the number of bits that represent the scalar
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determines the number of doubling operations. Montgomery Multiplication The Montgomery

multiplication effectively computes Montgomery form of ab mod N. This algorithm effectively
avoids the expensive division algorithms, which reduces the hardware cost. It performs series of
additions and right shifting. The hardware architecture of Montgomery Modular multiplication has
AND gate operations, three adders, two comparators, one register with or without pre-computing
value. There is two intermediate results is computed by addition and left shift operation. Then, we
need a two-bit multiplexer to select with two comparators to get the correct result.
(x) Proposed Outcome such as papers in journals, edited book/(s), book, policy papers,
document etc. with proposed timeline and place of publications (300 words)
The outcome of the Project: 1. A set of Literature in the proposed area of research 2. Source
Codes of Design / Developed Algorithms 3. Interim and Final Technical Reports 4. Publications
(Journals/Conferences) 5. Patents Timeline: Literature Collection, JRF Recruitment and
Equipment purchase – 2 Months Design of Crypto Processor in FPGA – 6 Months Power
Analysis attack and trace capture – 4 Months DPA and Machine Learning based Classification –
4 Months Validation of the analysis – 4 Months Report Preparation – 4 Months The output of
the project work can be published in International/National Journals or Conferences. The novelty
obtained in the project can be converted to Patents.
(xi) Any new data to be generated where data deficiency is felt (100-150 words) :
Yes. A new set of data set has to be obtained during the experiment. This data set is named Power
traces, which is the power dissipation that occurs during the crypto computation running on the
target device. In this proposal, we are using an ECC algorithm running on the SAKURA-X FPGA

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board. While the ECC computation procedure running on the FPGA, it consumes power. The

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power dissipation and the type of operations/computations are directly related. This power
consumption data are the main source for the detection of secret key information. Hence, in this

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proposal to validate the robustness of the modular ECC algorithm, it is necessary to generate the
new power data traces.

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(xii) Relevance of the proposed study for policy making :

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The proposed study follows the following policies, • A detailed literature review or analysis is to
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be done. • Identifying the key area gaps in the existing methodologies. • Formulate the
methodology or algorithm to bridge the gap. • Design and implement the formulated methods. •
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Obtain the results and analyze them. • Finally evaluating the validation of the results obtained. The
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various side-channel attacking strategies, ECC algorithm modifications, Target programmable

device and result analyzing methodologies are reviewed from the international/national
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publications and patents. From these reviews, gaps present in the existing methods will be
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identified. In order to bridge the gap, necessary design procedures, algorithms, software and
hardware setup is to be formulated. After implementing these formulations, the resultant data are
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validated against the desired outcome.

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(xiii) Relevance of the proposed study for society (approx. 200 words) :
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Today’s world is wrapped in data communication through various devices and applications. Most
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importantly, Internet of Things (IoT) based data transfer/communication, mobile communications

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and online transactions, satellite communications and defence communications require secured
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data transfer irrespective of the intelligence of the attacker. Secured communication is ensured
with the support of a secured encryption/decryption algorithm without any compensation in the
performance factors. In this proposal, we are intended to implement the modular ECC algorithm
in the SAKURA-X FPGA board for the side-channel attack. The resilience of the ECC algorithm
against the side-channel attack would ensure the secured communication. Hence, this study could
be employed in internal and external communication of an enterprise, cyber security, defence
communication and online money transactions.
(xiv) Milestones set for each successive quarter of the study
Quarter Milestone
Collection of literature works, Appointment of JRF and Purchasing the
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necessary equipment for the project.
Designing the Crypto Processor in software (HDL) level with modulo
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operations for scalar addition and multiplication.
Converting the HDL code into a synthesizable netlist and implement the same
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in the SAKURA-X FPGA.
The power consumption details of the implemented algorithm are recorded in
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the form of Trace.
Applying the Differential power analysis statistical method to the collected

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power traces to identify the secret data.

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Introducing a machine learning algorithm (SVM) to improve the classification
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of secret information.

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Comparing the obtained results with the original secret information as a
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validation process.

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Documenting the finding of the project and submitting it to the peer-reviewed
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Journal and preparing the detailed Project report for ICSSR.
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(xv) Budget and Duration (please see Guidelines at 5.3 for proportionate Limit of a head)
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Duration Proposed
Total Grant expected under the scheme (In Rs.)
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(months)
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2025000 24
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(xvi) Proposed budget of the study under expenditure heads with justification
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Heads of Expenditure NumberMonthsRate Amount
[Link] Staff 1 24 25000 600000
1(a).Research Associate
1(b).Research Assistant
1(c).Field Investigator
[Link] work 24 850000
[Link] and study material 24 325000
[Link] 24 125000
Total 24 1900000

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[Link] of report - approx.5-7% (The allocation for

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publication amount will be retained by the ICSSR for
24 125000
publication of the final report if it is found to be high quality

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by the expert/experts appointed by the ICSSR)
Grand Total 24 2025000

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Justification of different heads of budget (write in 30 words each)
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[Link] Staff
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The PI and his team will be engaged, in addition to the project, with regular class works and other
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academic activities. Therefore, a Research Associate is required.

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[Link] work
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Xilinx® Kintex™-7 (XC7K160T) for cryptographic circuit and Spartan-6 (XC6SLX45) for the
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control circuit. The power traces from the SAKURA-X board has to be recorded using Tektronix
oscilloscope.
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[Link] and study material

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A dedicated higher-end workstation is required to design, implement and analyze the proposed
research. A scanner and printer for accessories purposes.
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Declaration
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• I am not a defaulter of any previous ICSSR grant.

• I have not availed ICSSR pay protection scheme
previously.
• I have neither been subjected to any disciplinary
action nor found guilty of any criminal offence in my
career.
I hereby declare that:
• The Research Proposal and its contents are entirely
original and as per the standard practice
• I have not concealed any information in my
fellowship application. If ICSSR finds any contrary
information at any stage, it may cancel my fellowship
out rightly and/or penalize me as per ICSSR rules.
Place : Sivakasi
Declaration Date : 31/08/2021

Signature :

Annexure/Checklists
( ) Forwarding letter from the Head of the affiliating Institution duly stamped and signed on the
letter head. .

( ) CV of all Researchers (PD and Co-PDs) with their signatures and consents in writing (Brief
CVs, not more than two to three pages each).

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Self-attested SC/ST certificate or certificate of disability issued by the competent authority, if

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required.

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