Department of Electronics and Communication Engineering
Computer Architecture (ECT-318) - Question Bank - 2 Marks
MODULE I
BASICS OF COMPUTER AND PROGRAMS
Q1. Define computer and list its basic functional units.
A1. A computer is an electronic device that processes data according to instructions. Basic
functional units are: Input Unit, Memory Unit, CPU (ALU + Control Unit), and Output Unit.
Q2. What is Von Neumann architecture? Draw its block diagram.
A2. Von Neumann architecture stores both data and instructions in the same memory. Block
diagram: Input → Memory ↔ CPU (ALU + Control Unit) → Output, connected by system buses.
Q3. Distinguish between primary and secondary memory.
A3. Primary memory: Directly accessible by CPU, volatile (RAM) or non-volatile (ROM), faster,
smaller capacity. Secondary memory: Not directly accessible, non-volatile, slower, larger capacity.
Q4. What are the main functions of ALU and Control Unit?
A4. ALU: Performs arithmetic (+, -, ×, ÷), logical (AND, OR, NOT), comparison, and shift
operations. Control Unit: Fetches, decodes instructions, controls execution sequence, manages
data flow.
Q5. Explain the fetch-decode-execute cycle.
A5. Fetch: Get instruction from memory using PC. Decode: Determine operation and operands
from instruction. Execute: Perform the operation using ALU. Store: Save results if needed.
Q6. What are registers? List any four types of registers.
A6. Registers are high-speed storage locations within CPU. Types: PC (Program Counter), IR
(Instruction Register), MAR (Memory Address Register), MDR (Memory Data Register).
Q7. Classify software and give examples of each type.
A7. System Software (OS, compilers, assemblers), Application Software (MS Word, games,
browsers), Programming Software (IDEs, debuggers, development tools).
Q8. What is the difference between compiler and interpreter?
A8. Compiler: Translates entire program at once, creates executable file, faster execution.
Interpreter: Translates line by line during execution, no executable file, slower execution.
Q9. Define machine language and assembly language.
A9. Machine language: Lowest level language using binary patterns (0s, 1s), directly executable
by CPU. Assembly language: Low-level language using mnemonics, requires assembler for
translation.
Q10. What are the components of a machine instruction?
A10. Machine instruction components: Opcode (operation code specifying the operation like
ADD, SUB) and Operand field(s) (data or addresses on which operation is performed).
Q11. Explain different types of instructions with examples.
A11. Data Transfer (LOAD, STORE), Arithmetic (ADD, SUB, MUL), Logical (AND, OR, NOT),
Control Transfer (JUMP, BRANCH, CALL), I/O instructions.
Q12. What is instruction format? List different instruction formats.
A12. Instruction format defines how instruction bits are organized. Types: Zero address, One
address, Two address, Three address formats based on number of operand fields.
Q13. Define stack and queue. Give their applications.
A13. Stack: LIFO (Last In First Out) data structure. Applications: Function calls, expression
evaluation. Queue: FIFO (First In First Out) data structure. Applications: Process scheduling,
buffer management.
Q14. What are subroutines? What are their advantages?
A14. Subroutines are independent program modules that perform specific tasks. Advantages: Code
reusability, modularity, easier debugging, reduced program size, better organization.
Q15. Explain CPU performance factors and performance equation.
A15. Performance factors: Clock speed, IPC (Instructions Per Clock), cache performance, memory
bandwidth. Performance equation: CPU Time = Instruction Count × CPI × Clock Period.
MODULE II
PROCESSOR ORGANIZATION AND ALU OPERATIONS
Q1. Draw and explain the basic processor organization.
A1. Processor contains: ALU (arithmetic/logic operations), Register file (temporary storage),
Control unit (instruction control), Cache (fast memory), Buses (data transfer paths). All connected
for instruction execution.
Q2. What is information representation? Explain different number systems.
A2. Information representation is how data is stored in computers. Number systems: Binary (base
2), Decimal (base 10), Octal (base 8), Hexadecimal (base 16). Computers use binary internally.
Q3. Convert (25)₁₀ to binary, octal, and hexadecimal.
A3. (25)₁₀ = (11001)₂ = (31)₈ = (19)₁₆ Method: Divide by base repeatedly and collect remainders.
Q4. Explain signed number representation methods.
A4. Sign-Magnitude: MSB for sign, remaining for magnitude. 1's Complement: Invert all bits for
negative. 2's Complement: 1's complement + 1, most commonly used.
Q5. What is BCD? Give example of BCD addition.
A5. BCD (Binary Coded Decimal): Each decimal digit represented by 4-bit binary. Example:
(29)₁₀ = (0010 1001)BCD. BCD addition requires correction when sum > 9.
Q6. Explain binary multiplication algorithm.
A6. Steps: 1) Initialize product = 0. 2) For each multiplier bit from right: if bit = 1, add multiplicand
to product. 3) Shift multiplicand left. 4) Continue for all bits.
Q7. What is Booth's algorithm? When is it used?
A7. Booth's algorithm is an efficient method for binary multiplication, especially for signed
numbers. It reduces the number of additions by examining pairs of bits and using add/subtract/shift
operations.
Q8. Explain binary division algorithm (restoring method).
A8. Steps: 1) Load dividend in AQ register. 2) Shift AQ left. 3) Subtract divisor from A. 4) If
result ≥ 0, set Q₀ = 1; else restore A, set Q₀ = 0. 5) Repeat n times.
Q9. What is non-restoring division algorithm?
A9. Non-restoring division doesn't restore remainder after unsuccessful subtraction. Instead, it
adds divisor in next step if previous operation was unsuccessful, making it faster than restoring
method.
Q10. Define floating point representation. What is IEEE 754 standard?
A10. Floating point represents real numbers as: Sign bit + Exponent + Mantissa. IEEE 754 is
international standard defining formats: Single precision (32-bit), Double precision (64-bit).
Q11. Explain IEEE 754 single precision format.
A11. 32-bit format: 1 sign bit, 8 exponent bits (biased by 127), 23 mantissa bits (normalized with
hidden 1). Range: ±1.18×10⁻³⁸ to ±3.4×10³⁸.
Q12. What are special values in IEEE 754 format?
A12. Special values: Zero (exp=0, mantissa=0), Infinity (exp=all 1s, mantissa=0), NaN-Not a
Number (exp=all 1s, mantissa≠0), Denormalized numbers (exp=0, mantissa≠0).
Q13. Perform floating point addition algorithm steps.
A13. Steps: 1) Compare exponents. 2) Shift mantissa of smaller number right. 3) Add/subtract
mantissas. 4) Normalize result. 5) Check for overflow/underflow. 6) Round result.
Q14. Design a 4-bit ALU and explain its operations.
A14. 4-bit ALU contains: 4 full adders for arithmetic, logic gates for logical operations, control
lines to select operation, status flags (carry, zero, overflow). Performs ADD, SUB, AND, OR,
XOR operations.
Q15. What are the design considerations for ALU?
A15. Considerations: Speed (propagation delay), Area (number of gates), Power consumption,
Flexibility (number of operations), Status flag generation, Overflow detection, Modular design for
expandability.
MODULE III
MICRO-PROGRAMMED AND CPU CONTROL
Q1. What is control unit? Explain its functions.
A1. Control unit coordinates CPU operations. Functions: Instruction fetch and decode, generate
control signals, sequence instruction execution, handle interrupts, control data paths between
components.
Q2. Distinguish between hardwired and microprogrammed control.
A2. Hardwired: Control logic implemented using gates and flip-flops, faster, less flexible, complex
design. Microprogrammed: Control signals generated by microprogram, slower, more flexible,
easier to modify.
Q3. What is instruction sequencing? Explain with example.
A3. Instruction sequencing is the order in which instructions are executed. Normally sequential
(PC+1), modified by branches/jumps. Example: LOAD R1, 100; ADD R2, R1; STORE R1, 200.
Q4. Explain the instruction interpretation process.
A4. Steps: 1) Fetch instruction from memory. 2) Decode opcode and operands. 3) Calculate
effective addresses. 4) Fetch operands. 5) Execute operation. 6) Store results. 7) Update PC.
Q5. What are the design methods for hardwired control?
A5. Methods: State table method (define states and transitions), Delay element method (use delays
for timing), Counter method (use counters for sequencing), PLA method (Programmable Logic
Array).
Q6. Draw and explain hardwired control unit design.
A6. Components: Instruction register, Instruction decoder, Control logic (gates), Timing circuits,
Control signal outputs. Decoder generates control signals based on opcode and timing.
Q7. What is microinstruction? What are its components?
A7. Microinstruction is a low-level instruction that generates control signals. Components: Control
field (specifies operations), Address field (next microinstruction), Condition field (for branching).
Q8. Explain basic concepts of microprogrammed control.
A8. Concepts: Control store (holds microprograms), Microprogram counter (addresses
microinstructions), Control logic generates signals from microinstructions, Easier to modify and
debug than hardwired.
Q9. What are the techniques for minimizing microinstruction size?
A9. Techniques: Field encoding (group related signals), Residual control (separate highly encoded
and less encoded fields), Vertical microcode (high encoding), Horizontal microcode (low
encoding).
Q10. Explain vertical and horizontal microcode.
A10. Vertical: Highly encoded, fewer bits, requires decoding, slower execution, compact control
store. Horizontal: Less encoded, more bits, direct control, faster execution, larger control store.
Q11. What is microprogram sequencing? Explain different methods.
A11. Microprogram sequencing determines next microinstruction address. Methods: Explicit
(address in microinstruction), Implicit (sequential), Mapping (from instruction opcode), Residual
control.
Q12. Design a multiplier control unit using microprogrammed approach.
A12. Components: Control store with multiply microprogram, microprogram counter, multiplier
datapath control, condition testing for zero multiplier, microinstructions for shift-add operations,
result storage control.
Q13. What are the advantages and disadvantages of microprogrammed control?
A13. Advantages: Flexibility, easier debugging, systematic design, regular structure.
Disadvantages: Slower than hardwired, requires control memory, additional level of interpretation
overhead.
Q14. Explain the concept of microprogram branching. A14. Microprogram branching changes
execution sequence based on conditions. Types: Unconditional (always branch), Conditional (test
flags), Multi-way (based on instruction type), Subroutine calls in microprograms.
Q15. What is nanoprogramming? Where is it used?
A15. Nanoprogramming is two-level microprogramming where microinstructions point to
nanoinstructions. Used when control store is expensive, provides better optimization, reduces
control store size significantly.
MODULE IV
MEMORY SYSTEMS
Q1. Explain memory hierarchy and its characteristics.
A1. Memory hierarchy organizes storage by speed and cost: Registers (fastest), Cache, Main
memory, Secondary storage (slowest). Characteristics: Speed decreases, capacity increases, cost
per bit decreases down the hierarchy.
Q2. What are the different types of RAM? Explain their characteristics.
A2. SRAM (Static RAM): Fast, expensive, low density, no refresh needed. DRAM (Dynamic
RAM): Slower, cheap, high density, requires refresh. SRAM used for cache, DRAM for main
memory.
Q3. Distinguish between SRAM and DRAM.
A3. SRAM: Uses flip-flops, faster access, no refresh, more expensive, lower density, used in
cache. DRAM: Uses capacitors, slower access, needs refresh, cheaper, higher density, used in main
memory.
Q4. What are different types of ROM? Explain each.
A4. ROM (Read Only): Programmed during manufacturing. PROM: Programmable once by user.
EPROM: Erasable with UV light. EEPROM: Electrically erasable. Flash: Block-erasable
EEPROM.
Q5. Explain memory organization with address decoding.
A5. Memory chips connected to address, data, and control buses. Address decoder selects specific
chip. Higher address bits for chip selection, lower bits for location within chip. Enable signals
control access.
Q6. What is memory interleaving? What are its advantages?
A6. Memory interleaving divides memory into independent modules accessed simultaneously.
Advantages: Increased memory bandwidth, reduced average access time, better processor
utilization, parallelism in memory access.
Q7. Define cache memory. What is the principle of locality?
A7. Cache is high-speed memory between CPU and main memory. Locality principle: Temporal
(recently used data likely to be used again), Spatial (nearby data likely to be used together).
Q8. Explain different cache mapping techniques.
A8. Direct mapping: Block maps to specific cache line. Associative: Block can go anywhere. Set-
associative: Block maps to specific set, anywhere within set. Trade-off between cost and
flexibility.
Q9. What is cache hit and cache miss? Define hit ratio.
A9. Cache hit: Required data found in cache. Cache miss: Data not in cache, must fetch from
memory. Hit ratio: Percentage of memory accesses found in cache (hits/total accesses).
Q10. Explain write-through and write-back cache policies.
A10. Write-through: Data written to both cache and memory simultaneously, slower writes,
consistent memory. Write-back: Data written only to cache initially, written to memory when
replaced, faster writes.
Q11. What is virtual memory? What are its advantages?
A11. Virtual memory allows programs larger than physical memory by using secondary storage.
Advantages: Large address space, memory protection, program relocation, multiprogramming
support.
Q12. Explain paging mechanism in virtual memory.
A12. Paging divides virtual memory into fixed-size pages and physical memory into frames. Page
table maps virtual pages to physical frames. OS handles page faults by loading pages from disk.
Q13. What is segmentation? How does it differ from paging?
A13. Segmentation divides program into logical segments (code, data, stack). Paging uses fixed-
size blocks, segmentation uses variable-size segments. Segmentation provides logical protection,
paging provides uniform address translation.
Q14. Explain Translation Lookaside Buffer (TLB).
A14. TLB is cache for page table entries, speeds up address translation. Contains recent virtual-
to-physical address mappings. On TLB hit, direct translation; on miss, access page table in
memory.
Q15. What are the different page replacement algorithms?
A15. FIFO (First In First Out), LRU (Least Recently Used), Optimal (replace page not used for
longest time), Second chance (FIFO with reference bit), Clock algorithm (circular buffer version).
MODULE V
INPUT/OUTPUT INTERFACING
Q1. Explain different methods of I/O data transfer.
A1. Programmed I/O: CPU directly controls I/O. Interrupt-driven I/O: Device interrupts CPU
when ready. DMA: Direct memory access without CPU intervention. Each method trades CPU
involvement for complexity.
Q2. What is programmed I/O? What are its advantages and disadvantages?
A2. CPU directly controls I/O operations by checking device status and transferring data.
Advantages: Simple implementation, full CPU control. Disadvantages: CPU time wasted in
polling, inefficient for slow devices.
Q3. Explain interrupt-driven I/O mechanism.
A3. Device generates interrupt when ready for I/O. CPU saves context, executes interrupt service
routine, transfers data, restores context. More efficient than programmed I/O as CPU can do other
work.
Q4. What is interrupt? Explain interrupt processing steps.
A4. Interrupt is signal from device to CPU requesting attention. Steps: 1) Save current state. 2)
Identify interrupt source. 3) Jump to interrupt service routine. 4) Execute service routine. 5)
Restore state. 6) Resume execution.
Q5. Distinguish between maskable and non-maskable interrupts.
A5. Maskable interrupts: Can be disabled by CPU (keyboard, disk). Non-maskable interrupts:
Cannot be disabled, used for critical events (power failure, memory errors). NMI has higher
priority.
Q6. What is interrupt priority? Explain priority interrupt system.
A6. Interrupt priority determines which interrupt is serviced first when multiple interrupts occur.
Priority methods: Polling, daisy chain, parallel priority interrupt. Higher priority interrupts can
interrupt lower priority ones.
Q7. Explain DMA (Direct Memory Access) and its advantages.
A7. DMA allows devices to transfer data directly to/from memory without CPU intervention.
Advantages: Frees CPU for other tasks, faster data transfer, efficient for block transfers, reduces
interrupt overhead.
Q8. What are the different DMA transfer modes?
A8. Burst mode: DMA controller takes complete control until transfer complete. Cycle stealing:
DMA controller transfers one word per bus cycle. Transparent mode: DMA operates only when
CPU doesn't need bus.
Q9. Draw and explain DMA controller block diagram.
A9. Components: Address register (memory address), Word count register (transfer size), Control
register (operation type), Status register (flags), Bus interface logic, Handshaking logic with
devices.
Q10. What are standard I/O interfaces? Give examples.
A10. Standard interfaces ensure compatibility between devices and systems. Examples: USB
(Universal Serial Bus), PCI (Peripheral Component Interconnect), SATA (Serial ATA), Ethernet
for networking.
Q11. Explain USB interface and its features.
A11. USB (Universal Serial Bus): Serial interface for connecting peripherals. Features: Hot-
pluggable, up to 127 devices, different speeds (Low, Full, High, Super), master-slave protocol,
bus-powered devices.
Q12. What is parallel processing? List its forms.
A12. Parallel processing executes multiple operations simultaneously. Forms: Bit-level (wider
data paths), Instruction-level (pipelining), Data-level (vector processing), Task-level (multiple
processors).
Q13. Explain pipelining concept with example.
A13. Pipelining overlaps execution of multiple instructions. Example: 4-stage pipeline (Fetch,
Decode, Execute, Write-back). While one instruction executes, next fetches, improving throughput
without reducing individual instruction time.
Q14. What are the different types of pipeline hazards?
A14. Structural hazards: Resource conflicts. Data hazards: Dependencies between instructions
(RAW, WAR, WAW). Control hazards: Branches and jumps disrupt pipeline flow. Solutions
include forwarding, stalling, prediction.
Q15. Explain different interconnection networks for parallel processing.
A15. Bus networks: Shared bus (simple, limited bandwidth). Crossbar: Full connectivity,
expensive. Mesh: Regular 2D grid. Hypercube: n-dimensional cube. Tree: Hierarchical structure.
Each has different cost-performance characteristics.