Department of Electronics and Communication Engineering

Digital System Design using Verilog (BEC302)

B.E - III Semester
2022 scheme - Lab Manual
2024-25

Prepared by Approved by
Prof. Khamer Unnisa H Dr. Ravishankar C V
Professor & HOD
Assistant Professor
Dept. Of ECE., SaIT.
Dept. Of ECE., SaIT.

Name :

USN :

Batch : Section :
 Department of Electronics and Communication Engineering

VISION AND MISSION OF THE INSTITUTE

VISION
The future is embodied in the present generation. Professional education combined
with practical exposure to create values in the students who are the future of our
nation.
MISSION
Work oriented education combined with ethical values, character building in context
of today`s millennium.

QUALITY POLICY
The Sambhram Institute of Technology is committed to create quality professionals
to meet the emerging industrial and social needs through innovative teaching
applied research, Industrial Interaction, placing faith in human values and aiming at
continual improvement in all activities. We strive to provide the quality education
that meets the need and aspirations of the students, employers and society. The
institute aims to respond to all of these groups by providing curriculum and support
which is necessary to enable the progression and to allow individuals to grow,
develop and become universally accepted technocrat.
 Department of Electronics and Communication Engineering

DEPARTMENT VISION

“To harness emerging technology by rendering innovative and excellent technical

knowledge for the benefit of mankind.”

DEPARTMENT MISSION

“To imbibe a blend of practical and theoretical ideas in the students to make them
knowledgeable, industrious, entrepreneurial and professional, so that they
contribute not only to the country but also to the world and to humanity in general.”
 Department of Electronics and Communication Engineering

Program Educational Objectives (PEOs)

After successful completion of the program, the graduates will be

ECPEO 1: Able to apply concepts of mathematics, science and computing to Electronics and
Communication Engineering.

ECPEO 2: Able to design and develop interdisciplinary and innovative systems.

ECPEO 3: Able to inculcate effective communication skills, team work, ethics, leadership in
preparation for a successful career in industry and R&D organizations.

Program Specific Outcomes (PSOs)

At the end of the program, the student

PSO1. Should be able to clearly understand the concepts and applications in the field of
Communication / networking, signal processing, embedded systems and semiconductor
technology.

PSO2. Should be able to associate the learning from the courses related to Microelectronics,
Signal processing, Microcomputers, Embedded and Communication Systems to arrive at
solutions to real world problems.

PSO3. Should have the capability to comprehend the technological advancements in the usage of
modern design tools to analyze and design subsystems/processes for a variety of
applications.

PSO4. Should possess the skills to communicate in both oral and written forms, the work already
done and the future plans with necessary road maps, demonstrating the practice of
professional ethics and the concerns for societal and environmental wellbeing.
 Department of Electronics and Communication Engineering

Course objectives:

This laboratory course enables students to,

 To impart the concepts of simplifying Boolean expression using K-map techniques and Quine-

McCluskey minimization techniques.

 To impart the concepts of designing and analyzing combinational logic circuits.

 To impart design methods and analysis of sequential logic circuits.
 To impart the concepts of Verilog HDL-data flow and behavioural models for the design of digital
system

Course outcomes:

At the end of the course the student will be able to:

1. Simplify Boolean functions using K-map and Quine-McCluskey minimization technique.

2. Analyze and design for combinational logic circuits.

3. Analyze the concepts of Flip Flops (SR, D,T and JK) and to design the synchronous sequential
circuits using Flip Flops.

4. Model Combinational circuits (adders, subtractors, multiplexers) and sequential circuits using
Verilog descriptions.
 Department of Electronics and Communication Engineering
Program outcomes (POs):
Engineering Graduates will be able to:
PO1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
PO2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
PO3. Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for
the public health and safety, and the cultural, societal, and environmental considerations.
PO4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
PO6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
PO7. Environment and sustainability: Understand the impact of the professional engineering solutions
in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
PO8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
PO9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
PO10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
PO11. Project management and finance: Demonstrate knowledge and understanding of the engineering
and management principles and apply these to one’s own work, as a member and leader in a team,
to manage projects and in multidisciplinary environments.
PO12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
 Department of Electronics and Communication Engineering
SYLLABUS
Digital System Design using Verilog Lab
Subject Code : BEC302 CIE : 25
Teaching Hrs/Week.: [Link] SEE : 25
Credits : 04 Exam Hours : 02

List of Experiments:
[Link] Experiments
1 To simplify the given Boolean expression and realize using Verilog program
2 To realize Adder/Subtractor (Full/half) circuits using Verilog data flow description.
3
To realize 4-bit ALU using Verilog program
4
To realize the following Code conversion using Verilog Behavioral description (a) Gray
to Binary and vice versa (b) Binary to Excess3 and vice versa
5
To realize using Verilog Behavioral description 8:1 mux, 8:3 encoder, priority encoder.

6
To realize using Verilog Behavioral description 1:8 demux, 3:8 decoder, 2-bit
comparator.
7 To realize using Verilog Behavioral description flipflops : a) JK type b) SR type c) T
type and d) D type.
8 To realize Counters -up/down using Verilog behavioral description
Demonstration Experiments (For CIE only- not to be included for SEE)
9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor in
the specified direction (by N steps)
10 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate
its working
 Department of Electronics and Communication Engineering

Suggested Learning Resources:

1. Digital Logic Applications and Design by John MYarbrough,Thomson Learning,2001.

2. Digital Principles and Design by Donald D Givone,McGrawHill, 2002.

3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dream techpress

COURSE ASSESSMENT AND EVALUATION

Direct Assessment Methods
When/where
Contribution
To (Frequency Max. Evidence
What to course
Whom in the Marks collected
outcomes
course)

Observation
Every Lab book written
Session at each lab +
Record and
(Avg. of all Record CO1 – CO4
CIE Observation Students
experiment submitted at
marks) each lab +
Viva

IA Test Two 20 Bluebooks CO1 – CO4

 Department of Electronics and Communication Engineering

CO-PO and PSO Mapping

PO PSO
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4

CO1 2 - - 3 - - - - - - - - 2 2 - -
CO2 3 - - 3 - - - - - - - - 2 2 - -
CO3 3 - - - - - - - - - - - 2 2 - -
CO4 - - - - 3 - - - - - - - 2 2 - -
SUM 8 - - 6 3 - - - - - - - 8 8 - -
AVG 2 - - 3 3 - - - - - - - 2 2 - -

3- Highly mapped 2- Moderately mapped 1- Slightly mapped

 Department of Electronics and Communication Engineering

INSTRUCTIONS TO THE CANDIDATES

 Student should come with thorough preparation for the experiment to be conducted.
 Student should take prior permission from the concerned faculty before availing the leave.
 Student should come with proper dress code and to be present on time in the laboratory.
 Student will not be permitted to attend the laboratory unless they bring the practical record
fully completed in all respects pertaining to the experiment conducted in the previous
class.
 Student will not be permitted to attend the laboratory unless they bring the observation
book fully completed in all respects pertaining to the experiment to be conducted in
present class.
 Experiment should be started conducting only after the staff-in-charge has checked the
circuit diagram.  All the calculations should be made in the observation book. Specimen
calculations for one set of readings have to be shown in the practical record.
 Wherever graphs to be drawn, A-4 size graphs only should be used and the same should
be firmly attached in the practical record.
 Practical record and observation book should be neatly maintained.
 Student should obtain the signature of the staff-in-charge in the observation book after
completing each experiment.

 Theory related to each experiment should be written in the practical record before
procedure in your own words with appropriate references.
 Department of Electronics and Communication Engineering

CONTENTS
Sl. [Link] of the Experiment Page No.
1 1
To simplify the given Boolean expression and realize using Verilog
program

2 To realize Adder/Subtractor (Full/half) circuits using Verilog data flow 2-4

description.
3 5-6
To realize 4-bit ALU using Verilog program

4 7-8
To realize the following Code conversion using Verilog Behavioral
description (a) Gray to Binary and vice versa (b) Binary to
Excess3 and vice versa
5 To realize using Verilog Behavioral description 8:1 mux, 8:3 encoder, 9-11

priority encoder.

6 To realize using Verilog Behavioral description 1:8 demux, 3:8 decoder, 2-bit 12-14
comparator.
7 To realize using Verilog Behavioral description flipflops : a) JK type b) SR 15-17
type c) T type and d) D type
8 To realize Counters -up/down using Verilog behavioral description 18-19
Demonstration Experiments (For CIE only- not to be
included for SEE)
9 Verilog Program to interface a Stepper motor to the
FPGA/CPLD and rotate the motor in the specified direction (by
N steps)
10 Verilog programs to interface Switches and LEDs to the
FPGA/CPLD and demonstrate its working
 Digital System design using verilog (BEC302) 2024-25

Experiment No.1
Simplify the given Boolean expression and realize using Verilog program.
Aim: To simplify the given Boolean expression and realize using Verilog program.

Apparatus Required: Xilinx tool

Theory:
 A Boolean expression is a logical statement that evaluates to either true or false. Boolean expressions
are used in programming languages, and are a special case of Boolean circuits.
 Boolean expressions can compare data of any type, as long as both parts of the expression have the
same basic data type.
 Boolean expressions can be used to test if data is equal to, greater than, or less than other data.
Boolean expressions can be used to combine and manipulate search terms.
 Verilog is a hardware description language (HDL) used to design and verify digital circuits.
It's a textual language that allows engineers to model the behavior of digital systems.
Verilog uses modules, which represent hardware entities, as building blocks for larger circuits.
 Verilog supports various data types, including integers, registers, nets, and time. Verilog uses a hardware-
centric approach to model complex digital systems.

Program:

F(A,B,C,D)=( A+ B) +C

module BOO_EXP(A,B,C,F);
input A,B,C;
output F;
assign F= (~(A+B))|(~C);
endmodule

Output waveform:

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 Digital System design using verilog (BEC302) 2024-25

Experiment No.2
Implementing Adder/Subtractor using Verilog Dataflow description.
Aim: To realize adder/subtractor (Full and Half) circuits using Verilog dataflow description

Apparatus Required: Xilinx tool

Theory:
 A half adder and a full adder are both combinational logic circuits that add binary numbers. A half adder
adds two binary digits, while a full adder adds three binary digits.
 Half Adder is a combinational logic circuit that is designed by connecting one EX-OR gate and one
AND gate. The half-adder circuit has two inputs: A and B, which add two input digits and generate a
carry and a sum.
 Full Adder is the circuit that consists of two EX-OR gates, two AND gates, and one OR gate. Full
Adder is the adder that adds three inputs and produces two outputs which consist of two EX-OR gates,
two AND gates, and one OR gate. The first two inputs are A and B and the third input is an input carry
as C-IN. The output will be sum and carry.
 A half subtractor and a full subtractor are digital circuits that perform subtraction of binary numbers.
A half subtractor subtracts two bits, while a full subtractor subtracts three bit

Block diagram:

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 Digital System design using verilog (BEC302) 2024-25

Program:

a) Half Adder

module half_adder (a,b,sum,carry);

input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule

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 Digital System design using verilog (BEC302) 2024-25

Output waveform:

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 Digital System design using verilog (BEC302) 2024-25

Half subtractor

module half_subtractor (a,b,diff,borrow);

input a,b;
output diff,borrow;
assign diff=a^b;
assign borrow=(~a)&b;
endmodule

Output waveform:

b) Full Adder
module full_adder (a,b,c,sum,carry);
input a,b,c;
output sum, carry;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

Output waveform:

c) Full Subtractor
module full_subtractor (a,b,c,diff,borrow);
input a,b,c;
output diff, borrow;
assign diff=a^b^c;

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 Digital System design using verilog (BEC302) 2024-25

assign borrow=((~a)&b)|(b&c)|(c&(~a));
endmodule

Output waveform:

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 Digital System design using verilog (BEC302) 2024-25

Experiment No.3
Realize 4-bit ALU using Verilog program.
Aim: To realize 4 bit ALU using Verilog program.

Apparatus Required: Xilinx tool

Theory:
 ALU stands for Arithmetic Logic Unit. It is a digital circuit that performs arithmetic and logic
operations on binary numbers. ALUs are a fundamental component of a computer's central
processing unit (CPU).
 In some processors, the ALU is divided into two units: an arithmetic unit (AU) and a
logic unit (LU). Some processors contain more than one AU -- for example, one for
fixed-point operations and another for floating-point operations.

Block diagram:

Program:

module pro4(a,b,opcode,enable,result);
input [3:0]a;
input [3:0]b;
input enable;
input [2:0]opcode;
output reg[3:0]result;
always @ (opcode,enable,a,b)

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 Digital System design using verilog (BEC302) 2024-25
begin
if(!enable)
result=4'bz;
else
case (opcode)
3'b000:result=a+b;
3'b001:result=a-b;
3'b010:result=a+1;
3'b011:result=a-1;
3'b100:result=a;
3'b101:result=~a;
3'b110:result=a|b;
3'b111:result=a&b;
default:result=3'b000;
endcase
end
endmodule

Output waveform:

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 Digital System design using verilog (BEC302) 2024-25

Experiment No.4
Realize the Code Converters by using Verilog Behavioral Description.
Aim: To realize the code converters by using Verilog Behavioral Description

a) Gray to Binary and vice versa b) Binary to excess-3 and vice versa

Apparatus Required: Xilinx tool

Theory:
 A code converter in digital electronics is a circuit that changes the type of input encoding
to a different type of output encoding. Code converters are often used to convert between
different types of binary codes.
 Gray code has a property that two successive numbers differ in only one bit because of this
property gray code does the cycling through various states with minimal effort and is used
in K-maps, error correction, communication, etc .
 Binary Number is the default way to store numbers, but in many applications, binary numbers
are difficult to use and a variety of binary numbers is needed. This is where Gray codes are very
useful.
 Verilog supports various data types, including integers, registers, nets, and time. Verilog uses a
hardware-centric approach to model complex digital systems.
 Excess-3 code (XS3) is a non-weighted binary coded decimal (BCD) code that represents
decimal numbers. It's a self-complementary, sequential, and reflective code.

Block diagram:

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 Digital System design using verilog (BEC302) 2024-25

Program:

I) Binary to Gray Code Converter

module bin_gry(b,g);
input[3:0]b;
output reg [3:0]g;
always @(b)
begin
g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule

2) Gray to binary code converter

module bin_gry(b,g);
input[3:0]g;
output reg [3:0]b;
always @(g)
begin
b[3]=g[3];
b[2]=g[3]^g[2];
b[1]=g[2]^g[1];
b[0]=g[1]^g[0];
end
endmodule

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 Digital System design using verilog (BEC302) 2024-25

Output waveform:

II) Binary to Excess 3 code converter

module gtb(b,g);
input[3:0]g;
output reg [3:0]b;
always @(g)
begin
b[3]=g[3];
b[2]=g[3]^g[2];
b[1]=g[3]^g[2]^g[1];
b[0]=g[3]^g[2]^g[1]^g[0];
end
endmodule

II) Excess 3 to binary code converter

module gtb(b,g);
input[3:0]g;
output reg [3:0]b;
always @(g)
begin
b[3]=g[3];
b[2]=g[3]^g[2];
b[1]=g[3]^g[2]^g[1];
b[0]=g[3]^g[2]^g[1]^g[0];
end
endmodule

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 Digital System design using verilog (BEC302) 2024-25

Experiment No.5
Realize Combinational circuits using Verilog Behavioral description.
Aim: To realize using Verilog behavioral description : 8:1 mux, 8:3 encoder, Priority Encoder.

Apparatus Required: Xilinx tool

Theory:
 A multiplexer is a combinational circuit that has many data inputs and a single output, depending on
control or select inputs. For N input lines, log2(N) selection lines are required, or equivalently, for
2n2n input lines, n selection lines are needed.
 Multiplexers are also known as “N-to-1 selectors,” parallel-to-serial converters, many-to-one circuits,
and universal logic circuits. They are mainly used to increase the amount of data that can be
sent over a network within a certain amount of time and bandwidth .
 An encoder is a device that converts motion into an electrical signal. It can also convert information
from one format to another. Encoders are used in many industries to provide information about position,
speed, direction, and count.
 A "priority encoder" is a type of encoder in digital logic that, when multiple input signals are active
at the same time, outputs the binary code corresponding to the input with the highest priority,
essentially giving precedence to the most important signal among all active inputs; it prioritizes the
highest numbered input that is active, unlike a regular encoder which might output an undefined
result in such scenarios.

Block diagram:

Program:

A) 8:1 Multiplexer
module mux81(
input [7:0]i,
input [2:0]s,
output reg y );
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 Digital System design using verilog (BEC302) 2024-25
always @ (i,s)
begin
if (s==3'b000)y=i[0];
else if (s==3'b001)y=i[1];
else if (s==3'b010)y=i[2];
else if (s==3'b011)y=i[3];
else if (s==3'b100)y=i[4];
else if (s==3'b101)y=i[5];
else if (s==3'b110)y=i[6];
else y=i[7];
end
endmodule

Output waveform:

b) 8:3 Encoder
module encoder83(
input [7:0] d,
output reg[2:0] q );
always @ (d)
begin
case(d)
8'b10000000:q=3'b111;
8'b01000000:q=3'b110;
8'b00100000:q=3'b101;
8'b00010000:q=3'b100;
8'b00001000:q=3'b011;
8'b00000100:q=3'b010;
8'b00000010:q=3'b001;
8'b00000001:q=3'b000;
default:q=3'b000;
endcase
end
endmodule

OUTPUT WAVEFORM

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 Digital System design using verilog (BEC302) 2024-25

c) 8:3 Priority Encoder

module priority83(
input [7:0] d,
output reg[2:0] q );
always @ (d)
begin
casex(d)
8'b1xxxxxxx:q=3'b111;
8'b01xxxxxx:q=3'b110;
8'b001xxxxx:q=3'b101;
8'b0001xxxx:q=3'b100;
8'b00001xxx:q=3'b011;
8'b000001xx:q=3'b010;
8'b0000001x:q=3'b001;
8'b00000001:q=3'b000;
default:q=3'bxxx;
endcase
end
endmodule

OUTPUT WAVEFORM

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 Digital System design using verilog (BEC302) 2024-25

EXPERIMENT NO 6

REALIZE DEMUX, DECODER AND 2 BIT COMPARATOR USING VERILOG BEHAVIOURAL

DESCRIPTION.

Aim: To realize demux, decoder and 2 bit comparator using Verilog behavioral description

Apparatus Required: Xilinx tool

Theory:
 A demultiplexer (demux) is a device that takes a single input signal and directs it to one of
multiple output lines. It's the opposite of a multiplexer (mux), which combines multiple input
signals into one output
 Select inputs specify which output line the input is connected to. The number of select lines determines how
many outputs the demux can manage. outputs.
 A binary decoder is a digital circuit that converts a binary code into a set of outputs.
 The binary code represents the position of the desired output and is used to select the specific output that is
active.
 Binary decoders are the inverse of encoders and are commonly used in digital systems to convert a serial
code into a parallel set of outputs.
 A comparator used to compare two binary numbers each of two bits is called a 2-bit magnitude comparator.

A) 1:8 Demultiplexer
module demux18(
input i,
input [2:0]s,
output reg [7:0]y );
always @ (i,s)
begin
y=0;
if (s==3'b000)y[0]=i;
else if (s==3'b001)y[1]=i;
else if (s==3'b010)y[2]=i;
else if (s==3'b011)y[3]=i;
else if (s==3'b100)y[4]=i;
else if (s==3'b101)y[5]=i;
else if (s==3'b110)y[6]=i;
else y[7]=i;
end
endmodule

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 Digital System design using verilog (BEC302) 2024-25

OUTPUT WAVEFORM

A) 3:8 Decoder
module decoder38(
input [2:0]i,
input en,
output reg [7:0]y);
always @(i or en)
begin
if (en)
begin
y=8'd0;
case (i)
3'b000:y[0]=1'b1;
3'b001:y[1]=1'b1;
3'b010:y[2]=1'b1;
3'b011:y[3]=1'b1;
3'b100:y[4]=1'b1;
3'b101:y[5]=1'b1;
3'b110:y[6]=1'b1;
3'b111:y[7]=1'b1;
default:y=8'd0;
endcase
end
else
y=8'd0;
end
endmodule

OUTPUT WAVEFORM

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A) 2-Bit Comparator
module cmp(
input [1:0]a,b,
output reg equal, greater, lower);
always@ (a or b)
begin
if (a<b)
begin
greater=0;
equal=0;
lower=1;
end
else if (a==b)
begin

greater=0;
equal=1;
lower=0;
end
else
begin
greater=1;
equal=0;
lower=0;
end
end
endmodule

OUTPUT WAVEFORM

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EXPERIMENT NO 7

REALIZE FLIP FLOPS USING VERILOG BEHAVIOURAL DESCRIPTION.

Aim: To realize flipflops using Verilog behavioral description

Apparatus Required: Xilinx tool

Theory:
 The flip-flop is a circuit that maintains a state until directed by input to change the state. A basic flip-flop
can be constructed using four-NAND or four-NOR gates. Flip-flop is popularly known as the basic
digital memory circuit. It has its two states as logic 1(High) and logic 0(low) states. A flip flop is a
sequential circuit which consist of single binary state of information or data. The digital circuit is a
flip flop which has two outputs and are of opposite states. It is also known as a Bistable Multivibrator.
 In the flip flop, with the help of preset and clear when the power is switched ON, the states of the circuit
keeps on changing, that is it is uncertain. It may come to set(Q=1) or reset(Q’=0) state.
 Its name comes from its ability to “flip” or “flop” between two stable states. By latching a value and changing
it when triggered by a clock signal, flip-flops can store data over time. They are called flip-flops because
they have two stable states and switch between them based on a triggering event.

A) JK FLIP FLOPS
module jkff(
input j,k,clk,
output q,qbar);
reg q=0,qbar=1;
always @ (posedge clk)
begin

case ({j,k})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
default:q=~q;
endcase
qbar=~q;
end
endmodule

OUTPUT WAVEFORM

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A) SR FLIP FLOP
module srff(
input s,r,clk,
output reg q=0,qbar=1);
always @ (posedge clk)
begin
case ({s,r})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
default:q=1'bx;
endcase
qbar=~q;
end
endmodule

OUTPUT WAVEFORM

B) D FLIP FLOP
module Dff(
input d,clk,
output reg q,qbar);
always @ (posedge clk)
begin
q=d;
qbar=~q;
end
endmodule

OUTPUT WAVEFORM

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 Digital System design using verilog (BEC302) 2024-25

C) T FLIP FLOP
module tff(
input t, clk,
output reg q=0,
output reg qbar
);
always @ (posedge clk)
begin
case(t)
1'b0:q=q;
1'b1:q=~q;
endcase
qbar=~q;
end
endmodule

OUTPUT WAVEFORM

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 Digital System design using verilog (BEC302) 2024-25

EXPERIMENT NO 8

TO REALIZE COUNTER-UP/DOWN (BCD AND BINARY) USING VERILOG BEHAVIOURAL

DESCRIPTION.

Aim: To realize counter (up-down and binary) using verilog behavioral description language

Apparatus Required: Xilinx tool

Theory:
 Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter.
Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied.
Counters are of two types.
 Asynchronous or Ripple Counters and Synchronous Counters
 Asynchronous counters are a kind of digital circuitry which may count either upwards or downwards
while not adhering to the timing pulses from an oscillator. As a result, state transitions are determined
by extra inputs rather than by time frames at fixed intervals. The flip-flops and logic gates are
utilized for designing the asynchronous counter in order to get counting sequence control based on input
signals. With such characteristics they offer flexibility in counting and can be applied in many situations
that demands am asynchronous action.

i) Binary Counter (UP Counter)

module bcd(q,clk,reset);
input reset,clk;
output reg [3:0]q;
always @(posedge clk)
begin
if(reset==1)
q<=4'b0000;
else
q<=q+1;
end
endmodule

OUTPUT WAVEFORM

i) Binary Counter (Down counter)

module bcd(q,clk,reset);
input reset,clk;
output reg [3:0]q;
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 Digital System design using verilog (BEC302) 2024-25
always @(posedge clk)
begin
if(reset==1)
q<=4'b1111;
else
q<=q-1;
end
endmodule

OUTPUT WAVEFORM

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 Digital System design using verilog (BEC302) 2024-25

fc=50kHz.

Ic=1mA, Ic=Ie.

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 Digital Communication Lab (BECL504) 2024-25

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 Digital Communication Lab (BECL504) 2024-25

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