Chapter 2

Machine Instructions
and Programs

1
Objectives
⚫ Machine instructions and program execution,
including branching and subroutine call and return
operations.
⚫ Number representation and addition/subtraction in
the 2’s-complement system.
⚫ Addressing methods for accessing register and
memory operands.

2
Number, Arithmetic
Operations, and
Characters

3
Signed Integer Representations
⚫ 3 major representations:
Sign and magnitude
One’s complement
Two’s complement

4
 Binary, Signed-Integer
Representations
B Values represented
Page 28
Sign and
b3 b2b1b0 magnitude 1's complement 2's complement

0 1 1 1 + 7 +7 + 7
0 1 1 0 + 6 +6 + 6
0 1 0 1 + 5 +5 + 5
0 1 0 0 + 4 +4 + 4
0 0 1 1 + 3 +3 + 3
0 0 1 0 + 2 +2 + 2
0 0 0 1 + 1 + 1 + 1
0 0 0 0 + 0 +0 + 0
1 0 0 0 - 0 -7 - 8
1 0 0 1 - 1 -6 - 7
1 0 1 0 - 2 -5 - 6
1 0 1 1 - 3 -4 - 5
1 1 0 0 - 4 -3 - 4
1 1 0 1 - 5 -2 - 3
1 1 1 0 - 6 - 1 - 2
1 1 1 1 - 7 -0 - 1

Figure 2.1. Binary, signed-integer representations. 5

 Sign and Magnitude
Representation
-7 +0
-6 1111 0000 +1
1110 0001
-5 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4

-3 1011 0100 +4 1 100 = - 4

1010 0101
-2 +5 -
1001 0110
-1 1000 0111 +6
-0 +7
• High order bit is sign: 0 = positive (or zero), 1 = negative
• Three low order bits is the magnitude: 0 (000) through 7 (111)
• Number range for n bits = +/- (2n-1 - 1)
• Problems: Two representations for 0 (0000 is +0, 1000 is –0) (see
the number wheel)
• Some Complexities in Addition, Subtraction
6
 One’s Complement
Representation
-0 +0
-1 1111 0000 +1
1110 0001
-2 +2 +
1101 0010
-3 1100 0011 +3 0 100 = + 4

-4 1011 0100 +4 1 011 = - 4

1010 0101
-5 +5 -
1001 0110
-6 1000 0111 +6
-7 +7

⚫ - x = 1’s complement of x
⚫ 1’s complement is invert 0 to 1 and 1 to 0
⚫ Two representations for 0 (0000 is +0, 1111 is -0). causes some
problems. Some complexities in addition, subtraction
⚫ Subtraction (X-Y) implemented by addition & 1's complement (x – y = X +
1’s complement of Y = X + Y' )
7
 Two’s Complement
Representation
-1 +0
-2 1111 0000 +1
1110 0001
-3 +2 +
like 1's comp 1101 0010

except -4 1100 0011 +3 0 100 = + 4

negative numbers -5 1011 0100 +4 1 100 = - 4

shifted 1010 0101
one position -6 +5 -
1001 0110
clockwise -7 1000 0111 +6
-8 +7

⚫ - x = 2’s complement of x
⚫ Range : -2n-1 to (2n-1 - 1)
⚫ 2’s complement is just 1’s complement + 1
⚫ Only one representation for 0 ( 0000 => 1111+1 => 10000 => 0000 in 4 bits,
ignore the carry out / MSB 1)
⚫ Addition, Subtraction Very Simple

8
 2’s-Complement Add and
Subtract Operations
(a) 0010 ( + 2) (b) 0100 ( + 4)
+ 0011 ( + 3) + 1010 (- 6 )
Page 31 (- 2 )
0101 ( + 5) 1110
(c) 1011 (- 5) (d) 0111 ( + 7)
+ 1110 (- 2) + 1101 ( - 3)
1001 (- 7) 0100 ( + 4)
(e) 1101 (- 3) 1101
- 1001 (- 7) + 0111
0100 ( + 4)
(f) 0010 ( + 2) 0010
- 0100 ( + 4) + 1100
1110 ( - 2)
(g) 0110 ( + 6) 0110
- 0011 ( + 3) + 1101
0011 ( + 3)
(h) 1001 ( - 7) 1001
- 1011 (- 5) + 0101
1110 ( - 2)
(i) 1001 (- 7) 1001
- 0001 ( + 1) + 1111
1000 ( - 8)
(j) 0010 ( + 2) 0010
- 1101 ( - 3) + 0011
0101 ( + 5)

Figure 2.4. 2's-complement Add and Subtract operations.

9
Overflow- When the result of an arithmetic operation is outside the
representable range, an arithmetic overflow occurs. It also occurs if two
positive numbers are added to get a negative number or two negative
numbers are added to get a positive number.

-1 +0 -1 +0
-2 1111 0000 +1 -2 1111 0000 +1
1110 0001 1110 0001
-3 +2 -3
1101 1101 +2
0010 0010
-4 -4
1100 0011 +3 1100 0011 +3
-5 1011 -5 1011
0100 +4 0100 +4
1010 1010
-6 0101 -6 0101
1001
+5 +5
0110 1001 0110
-7 1000 0111 +6 -7 1000 +6
0111
-8 +7 -8 +7

5 + 3 = -8 -7 - 2 = +7
0101 + 0011 = 1000 1001 + 1100 = 10111 => 0111
x
10
 Overflow Condition – Carry in
to MSB ≠ Carry out from MSB
0 1 1 1←carry-in 1000
5 0101 -7 1001
Overflow Overflow
3 0011 -2 1100
-8 1000 7 10111

0000 1111
No 5 0101 1101
overflow -3
No overflow
2 0010 -5 1011
7 0111 -8 11000

Ways to detect Overflow:

(1) when carry-in to the MSB (most significant bit) does not equal carry out from MSB
(2) Add two positive numbers to get a negative number or, Add two negative numbers to
get a positive number
(3) Result is out of range
11
Memory Locations,
Addresses, and
Operations

12
 Memory Location, Addresses,
and Operation n bits
first word
⚫ Memory consists of many second word
millions of storage cells,
each of which stores 1 bit. •
•
⚫ Data is usually accessed •
in n-bit groups, called a
“word”. i th word

⚫ n is called word length. •

⚫ Typically n=32 or 64 bits •
•
etc. (such systems called
32-bit systems, like: last word

32-bit CPU or 64-bit OS) Figure 2.5. Memory words.

13
Memory Location, Addresses,
and Operation
⚫ 32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits

8 bits/1 byte
(or, 1 byte)

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters 14

 Memory Location, Addresses,
and Operation
⚫ To retrieve information from memory, either for one word or
one byte (8-bit), addresses for each location needed.
⚫ Each byte (8-bit group) in the memory are addressable! =>
This is called byte addressable!
⚫ A k-bit addressed memory chip has 2k memory locations,
namely 0 – 2k-1, called memory space. (example: 4 bit =>
addresses 0000 to 1111 = 0 to 15 = 0 to 24-1)
⚫ 1K(kilo)=210=1024;1MB(Megabyte)=1024KB(kilobyte)=210*210=220bytes
⚫ 1GB (Gigabytes)=1024Megabytes=210*220bytes= 230bytes
⚫ 24-bit memory:224= 24*220=16*1Mega= 16M (1Mega=220)
⚫ 32-bit memory: 232 = 4GB (1GB (gigabytes) = 230 bytes
4GB=232 bytes because 4G= 4*1G = 22*230 = 232)
⚫ 1T(tera)=240, (after this, peta=250,exa=260,zetta=270,yotta
15
 Memory Location, Addresses,
and Operation
⚫ It is impractical to assign distinct addresses to
individual bit locations in the memory.
⚫ The most practical assignment is to have
successive addresses refer to successive byte
locations in the memory byte-addressable
memory.
⚫ Byte locations have addresses 0, 1, 2, … If
word length is 32 bits (4 bytes), then
successive words are located at addresses 0,
4, 8,…
16
Big-Endian and Little-Endian Assignment of Memory
Addresses
Big-Endian: higher (bigger) byte addresses are used for the least significant bytes
of the word (hint: bigger address ends it (i.e. at rightmost / LSB)
Little-Endian: opposite ordering. lower byte addresses are used for the less
significant bytes of the word

Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2 - 2 2 - 1 2 - 4 2 - 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Figure 2.7. Byte and word addressing. 17

Memory Location, Addresses,
and Operation
⚫ Ordering of bytes: Little endian and Big endian
schemes
⚫ Word alignment
⚫ Words are said to be aligned in memory if they begin
at a byte address. that is a multiple of the num of
bytes in a word.
⚫ 16-bit word: word addresses: 0, 2, 4, 6, 8, …. bytes
⚫ 32-bit word: word addresses: 0, 4, 8, 12, 16, …. bytes
⚫ 64-bit word: word addresses: 0, 8,16, 24, 32, …. bytes
⚫ Access numbers, characters, and character
strings
18
 Memory Operation
⚫ LOAD (or Read or Fetch)
➢ Copy content from memory to a Register.
The memory content doesn’t change.
➢ CPU places the sought address in MAR register, then places
the RD control signal to the memory chip, then waits, until it
receives the desired data into the MDR register.
⚫ STORE (or Write)
➢ Overwrite the content in memory
➢ CPU Places the Address and Data in MAR and MDR
registers, sends the WR control signal to the memory chip.
Upon completion, the memory chip sends back MFC
(Memory Function Complete) signal.
19
Instruction and
Instruction
Sequencing

20
“Must-Perform” Operations for
computer instructions:
⚫ Data transfers between the memory and the
processor registers
⚫ Arithmetic and logic operations on data
⚫ Program sequencing and control
⚫ I/O transfers

21
Computer instructions must be capable of performing 4 types of
operations:

i. Data transfer/movement between memory and processor registers.

E.g., memory read, memory write

ii. Arithmetic and logic operations:

E.g., addition, subtraction, comparison between two numbers.

iii. Program sequencing and flow of control:

Branch instructions

iv. Input/output transfers to transfer data to and from the real world.

22
Examples of different types of instructions in assembly language notation:

❑ Data transfers between processor and memory:

Move A, B (B = A).
Move A, R1 (R1 = A).

❑ Arithmetic and logic operation:

Add A, B, C (C = A + B)

❑ Sequencing:

Jump Label (Jump to the subroutine which starts at Label).

❑ Input/output data transfer:

Input PORT, R5 (Read from i/o port “PORT” to register R5).

23
Register Transfer Notation
⚫ Identify a location by a symbolic name standing
for its hardware binary address (LOC, R0,…)
⚫ R0, R1, R2, .... => always indicates registers
⚫ Any other symbol => indicates memory location
⚫ Example: X, Y, Z, A, B, M, LOC, LOCA, LOCB
⚫ Contents of a location are denoted by placing
square brackets around the name of the
location (R1←[LOC], R3 ←[R1]+[R2])
⚫ Register Transfer Notation (RTN)
24
 Assembly Language Notation
⚫ Represent machine instructions and programs.

Opcode source_operand destination_operand

OP src_op dest_op

⚫ MOV LOC, R1 ➔ equivalent ==> R1←[LOC]

⚫ ADD R1, R2, R3 ➔ equivalent=> R3 ←[R1]+[R2]

25
 CPU Organization: Internal
Storage Architecture:
⚫ Controls how its instructions use the operand(s).
⚫ The type of internal storage in a processor is the
most basic differentiation.
i. Single Accumulator (AC) CPU Organization
⚫ One operand is implicitly the Accumulator Register.
⚫ The Accumulator is both an implicit input operand and
a source or a destination, depending on the instruction.
⚫ Accumulator (AC) has to be saved to memory quite often.

26
ii. Register-Memory CPU Organization:

• One input operand is a register, one is in memory and

the result of arithmetic operation goes to a register.

•It can access memory as part of any instruction.

iii. Register-Register/Load-Store CPU

Organization:

• All operands are registers.

•It can access memory only with load and store

instructions.
27
iv. Stack CPU Organization:

•No Registers, but CPU-internal stack memory

holds operands and result are always in the stack.

•A Top of stack register (TOS) points to the top

input operand, which is combined with the operand
below. The first operand is removed from the stack,
the result takes the place of the second operand
and TOS is updated to point to the result.

•All operands are implicit.

28
 Instruction Formats
⚫ Three-Address Instructions
⚫ ADD R2, R3, R1 R1 ← [R2] + [R3]
⚫ Two-Address Instructions
⚫ ADD R2, R1 R1 ← [R1] + [R2]
⚫ One-Address Instructions (usually use for Single
Accumulator CPU organization): AC register is always an
implicit operand
⚫ ADD X (AC ← [AC]+M[X] (AC is the Accumulator Register))
⚫ Zero-Address Instructions (Usually for Stack CPU
organization) No explicit operands, both operands are implicit
⚫ ADD (TOS ← TOS + (TOS – 1); TOS means Top of Stack)
⚫ RISC Instructions: An instruction can have 3~4 registers!
Memory Access is restricted Only to LOAD and STORE instructions

Instruction
Opcode Operand(s) or Address(es) 29
Instruction Formats
Example: Evaluate X ← (A+B)  (C+D)

⚫ Three-Address Format
1. ADD A, B, R1 ; R1 ← M[A] + M[B]
2. ADD C, D, R2 ; R2 ← M[C] + M[D]
3. MUL R1, R2, X ; M[X] ← [R1]  [R2]

30
 Instruction Formats
Example: Evaluate X←(A+B)  (C+D)
⚫ Two-Address instruction format
1. MOV A, R1 ; R1 ← M[A]
2. ADD B, R1 ; R1 ← [R1] + M[B]
3. MOV C, R2 ; R2 ← M[C]
4. ADD D, R2 ; R2 ← [R2] + M[D]
5. MUL R2, R1 ; R1 ← [R1]  [R2]
6. MOV R1, X ; M[X] ← [R1]

Why not instructions like ADD A,B to make like B ← A+B

Because => both operands can’t be memory locations, at least one
must be register. Besides the content of B should not be overwritten
(the programmer knows nothing about this side effect!) 31
 Instruction Formats
Example: Evaluate X ← (A+B)  (C+D)
⚫ One-Address Instruction Format
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← [AC] + M[B]
3. STORE T ; M[T] ← [AC]
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← [AC] + M[D]
6. MUL T ; AC ← [AC]  M[T]
7. STORE X ; M[X] ← [AC]

32
 Instruction Formats
Example: Evaluate X = (A+B)  (C+D)
⚫ Zero-Address Instruction Format
(must use stack processor organization.
TOS means Top of Stack)
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ←(C+D)(A+B)
8. POP X ; M[X] ← TOS
33
 Instruction Formats
Example: Evaluate X = (A+B)  (C+D)
⚫ RISC Instruction Format (i).RISC can use 3
registers in a single instruction; (ii).Only the LOAD
and STORE instructions can access memory
1. LOAD A, R1 ; R1 ← M[A]
2. LOAD B, R2 ; R2 ← M[B]
3. LOAD C, R3 ; R3 ← M[C]
4. LOAD D, R4 ; R4 ← M[D]
5. ADD R1, R2, R1 ; R1 ← [R1] + [R2]
6. ADD R3, R4, R3 ; R3 ← [R3] + [R4]
7. MUL R1, R3, R1 ; R1 ← [R1]  [R3]
8. STORE R1, X ; M[X] ← [R1]
34
Using Registers
⚫ Registers are faster
⚫ Shorter instructions
⚫ Potential speedup
⚫ Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.

35
Instruction Execution
⚫ Basic instruction cycle
Fetch/Execute cycle
⚫ Execution of an instruction takes place in two phases:
⚫ Instruction fetch.
⚫ Instruction execute.

⚫ Instruction fetch:
⚫ Fetch the instruction from the memory location whose address is in the Program
Counter (PC).
⚫ Place the instruction in the Instruction Register (IR).
⚫ Instruction execute:
⚫ Instruction in the IR is examined (decoded) to determine which operation is to be
performed.
⚫ Fetch the operands from the memory or registers.
⚫ Execute the operation.
⚫ Store the results in the destination location.
⚫ Basic fetch/execute cycle repeats indefinitely.

37
Straight-line sequencing
⚫ The processor control circuits use the
information in the program counter (PC) to
fetch and execute instructions, one at a time,
in the order of increasing addresses.
⚫ This is called straight- line sequencing.

38
Instruction Execution and
Straight-Line Sequencing
Assumptions:
Address Contents
- One memory operand
Begin execution here i Mov A,R0
per instruction
3-instruction - 32-bit word length
i+4 Add B,R0 program
segment - Memory is byte
i+8 Mov R0,C
addressable
- Each instruction fits in
ONE word (Full memory
A address can be directly
specified in a single-word
instruction
B Data for (though this is not realistic!!!)
the program
Two-phase procedure
-Instruction fetch
-Instruction execute
C

Figure 2.8. A program for C   + 

39
Branching
⚫ Branch instructions load a new value into the
program counter.
⚫ As a result, the processor fetches and
executes the instruction at this new address,
called the branch target, instead of the
instruction at the location that follows the
branch instruction in sequential address
order.

40
Conditional Branching
⚫ A conditional branch instruction causes a
branch only if a specified condition is
satisfied.
⚫ If the condition is not satisfied, the PC is
incremented in the normal way, and the next
instruction in sequential address order is
fetched and executed.

41
 i Move NUM1,R0
Straight-Line i+4 Add NUM2,R0

Sequencing i+8 Add NUM3,R0

•
•
•

Adding An Array i + 4n - 4 Add NUM n,R0

Of Numbers i + 4n Move R0,SUM

without Using
any Loop •
(straight line program) •
•
SUM
NUM1
NUM2

•
•
•
NUM n

Figure 2.9. A straight-line program for adding n numbers.

42
 Move N,R1

Branching Clear R0

Branch target LOOP Determine address of

"Next" number and add
Program "Next" number to R0
loop
Decrement R1

Conditional branch Branch>0 LOOP

Move R0,SUM
Adding An Array
Of Numbers
With Loop •
•
•
SUM
N n
NUM1

Figure 2.10. Using a loop to add n numbers. NUM2

•
•
•
NUM n
43
Book Examples (Fig. 2.12): Move N,R1
Clear R0
Indirect Addressing to
LOOP
Compute the Array Determine address of
"Next" number and add
Program "Next" number to R0
Sum loop
Decrement R1
Branch>0 LOOP
Move R0,SUM

•
•
•
SUM
N n
NUM1
NUM2

•
•
•
NUM n
44
Book Examples (Fig. 2.12): Indirect Addressing
to Compute the Array Sum (Fig. 2.10)

45
 Condition Codes / Status flags
⚫ Condition code flags (Status flags) of the CPU
⚫ Condition code flags are the bits of a special register (i.e., status
register) within the processor. They are affected by the most recent ALU
operations
⚫ N (negative) or S (sign) flag (i.e., bit of the status register) is Set to 1 if the
result of most recent arithmetic operation is negative
⚫ Is used by some instructions, such as: Branch<0 LOOP

⚫ Z (zero) flag: is set if the result of the most recent arithmetic operation is
ZERO
⚫ Used by some instructions, like: Branch==0 LABEL

⚫ C (carry) flag is set if a carry out from most recent operation

⚫ V (Overflow flag) is set if Overflow occurs in most recent op.
⚫ Different instructions affect different flags

46
 Example: How Condition Codes
or Status Flags Set/Reset
⚫ Example: A: 11110000

⚫ A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
⚫ B: 0 0 0 1 0 1 0 0 1 11011100

A = -16; B=20 C=1 Z=0

So, A – B = -36 S=1
16 = 0001 0000
-16 = 2’s complement of 16 V=0
= 1111 0000
Subtract B ➔ Add (–B) = Add 2’s complement of B
= 1110 1100
47
Addressing Modes
⚫ Programmers use data structures to represent the data used in
computations. These include lists, linked lists, array, queues, and so
on

⚫ A high-level language enables the programmer to use constants,

local and global variables, pointers, and arrays

⚫ When translating a high-level language program into assembly

language, the compiler must be able to implement these constructs
using the facilities in the instruction set of the computer

⚫ The different ways in which the location of an operand is

specified in an instruction are referred to as addressing modes
Generic Addressing Modes
Addressing modes

⚫ Different ways in which the address of an operand is specified in

an instruction is referred to as addressing modes.
⚫ Register mode
⚫ Operand is the contents of a processor register.

⚫ Address of the register (its Name) is given in the instruction.

⚫ E.g. Clear R1 or Move R1, R2

⚫ Absolute mode
⚫ Operand is in a memory location.

⚫ Address of the memory location is given explicitly in the

instruction.
⚫ E.g. Clear A or Move LOC, R2
⚫ Also called as “Direct mode” in some assembly languages

⚫ Register and absolute modes can be used to represent

variables 50
Addressing modes (contd..)
⚫ Immediate mode
⚫ Operand is given explicitly in the instruction.

⚫ E.g. Move #200, R0

⚫ Can be used to represent constants.

⚫ Register, Absolute and Immediate modes contained either the

address of the operand or the operand itself.
⚫ Some instructions provide information from which the memory
address of the operand can be determined.
⚫ That is, they provide the “Effective Address” of the operand.

⚫ They do not provide the operand or the address of the operand

explicitly.
⚫ “Effective Address” of the operand can be generated in different
ways.
51
Indirection and Pointers
⚫ Indirect mode: the effective address of
the operand is the contents of a register
or memory location whose address
appears in the instruction
⚫ Indirection is denoted by placing the
name of the register or the memory
address given in the instruction in
parentheses
⚫ The register or memory location that
contains the address of an operand is
called a pointer
Addressing modes (contd..)
Effective Address of the operand is the contents of a register or
a memory location whose address appears in the instruction.

Add (R1),R0 Add (A),R0

Main
memory

B Operand A B

R1 B Register B Operand

•Register R1 contains Address B •Address A contains Address B

•Address B has the operand •Address B has the operand
R1 and A are called “pointers”
This is called as “Indirect Mode”
53
Using Indirect Addressing in a
Program
Using Indirect Addressing in a Program
Indexing and Arrays

⚫ Index mode: the effective address of the

operand is generated by adding a constant
value to the contents of a register
⚫ The register used may be either a special
register provided for this purpose, or, more
commonly, it may be any one of a set of
general purpose registers in the processor.
⚫ The register is referred to as an index register
Indexing and Arrays

⚫ The index mode is useful in dealing with lists

and arrays
⚫ We denote the Index mode symbolically as
X(Ri), where X denotes the constant value
contained in the instruction and Ri is the name
of the register involved.
⚫ The effective address of the operand is given
by EA=X+[Ri].
⚫ The contents of the index register are not
changed in the process of generating the
effective address
Addressing modes (contd..)
Effective Address of the operand is generated by adding a constant
value to the contents of the register

Add 20(R1),R0 •Operand is at address 1020

•Register R1 contains 1000
•Offset 20 is added to the
contents of R1 to generate the
1000 address 1020
•Contents of R1 do not change in the
offset = 20 process of generating the address
•R1 is called as an “index register”
1020 Operand
What address would be generated
by Add 1000(R1), R0 if R1 had 20?

R1 1000

This is the “Indexing Mode”

58
Indexed Addressing
Indexed Addressing
An Example for Indexed Addressing
 Variations of Indexed Addressing Mode

⚫ A second register may be used to contain the offset X, in

which case we can write the Index mode as (Ri,Rj)
⚫ The effective address is the sum of the contents of
registers Ri and Rj.
⚫ The second register is usually called the base register

⚫ This mode implements a two-dimensional array

⚫ Another version of the Index mode use two registers plus a

constant, which can be denoted as X(Ri,Rj)
⚫ The effective address is the sum of the constant X and the
contents of registers Ri and Rj
⚫ This mode implements a three-dimensional array
Relative mode

•Effective Address of the operand is generated by

adding a constant value to the contents of the
Program Counter (PC).
•Variation of the Indexing Mode, where the index
register is the PC instead of a general purpose
register.
•When the instruction is being executed, the PC holds
the address of the next instruction in the program.
•Useful for specifying target addresses in branch
instructions.
•Addressed location is “relative” to the PC, this is
called “Relative Mode”

63
Addressing Modes (contd..)
•Relative mode:
•The Instruction Branch > 0 Loop
•Suppose that the loop starts at address 1000, and
the branch instruction at address 1012.
•The PC value now is 1016.
•To branch to location Loop (1000), the offset value is
1000 – 1016 = -16
•When the assembler processes such instruction, it
computes the required offset value, and generates
the corresponding machine instruction using the
addressing mode:
-16(PC)

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Addressing Modes (contd..)
⚫ Autoincrement mode:
⚫ Effective address of the operand is the contents of a register specified
in the instruction.
⚫ After accessing the operand, the contents of this register are
automatically incremented to point to the next consecutive memory
location.
⚫ (R1)+
⚫ Autodecrement mode
⚫ Effective address of the operand is the contents of a register specified
in the instruction.
⚫ Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive
memory location.
⚫ -(R1)
⚫ Autoincrement and Autodecrement modes are useful for implementing
“Last-In-First-Out” data structures.

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Addressing modes (contd..)

⚫ Implicitly the increment and decrement

amounts are 1.
⚫ This would allow us to access individual bytes in a byte addressable
memory.

⚫ Recall that the information is stored and

retrieved one word at a time.
⚫ In most computers, increment and decrement amounts are equal to the
word size in bytes.

⚫ E.g., if the word size is 4 bytes (32 bits):

⚫ Autoincrement increments the contents by 4.
⚫ Autodecrement decrements the contents by 4.
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An Example of Autoincrement Addressing
Book Examples (Fig. 2.33): Computing Dot
Product of two vectors ... (1)

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Book Examples (Fig. 2.33): Computing Dot
Product of two vectors ... (2)

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