23EC340

COMPUTER ARCHITECTURE AND

ORGANIZATION

[Link]
Assistant Professor
Department of Electronics and Communication Engineering,
Thiagarajar College of Engineering, Madurai – 15.
 Chapter 3
X86

x86 Processors: Architecture and Modes of operations, memory segments and

Programming mode. Instruction sets, assembler directives. Stack, and interrupts.
Memory Banking. ASM Coding for data transfer and arithmetic computations.
Introduction to IA32 architecture.
 Introduction
• In the family of 16 bit microprocessors, Intel's 8086
was the first one to be launched in1978.

• The introduction of the 16 bit processor was a result

of the increasing demand for more powerful and
high speed computational resources.

• The 8086 microprocessor has a much more

powerful instruction set along with the architectural
developments which imparts substantial
programming flexibility and improvement in speed
over the 8 bit microprocessors.

3
8086 Architecture
 Architecture [1]
• 8086 supports a 16 bit ALU, a set of 16 bit registers
and provides segmented memory addressing
capability, a rich instruction set, powerful interrupt
structure, fetched instruction queue for overlapped
fetching and execution etc.
• The internal block diagram, shown in Fig. 1.2
describes the overall organization of different units
inside the chip.
• The complete architecture of 8086 can be divided
into two parts
– Bus Interface Unit (BIU) and
– Execution Unit (EU).
• The bus interface unit contains the circuit for
physical address calculations and pre-decoding
instruction byte queue (6 bytes long).
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6
 Architecture [2]
• The bus interface unit makes the system’s bus
signals available for external interfacing of the
devices. In other words, this unit is responsible for
establishing communication with external devices
and peripherals including memory via the bus.

• For generating a physical address from contents of

this two registers, the content of a segment register
also called as segment address is shifted left bit
wise four times and to this result, content of an offset
register also called as offset address is added, to
produce a 20 bit physical address.
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 Architecture [2]: Physical Address Generation
• For example, if the segment address is 1005H and the offset is 5555H,
then the physical address calculated as below:

Particulars Hex Value Binary Value

Segment 1005H 0001 0000 0000 0101

Address (16 bit)
Offset Address 5555H 0101 0101 0101 0101
(16 bit)
Shifted by 4 – 10050H 0001 0000 0000 0101 0000
bits (20 bit)
Addition 0001 0000 0000 0101 0000
+ 0101 0101 0101 0101
Physical 155A5H 0001 0101 0101 1010 0101
Address (20 bit)

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Example:
 Architecture [3]
• Thus, the segment addressed by the segmented value
1005H can have offset values from 0000H to FFFFH within it,
i.e. maximum 64K locations may be accommodated in the
segment.
• Thus, the segment register indicates the base address of
particular segment, while the offset indicates the distance of
the required memory location in the segment from the base
address.
• Since the offset is 16 bit number, each segment can have a
maximum of 64K locations.
• The bus interface unit has a separate adder to perform this
procedure for obtaining a physical address while addressing
memory.
• The segment address value is to be taken from appropriate
segment register, while the offset may be the content of IP,
BX, SI, DI, SP,BP or an immediate 16 bit value, depending on
addressing mode.

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 Architecture [4]
• In the case of 8085, once the opcode is fetched and
decoded, the external bus remains free for some time, while
the processor internally executes the instruction.
• This time slot is utilized in 8086 to achieve the overlapped
fetch and execution cycles.
• While the fetched instruction is executed internally, the
external bus is used to fetch the machine code of the next
instruction arrange it in a queue known as precoded
instruction byte queue.
• It is a 6 byte long, first in first out structure. The instructions
from the queue are taken for decoding sequentially.
• The execution unit contains the register set of 8086 except
segment register and IP. It has a 16 bit ALU, able to perform
arithmetic and logical operations. The 16 bit flag register
reflects the result of execution by the ALU.

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 Register organization of 8086 [1]
• 8086 has a powerful set of registers known as
general purpose and special purpose registers.
• All of them are 16 bit registers.
• The general purpose registers, can be used as
either 8 bit registers or 16 bit registers.
• These Registers can be either used for holding data,
variables and intermediate results temporarily or for
other purposes like a counter or for sorting offset
address for some particular addressing mode etc.
• The special purpose registers are used as segment
registers, pointers, index registers or as offset
storage registers for particular addressing modes.
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Register Organization of 8086 [2]

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 General Data Register
• The registers AX, BX, CX and DX are the general
purpose 16 bit registers.
– Usually the letters L and H specify the lower and higher bytes of particular
register.
– The letter X used specify the complete 16 bit register.

Register AX: used as 16 bit accumulator, with the lower 8

bits of AX designated as AL and higher 8 bits as AH. AL
can be used as an 8 bit accumulator for 8 bit operations.
Register BX: used as an offset storage for forming
physical addresses in case of certain addressing modes.
Register CX: is also used as a default counter in the
case of string and loop instructions.
Register DX: is a general purpose register which may be
used as an implicit operand or destination in case of a few
instructions.
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 Segment Registers [1]
• The microprocessor 8086 addresses a segmented memory.
• The complete 1 megabyte memory, which the 8086
addresses, is divided into 16 bit logical segments.
• Each segment contains 64 Kbytes of memory.
• There are four segment registers, viz. code segment register
(CS), Data segment register (DS), Extra segment register
(ES) and Stack segment register (SS).
• Code segment register is used for addressing a memory
location in the segment of the memory, where the executable
program is stored.
• Data segment register points to the data segment of the
memory, where the data is resided.
• Extra segment also refers to a segment which essentially is
another data segment of the memory.

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 Segment Registers [2]
• The Stack segment register is used for addressing
stack segment of memory i.e. memory which is used
to store stack data.
• While addressing any location in the any memory
bank, the physical address is calculated from two
parts.
– The first is segment address and
– second is offset.
• The segment registers contain 16 bit segment base
addresses, related to different segments.
• Any of the pointers and index registers or BX may
contain offset of the location to be addressed.
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 Segment Registers [3]
• The advantage of this scheme is that instead
of maintaining a 20 bit register for a physical
address, the processor just maintains two 16
bit registers which are within the word length
capacity of the machine.
• Thus the CS, DS, SS and ES segment
registers, respectively; contain the segment
addresses for the code, data, stack and extra
segments of memory.
• It may be noted that all these segments are
the logical segments.

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 Pointers and Index Registers
• The pointers contain offset within the particular
segments.
• The pointers IP, BP and SP usually contain offsets
within the code, and stack (BP & SP) segments.
• The index registers are used as general purpose
registers as well as for offset storage in case of
indexed, based indexed and relative based indexed
addressing modes.
• The register SI is generally used to store the offset
of source data in data segment while the register DI
is used to store the offset of destination in data or
extra segment.
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 Flag Register [1]
• The 8086 flag register contents indicate the
results of computations in the ALU.
• It also contains some flag bits to control the
CPU operations.

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 Flag Register [2]
• 8086 has a 16 bit flag register which is divided into two parts,
– Condition code or status flag and
– Machine control flags.

• The condition code flag register is the lower byte of the 16

bit flag register along with the overflow flag.

• This flag is identical to the 8085 flag register, with an

additional overflow flag, which is not present in 8085.

• This part of the flag register of 8086 reflects the results of the
operations performed by ALU.

• The control flag register is the higher byte of the flag

register of 8086.
– It contains three flags, viz. direction flag (D), interrupt flag (I) and trap
flag (T).
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 Flag Register [3]
• S (Sign Flag): This flag is set when the result of the
any computation is negative.
• Z (Zero Flag): This flag is set if the result of the
computation or comparison performed by the
previous instruction/instruction is zero.
• P (Parity Flag): This flag is set to 1 if the lower byte
of the result contain even number of 1s.
• C (Carry Flag): This flag is set when there is carry
out of MSB in case of addition or a borrow in case of
subtraction.
• T (Trap Flag): If this flag is set, the processor enters
the single step execution mode.
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 Flag Register [4]
• I (Interrupt Flag): If this flag is set, the maskable interrupt
are recognized by the CPU, otherwise they are ignored.
• D (Direction Flag): This is used by string manipulation
instruction. If this flag bit is ‘0’, the string is processed
beginning from the lowest address to the highest address, i.e.
auto-incrementing mode. Otherwise ,the string is processed
from highest address towards the lowest address, i.e. auto-
decrementing mode.
• AC (Auxiliary Carry Flag): This is set if there is carry from
the lowest nibble, i.e. bit three, during addition or borrow for
the lowest nibble, i.e. bit three, during subtraction.
• O (Overflow Flag): This flag is set when overflow occurs, i.e.
if the result of signed operation is large enough to be
accommodated in a destination register.

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Memory Segmentation
 Memory Segmentation [1]
• The memory in an 8086/8088 based system is
organized as segmented memory (1Mbytes of
physical memory).
• In this scheme, the complete physically available
memory may be divided into a number of logical
segments.
• Each segment is 64K bytes in size and is addressed
by one of the segment registers.
• The 16 bit contents of the segment register actually
point to the starting location of a particular segment.
To address a specific memory location within a
segment, we need an offset address.
• The offset address is also 16 bit long so that the
maximum offset value can be FFFFH, and the
maximum size of any segment is thus 64K locations.
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 Memory Segmentation [2]
• The addresses of the segments may be assigned as
0000H to F000H respectively.
• The offset address value s from 0000H to FFFFH so
that the physical addresses range from 0000H to
FFFFH.
• In the above said case, the segments are non
overlapping segments.
• In some cases, however, the segments may be
overlapping.
• Suppose a segment starts at a particular address
and its maximum size can be 64Kbytes. But, if
another segment starts before this 64Kbytes
location of the segment, the two segments are said
to be overlapping segments.

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 Memory Segmentation [3]
• The main advantages of the segmented
memory scheme are as follows:
– Allows the memory capacity to be 1Mbytes
although the actual addresses to be handled are
of 16 bit size
– Allows the placing of code, data and stack
portions of the same program in different parts
(segments) of memory, for data and code
protection
– Permits a program and/or its data to be put into
different areas of memory each time the program
is executed, i.e. provision for relation is done.

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Memory Segmentation [4]

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PIN Diagram or PIN OUT or Signal description
INTEL 8086 - Pin Diagram
 Signal Description Of 8086 [1]
• The microprocessor 8086 is a 16-bit CPU available in three
clock rates, i.e. 5, 8 and 10MHz, packaged in 40 pin CERDIP
or plastic package.
• The 8086 operates in single processor or multiprocessor
configuration to achieve high performance.
• Some of the pin serve a particular function in minimum mode
(single processor mode) and others function in maximum
mode (multiprocessor mode) configuration.
• The 8086 signal can be categorized in three groups.
– The first are the signals having common function in minimum as well
as maximum mode,
– The second are the signals which have special function for minimum
mode and
– The third are the signals having special function for maximum mode.

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 Signal Description Of 8086 [2]
• AD15-AD0:
– These are the time multiplexed memory I/O address and
data line. Address remains on the lines during T1 state,
while the data is available on data bus during T2,T3,Tw
and T4.

• A19/S6, A18/S5, A17/S4,A16/S3:

– These are the time multiplexed address and status lines.
– During T1, these are the most significant address lines for
memory operations.
– During I/O operation these lines are low.
– During memory or I/O operation, status information is
available on those lines for T2,T3,TW and T4.
– The S4 and S3 together indicate which segment register is
presently being used for memory accesses.

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 Signal Description Of 8086 [3]
• BHE /S7-Bus Enable/status: the bus high enable signal is
used to indicate the transfer of data over the higher order
(D15-D8) data bus shown in table 1.2. it goes low for the data
transfers over D15-D8 and is used to desire chip selects of
odd address memory bank or peripherals.
• RD bar-Read: Read signal, when low, indicates the
peripherals that the processor is performing a memory or I/O
read operation.
• INTR- Interrupt Request : This is a level triggered input. This
is sampled during the last clock cycle of each instruction to
determine the availability of the request. If any interrupt
request is pending, the processor enters the interrupt
acknowledge cycle. The can be internally masked by
resetting the interrupt enable flag.

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 Signal Description Of 8086 [4]
• TEST bar: This input is examined by a WAIT instruction. If the TEST bar
input goes low, execution will continue , else the processor remains in an
idle state.
• NMI-Non Maskable Interrupt: This is an edge-triggered input which
causes a Type 2 interrupt. The NMI is not maskable internally by software.
• RESET: This input causes the processor to terminate the current activity
and start execution from FFFF0H.
• CLK-Clock Input: The clock input provides the basic timing for processor
operation and bus control activity. It’s an asymmetric square wave 33%
duty cycle. The range of frequency for different 8086 versions is from
5MHz to 10MHz.
• Vcc : +5V power supply for the operation of the internally circuit.
• GND: ground for the internally circuit.
• MN/MX bar: The Logic level at this pin decides whether the processor is
to operate in either minimum (single processor) or maximum
(multiprocessor) mode.

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Instruction format
 Machine Language Instruction Format
• A machine language instruction format has one or more
number of fields associated with it.

• The first field is called is as operation code field or opcode

field, which indicates types of operation to be performed by
the CPU.

• The instruction format also contains other field also known as

operands field.

• CPU executes the instruction using the information which

reside in these fields .
• There are six general formats of instruction in 8086 in
instruction set.
• Length of an instruction may vary from one byte to six byte.

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 Machine Language Instruction Format
1. One byte instruction:
− This format is only one byte long may have the implied data or
register operands.
− The least significant 3-bits of the opcode are used for specifying the
register operands, if any.
− Otherwise, all the 8-bits form an opcode and the operands are
implied.

2. Register to Register:
− This format is 2 bytes long.
− The first byte of code specifies the operation code and width of the
operand specified by w bit.
− The second byte of the code shows the register operands and R/M
field.

3. Register to/from Memory with no Displacement:

− This format is also 2 bytes long and similar to the register to register
format except for the MOD field.
− The mode field shows the mode of addressing.
− The MOD, R/M, REG and the W field are decided in table. 57
 Machine Language Instruction Format
4. Register to /from Memory with Displacement:
– This type of instruction format contains one or two additional bytes for
displacement along with two byte the format of register to/form
memory without displacement.
5. Immediate Operand to register:
– In this format, the first byte as well as the 3 bits from the second byte
which are used for REG field in the case of register to register format
are used for opcode.
– It also contains one or two bytes of immediate data.
6. Immediate Operand to Memory with 16-bit displacement:
– This type of instruction format requires 5 or 6 bytes for coding.
– The first 2 bytes contain the information regarding OPCODE, MOD,
and R/M.
– The remaining 4 bytes contain 2 bytes of displacement and 2 bytes of
data.

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 Machine Language Instruction Format
Register to Register:

Register to/from Memory with no Displacement:

Register to /from Memory with Displacement:

Immediate Operand to register:

Immediate Operand to Memory with 16-bit displacement:

39
Machine Language Instruction Format
• The MOD, R/M, REG and the W field are given as:-

40
 Machine Language Instruction Format
• The opcode usually appears in the first byte, but in the few
instruction, a register destination is in the first byte and few
other instruction may have their three bits of opcode in the
second byte.
• The opcodes have the single bit indicator.
• Their definition and significance are given as follows:
– W-bit :
• This indicates whether the instruction is operate over
an 8-bit 16-bit data /operands.
• If W bit is zero, the operand is of 8-bit and if W is 1, the
operand is of 16-bits.
– D-bit:
• This is valid in case of double operand instruction.
• One of the operands must be a register specified by
REG field.
• The register specified by REG is source operand if
D=0, else, it is a destination operand.
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Machine Language Instruction Format
• S-bit :
− This bit is called sign extension bit. The S bit is used
along with W-bit to show the type of operation.
− 8-bit operation with 8-bit immediate operand is
indicated by S=0, W=0;
− 16-bit operation with 16 bit immediate operands is
indicated by S=0, W=1 and
− 16 bit operation with a sign extended immediate data is
given by S=1, W=1
• V-bit:
− This is used in case of shift and rotate instruction.
− This bit is set to 0, if shift count is one and is set to 1,if
CL contains the shift count.
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Machine Language Instruction Format
• Z-bit:
− This bit is used by REP instruction to control the loop.
− If Z-bit is equal to1,the instruction with REP prefix is executed until
the zero flag matches the Z-bit.

– Please note that usually all the addressing modes have DS as the default
data segment.
– However, the addressing modes using BP and SP have SS as the default
segment register.

– DS is the default data segment register when a data is to be referred as an

operand.
– CS is the default code segment register for storing program codes (executable
codes).
– SS is the default segment register for the stack data accesses and operations.
– ES is the default segment register for the destination data address.

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Machine Language Instruction Format
• Assignment of codes with different registers

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Addressing Modes of 8086
 Addressing Modes Of 8086 [1]
• Addressing mode indicate a way of locating data or
operands.
• Depending upon data types used in the instruction and the
memory addressing modes, any instruction may belong to
one or more addressing modes, or some instruction may not
belong to any of the addressing mode.
• Thus the addressing modes describes the types of operand
and the way they are accessed foe executing an instruction.
• According to the flow of instruction execution,
• The instruction may be categorized as
– Sequential control flow instruction and
– Control transfer instruction.
• Sequential execution, transfer control to the next instruction
appearing immediately after it (in the sequence) in the
program.
• The control transfer instruction, on the other hand, transfer
control to some predefined address or the address somehow
specified in the instruction after their execution.
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 Addressing Modes Of 8086 [2]
1. Immediate In this type of addressing, immediate data is a
part of instruction ,and appears in the form of the
successive byte.
Example: MOV AX,0005H

– In this example, 0005H is the immediate data. The immediate data

may be 8-bit in the size.

2. Direct In the direct addressing mode, a 16-bit memory

address is directly specified in the instruction as a part of it.
Example: MOV AX,[5000H]

– Here data resides in in a memory location in the data segment,

whose effective address may be computed using 5000H as the
offset address and content of DS as segment address.

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 Addressing Modes Of 8086 [3]
3. Register: In the register addressing mode, the data is
stored in a register and it is referred using the particular
register. All the register, except IP, may be used in this
mode.
Example: MOV BX, AX

4. Register Indirect: Sometimes the address of memory

location which contain data or operand is determined in an
indirect way, using the offset register.
– This mode of addressing is known as register indirect mode.
– In this addressing mode the offset address of data is in either BX or
SI or DI register.

Example: MOV AX,[BX]

– The default segment is either DS or ES.
– Here, data is present in a memory location in DS whose offset
address is in BX.

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 Addressing Modes Of 8086 [4]
5. Indexed: In this addressing mode offset of the
operand is stored in one of the index register.
– DS is the default segment for index register SI and DI.
– In case of string instruction DS and ES are default
segment for SI and DI respectively.
Example: MOV AX,[SI]
– Here data is available at an offset address stored in SI in
DS.
5. Register Relative: In this addressing mode the
data is available at an effective address formed by
adding an 8-bit or 16-bit displacement with the
content of any one of the register BX, BP,SI and DI
in the default (either DS or ES) segment.
Example: MOV AX,50H[BX]
– Here the effective address is given as
10H*DS+50H+[BX].
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 Addressing Modes Of 8086 [5]
7. Based Indexed: The effective address of data is formed, in this addressing mode,
by adding content of base register (any on e of BX or BP) to the content of an
index register (any one of SI or DI). The default segment register may be ES or
DS.

Example: MOV AX, [BX] [SI]

– Here BX is the base register and SI is the index register.

8. Relative Based Index: The effective address is formed by adding an 8 or 16bit

displacement with sum of content of any one of the base register (BX or BP) and
any one of the index register, in a default segment.

Example: MOV AX, 50H [BX] [SI]

– Here 50H is an immediate displacement, BX is a base register and SI is an Index
register.
– For the control transfer instruction, the addressing mode depend upon whether the
destination location is within the same segment or in a different one.
– Basically, there are two addressing modes for the control transfer instruction, viz.
intersegment and intrasegment addressing mode.
– If the location to which the control is to be transferred lies in a different segment other
than the current one, the mode is called intersegment mode.
– If the destination location lies in the same segment the mode is called intrasegment
mode.

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 Addressing Modes Of 8086 [6]
9. Intrasegment direct mode: In this mode, the address to
which the control is to be transferred lies in the same
segment in which the control transfer instruction lies and
appear directly in the instruction as an immediate
displacement value.
– In this addressing mode, the displacement is computed relative to the
content of the instruction pointer IP.
– The effective address to which the control will be transferred is given
by the sum of 8 or 16 bit displacement and current content of IP.
– In case of jump instruction,
• If the signed displacement (d) is of 8 bits (i. e. -128<d<+127), it as short
jump and
• If it is of 16 bit (i. e. -32767<d<+32767), it is termed as long jump.
– JMP SHORT LABLE lies within -128 to +127 from the current IP
content.
– Thus SHORT LABLE is 8-bit signed displacement.

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 Addressing Modes Of 8086 [7]
10. Intrasegment Indirect Mode: In this mode, the displacement to which the
control is to be transferred, is in the same segment in which the control transfer
instruction lies ,but it is passed to the instruction indirectly. Here the branch
address is found as the content of a register or memory location. This addressing
mode may be used in the unconditional branch instruction.

Example: JMP [BX]; jump to effective address stored in BX register.

11. Intersegment Direct: In this mode, the address to which the control is to be
transferred is in a different segment. This addressing mode provides a means of
branching from one code segment to another code segment. The CS and IP of the
destination address are specified directly in the instruction.

Example JMP 5000H :2000H;

– Jump to effective address 2000H segment 5000H.

12. Intersegment indirect: In this mode the address to which the control is to be
transferred lies in a different segment and it is passed to the instruction indirectly,
i. e. IP(LSB) and CS (MSB) sequentially.

Example JMP [2000H];

– The starting address of the memory block may be referred using any of the addressing
modes, except immediate mode.
– Jump to an address in the other segment specified at effective address 2000H in DS ,
that points to the memory block as said above. 52
The Stack
 The Stack (8 bit)

•The stack is used for temporary storage of

information such as data or addresses.

•When a CALL is executed, the 8086 automatically

PUSHes the current value of CS and IP onto the
stack.

Other registers can also be pushed

Before return from the subroutine, POP instructions

can be used to pop values back from the stack into
the corresponding registers. 54
The Stack (LIFO-last in first out)
Push: Insertion of data
POP: deletion of data
SP: stack pointer

55
Instruction Set of 8086
 Instruction Set Of 8086/8088
• The categories of 8086/8088 instructions are.

1. Data Copy/Transfer Instruction: These are used to transfer data

from source operand to destination operand.
2. Arithmetic and Logical Instruction: These instructions perform
arithmetic, logical, increment, decrement, compare and scan
operations.
3. Branch instruction: These instruction transfer control of execution to
the specified address.
4. Loop Instruction: These instructions are used to implement
unconditional and conditional loops.
5. Machine control instruction: These instruction control the machine
status.
6. Flag Manipulation Instruction: All the instruction which directly affect
flag register, come under this group of instruction.
7. Shift and Rotate Instruction: These instruction involve the bitwise
shifting or rotation in either direction with or without count.
8. String Instruction: These instruction involve various string
manipulation operation like load, MOVE, scan, compare, etc. These
instructions are only to be operated upon the strings.
57
 Data copy/Transfer Instruction
• MOV: Move
– This data transfer instruction transfers data from one register/memory location to
another register/memory location.
– The source may be any one of the segment register or other general or special purpose
register or a memory location and, another register or memory location may act as
destination.
– However in the case of immediate addressing mode ,a segment register cannot be a
destination register.
– To load the segment register with immediate date, one will have to load any general
purpose register with the data and then it will have to be moved to that particular
segment register.
• Examples:

MOV AX, 5000H; Immediate

MOV AX,BX Register
MOV AX, [Si]; Indirect
MOV AX, [2000H]; Direct
MOV AX, 50H[BX]; Based relative, 50H Displacement

MOV DS, 5000H; Not permitted (invalid)

– Thus to transfer an immediate data in to the segment register, we perform the

operation

MOV AX, 5000H

MOV DS, AX
58
 Data copy/Transfer Instruction
• Push: Push to stack
– This instruction pushes the content of the specified register/memory location on to the
stack.
– The stack pointer is decremented by 2, after each execution of the instruction.
– The actual current stack-top is always occupied by the previously pushed data.
– Hence, the push operation decrements SP by two and then stores the two byte content
of operands on to the stack.
– The higher byte is pushed first and then the lower byte.
– Thus out of two decremented stack address the higher byte occupies the higher
address and the lower byte occupies the lower address.
• The actual operation takes place as SS:SP points to the stack top of 8086 system
as shown in figure and AH, AL contain data to be pushed.
2000H

SS

SP-2 (Top of the stack

SP-1 (Top of the stack
SP (Top of the stack)
59
 Data copy/Transfer Instruction
• Push: Push to stack
– The sequence of operations are:
• Current stack top is already occupied so decrement SP by one then store
AH into address pointed to by SP.
• Further decrement SP by one and store AL in to the location pointed by
SP.
– Thus SP is decremented by 2 and AH-AL contents are stored in stack memory
as shown in figure
– Now contents of SP points to a new stack top.
– Example
• PUSH AX
• PUSH DS
• PUSH [5000H]; content of location 5000H and 5001 H in DS are pushed
on to stack.
• To read the contents for the stack memory POP instruction is used.

61
 Data copy/Transfer Instruction
• POP: Pop from stack
– This instruction when executed, loads the specified register/ memory location with the
content of the memory location of which the address is formed using the current stack
segment and stack pointer as usual.
– The stack pointer is incremented by 2.
– The POP instruction serves exactly opposite to PUSH instruction.
• The sequence of operation is as below:
– Contents of stack memory location is stored in AL and SP incremented by one.
– Further contents of memory location pointed by SP are copied to AH and SP is again
incremented by 1.
– Effectively SP is incremented by 2 and points to next stack top.
• The example of these instructions are shown follows
– POPAX
– POP DS
– POP [5000H]

SP
SP+1
AH AL SP+2

62
 Data copy/Transfer Instruction
• XCHG: Exchange
– This instruction exchanges the contents of the specified source and
destination operands, which may be registers or one of them may be a
memory location.
– However, exchange of contents of two memory locations is not permitted.
Immediate data also not allowed in these instructions .

– XCHG [5000H], AX; This instruction exchanges data between AX and a

memory location [5000h] in the data segment.
– XCHG BX, AX; This instruction exchanges data between AX and BX.

• IN: Input the port

– This instruction is used for reading an input port.
– The address of the input port may be specified in the instruction directly or
indirectly.
– AL and AX are the allowed destinations for 8 and 16 bit operations.
– If the port address is 16 bits it must be in DX.
– IN AL, 03H; This instruction reads data from an 8 bit port whose address is
03h and stores it in AL.
– IN AX, DX; This instruction reads data from a 16 bit port whose address is in
DX (implicit) and stores it in AX.

63
 Data copy/Transfer Instruction
• OUT: Output to the Port
– This instruction is used for writing to an output port.
– The address of the output port may be specified in the instruction
directly or implicitly in DX.
– Contents of AX or AL are transferred to a directly or indirectly
addressed port after execution of this instruction.
– The data to an odd addressed port is transferred on D8- D15 while
that to an even addressed port is transferred on D0-D7.
– The registers AL and AX are the allowed source operands for 8 bit and
16 bit operations respectively.
– If the address is of 16 bits it must be in DX.
– OUT 03H, AL; This sends data available in AL to a port whose address
is 03H.
– OUT DX,AX; This sends data available in AX to a port whose address
is specified implicitly in DX.
• XLAT: Translate
– The translate instruction is used for finding out the address codes in
case of code conversion problem, using look up table technique.

64
 Data copy/Transfer Instruction
• LEA: Load effective address
– The load effective address instruction loads the effective address
formed by destination operand into the specified source register.
• LEA BX, ADR; Effective address of label ADR i.e. offset of ADR will
be transferred to Register BX.
• LEA SI, ADR [BX]; offset label ADR will be added to content of BX
to form effective address and it will be loaded in SI.
• LDS/LES: Load pointer to DS/ES
– This instruction loads the DS or ES register and the specified destination
register in the instruction with the content of memory location specified as
source in the instruction.
– Ex: LDS BX, 5000H/LES BX, 5000H

65
 Data copy/Transfer Instruction
• LAHF: Load AH from lower byte of flag
– This instruction loads the AH register with the lower byte of the flag register.
– This command may be used to observe the status of all the condition code flags
(except overflow) at a time.

• SAHF: Store AH to Lower Byte of flag register

– This instruction sets or resets the condition code flags (except overflow) in the
lower byte of flag register depending upon the corresponding bit positions in AH.
– If a bit in AH is 1, the flag corresponding to the bit position is set,else reset.

• PUSHF: Push Flags to Stack

– The push flag instruction pushes the flag register on to the stack; first the upper
byte and then the lower byte is pushed on to it.
– The SP is decremented by 2, for each push operation.
– The general operation of the is instruction is similar to the PUSH operation.

• POPF: Pop flags from stack

– The pop flag instruction loads the flag register completely (both bytes) from the
word contents of the memory location currently addressed by SP and SS.
– The SP is incremented by 2, for each push operation

66
 Arithmetic instructions
• These instructions perform the arithmetic operations, like addition,
subtraction, multiplication and division along with the respective ASCII
and decimal adjust instructions.
• The increment and decrement also belong to this type of instructions.

• ADD: Add
– This instruction adds the immediate data or contents of the memory locations
specified in the instruction or a register (source ) to the contents of the
another register (destination) or memory location.
– The result is in the destination operand. However, both the source and
destination operands can not be memory operands.
– That means memory to memory addition is not possible. Also contents of
segment register can not be added using this instruction.
– Flag register entries will get affected due to this istruction.
– Examples:

1. ADD AX, 0100H Immediate

2. ADD AX, BX Register
3. ADD AX, [SI] Register Indirect
4. ADD AX, [5000H] Direct
5. ADD [5000H], 0100H Immediate
6. ADD [5000H], [0100H] Invalid instruction
67
 Arithmetic instructions
• ADC: Add with Carry
– This instruction performs same operation as ADD instruction, butadds
the carry flag bit (which may be set as a result of the previous
calculations) to the result.
– All the condition code flags effected by this instruction.
– Examples:

– ADC 0100H Immediate (AX implicit)

– ADC AX, BX Register
– ADC AX, [SI] Register Indirect
– ADC AX,[5000H] Direct
– ADC [5000H], 0100H Immediate

• INC : Increment
– This instruction increases the contents of the specified register or
memory location by 1.
– All the condition code flags are affected except the carry flag CF.
– This instruction adds 1 to the contents of the operand.
– Immediate data cannot be operand of this instruction.
– INC AX Register
– INC [BX] Register Indirect
– INC [5000H] Direct 82
 Arithmetic instructions
• DEC: Decrement :
– The decrement instruction subtracts 1 from the contents of the specified
register or memory location.
– All the condition code flags, except the carry flag, are affected depending
upon the results.
– Immediate data cannot be operand of this instruction.

– DECAX Register
– DEC [5000H] Direct

• SUB: Subtract
– The subtract instruction subtracts the source operand from the destination
operand and result is left in destination operand.
– Source operand may be a register, memory location or immediate data and
the destination operand may be a register or a memory location, but source
and destination operands both must not be memory operands.
– Destination operand can not be an immediate data.
– All the condition code flags are effected by this instruction.

– SUB AX, 0100H Immediate [destination AX]

– SUB AX, BX Register
– SUB AX, [5000H] Direct
– SUB [5000H], 0100H Immediate
83
 Arithmetic instructions
• SBB: Subtract with Barrow
– The Subtract with Barrow instruction subtracts the source operand and the borrow flag
(CF) which may be reflect the result of previous calculations, from the destination
operand.
– Subtract with Barrow, here means subtracting 1 from the subtraction obtained by SUB,
if carry (borrow) flag is set.
– The result stored in destination operand. All flags are effected (condition code) by this
instruction.
– SBB AX, 0100H Immediate [destination AX]
– SBB AX, BX Register
– SBB AX,[5000H] Direct
– SBB [5000H], 0100H Immediate
• CMP: Compare
– This instruction compares the source operand, which may be a register or an
immediate data or a memory location, with a destination operand that may be register
or memory location.
– For comparison, it subtracts the source operand from destination operand but does not
stores the result anywhere.
– The flags are affected depending upon the result of subtraction.
– If both operands are equal, zero flag is set. If source operand is greater than destination
operand carry flag is set or else carry flag is reset.

– CMP BX, 0100H Immediate

– CMP AX, 0100H Immediate
– CMP [5000H], 0100H Direct
– CMP BX, [SI] Register Indirect
– CMP BX, CX Register 84
 Arithmetic instructions
• AAA: ASCII Adjust AfterAddition:
– The AAA instruction executed after ADD instruction that adds two ASCII coded
operands to give a byte of result in AL.
– The AAA instruction converts the resulting contents of AL to unpacked decimal
digits.
– After the addition, the AAA instruction examines the lower 4 bits of Alto check
whether it contains the valid BCD number in the range 0 to 9.
– If it is between 0 to 9 and AF is zero, AAA sets the 4 high order bits of AL to0.
– The AH must be cleared before addition.
– If the lower digit of AL is between 0 to 9 and AF is set, 06 added to AL.

71
AAA
OR AX, 3030H
 Arithmetic instructions
– If the lower digit of AL is between 0 and 9 and AF is set, 06 is added to AL.
– The upper 4 bits of AL are cleared and AH is incremented by one.
– If the value in lower nibble of AL is greater than 9 then the AL is incremented
by 06,AH is incremented by 1 the AF and CF flags are set to 1, and the higher
4 bits of AL are cleared to 0.
– The remaining flags are unaffected.
– The AH is modified as sum of previous content (usually 00) and carry from the
adjustment.
– This instruction does not give exact ASCII codes of the sum, but they can be
obtained by adding 3030H to AX.

• AAS:ASCII Adjust AL after Subtraction

– AAS instruction correct the result in AL register after subtracting two unpacked
ASCII operands.
– The result is in unpacked decimal format.
– If the lower 4bits of AL register are greater than 9 or if the AF flag is 1,
– The AL is decremented by 1, the CF and AF are set to 1, otherwise the CF
and AF are set to 0.
– The result need no correction. As a result the upper nibble of AL is 00 and the
lower nibble may be any number from 0 to 9. The procedure is similar to the
AAA instruction except for the subtraction of 06 from AL.
– AH is modified as difference of previous contents (usually 0) of AH and borrow
for adjustment.
77
 Arithmetic instructions
• AAM:ASCII Adjust after Multiplication
– This instruction after execution converts the products
available in AL in to unpackaged BCD format.
– The AAM instruction follows a multiplication instruction
that multiplies two unpacked BCD operands i.e. higher
nibbles of the multiplication operands should be 0.
– The multiplication of such operands is carried out using
MUL instruction.
– Obviously the result of multiplication is available in AX.
– The following AAM instruction replaces content of AH by
tens of decimals multiplication and AL by singles of the
decimal multiplication.

– MOV AL , 04 ; AL ← 04
– MOV BL, 09 ; BL ← 09
– MUL BL ; AH-AL ← 24H(9*4)
– AAM ; AH ←03; AL ← 06
78
 Arithmetic instructions
• AAD:ASCII Adjust before Division
– Though the names of these two instruction (AAM and
AAD) appear to be similar there is a lot of difference
between their function.
– The AAD instruction converts two unpacked BCD digits in
AH and AL to the equivalent binary number inAL.
– This adjustment must be made before dividing the two
unpacked BCD digits in AX by an unpacked BCD byte.
– PF, SF, ZF are modified while AF, CF, OF are undefined,
after the execution of instruction AAD.
– In the instruction sequence this instruction appears before
DIV instruction unlike AAM appears after MUL.
– The examples explains the execution of the instruction.
– Let AX contents as 0508H
– AAD; Result in AX will be 003AH

79
 Arithmetic instructions
• DAA: Decimal Adjust Accumulator
– This instruction is used to convert the result of addition of two packed
BCD number to a valid BCD number.
– The result has to be only in AL, if the lower nibble is greater than 9,
after addition or if AF is set, it will add 06 to the lower nibble inAL.
– After addition 06 in the lower nibble of AL if the upper nibble of AL is
greater than 9 or if carry flag is set, DAA instruction adds 60H to AL.
– The instruction DAA affects AF, CF ,PF and ZF flags. The OFis
undefined.
• DAS: Decimal Adjust after Subtraction
– This instruction converts the result of subtraction of two packed BCD
numbers to a valid BCD number.
– The subtraction has to be in AL only, if the lower nibble of AL is greater
than 9 this instruction will subtract 06 from lower nibble ofAL.
– If the result of subtraction sets the carry flag or if upper nibble is
greater than 9 it subtracts 60H fromAL.
– This instruction modifies the AF, CF, SF, PF and ZF flags. The OF is
undefined after DAS instruction.

80
 Arithmetic instructions
• NEG: Negate
– The negate instruction forms 2’s complement of the specified destination in
the instruction.
– For obtaining 2’s complement it subtracts the component of destination from
zero.
– The result is stored back in the destination operand which may be a register
or a memory location.
– If OF is set it indicates that the operation could not be completed successfully.
This instruction affects all the condition code flags.

• MUL: Unsigned Multiplication Byte or Word

– This instruction multiplies an unsigned bytes or word by the contents of AL.
– The unsigned byte or word may be in any one of the general purpose register
or memory location.
– The most significant word of the result is stored in DX, while the least
significant word of the result is stored in AX.
– All the flags are modified depending upon the result.
– Example
• MUL BH ;(AX) ← (AL) * (BH)
• MUL CX ;(DX) (AX) ← (AX) * (CX)
• MUL WORD PTR[SI] ;(DX) (AX) ← (AX) * [SI]

81
 Arithmetic instructions
• IMUL: Signed multiplication
– This instruction multiplies a signed byte in source operand by a signed byte in
AL or a signed word in source operand by a signed word in AX.
– The source can be a general purpose register, memory operand, index
register or base register, but it cannot be immediate data.
– In case of 32 bit result , the higher order word (MSW) is stored in DX and
lower order word is stored in AX.
– The AF, PF, SF and ZF flags are undefined after IMUL.
– If AH and DX contain parts of 16 and 32 bit result respectively CF and OF
both will be set.
– The AL and AX are the implicit operand in case of 8bits and 16bits
multiplication respectively.
– Example
– IMUL BH
– IMUL CX
– IMUL [SI]
• CBW: Convert Signed Byte or Word
– This instruction converts a signed byte to a signed word.
– In other words, it copies the sign bit of a byte to be converted to all bits in the
higher byte of the result word.
• CWD: Convert Signed Word to Double word
– This instruction copies the sign bit of AX to all the bits of DX register.

82
 Arithmetic instructions
• DIV: Unsigned Division
– This instruction performs unsigned division.
– It divides an unsigned words or double word by a 16bit or 8bit operand.
– The dividend must be in AX for 16-bit operation and divisor may be specified
using any one of the addressing modes except immediate.
– The result will be in AL while AH will contain the remainder.
– In case of double word dividend (32-bit) the higher word should be in DX and
lower word should be in AX.
– The divisor may be specified as already explained.
– The quotient and the remainder, in this case will be in AX and DX respectively.
– This instruction does not affect any flag.

• IDIV: Signed Division

– This instruction performs the same operation as the DIV instruction but with
signed operands.
– The result are stored similarly as in case of DIV instruction in both cases or
word and double word division.
– The result will also be signed numbers.
– The operands are also specified in the same way as DIV instruction.
– Divide by 0 interrupt is generated, if the result is too big to fit in AX (16-bit
dividend operation) or AX and DX (32-bit dividend operation).
– All the flags are undefined after IDIV instruction.
83
 Logical instructions
• These types of instructions are used for carrying out the bit by bit shift ,
rotate or basic logical operation. All the condition code flags are affected
depending upon the result. Basic logical operation available with 8086
instruction set are AND, OR, NOT, and XOR.
• AND: Logical AND
– This instruction bit by bit ANDs the source operand that may be an immediate,
a register or a memory location to the destination operand that may be
register or memory location.
– The result is stored in the destination operand. both the operands cannot be
memory location or immediate operands.
– Example
– AND AX, 0008H
– AND AX, BX

• OR: Logical OR
– The OR instruction carries out the OR operation in the same way as described
in case of AND operation.
– The limitation on source and destination operands are also the same as in the
case of AND operation.
– Examples
– OR AX, 0098H
– OR AX, BX
– OR AX, [5000H]
84
 Logical instructions
• NOT: Logical Invert
– The NOT instruction complements the content of an operand register or a
memory location, bit by bit.
• NOT AX
• NOT [5000H]

• XOR: Logical Exclusive OR

– The XOR operation is again carried out in a similar way to the AND and OR
operation.
– The constraints in the operands are also similar. The XOR operation gives a
high output when the two input bits are dissimilar. Otherwise the output is zero.
• XOR AX,0098H
• XOR AX,BX

• TEST: Logical Compare Instruction

– The TEST instruction performs a bit by bit logical AND operation on the two
operands. Each bit of the result is then set to 1.
– If the corresponding bits of both operands are 1,else the result bit is reset to 0.
– The result of this ANDing operation is not available for further use, but flags are
affected.
– The affected flags are OF, CF, SF, ZF, and PF. The Operands may be register,
memory or immediate data.
• TEST AX, BX
• TEST [0500H], 06H
• TEST [BX] [DI], CX
85
 Logical instructions
• SHL/SAL: Shift Logical/Arithmetic Left
– These instruction shifts the operand word or byte bit by bit to the left and insert
zeros in the newly introduced least significant bits.
– In case of all SHIFT and ROTATE instruction, the count is either 1 or specified
by register CL.
– The operand may reside in a register or memory location but cannot be
immediate data. All the flags are affected depending upon the result.

• SHR: Shift Logical Right

– This instruction performs bit-wise right shifts on the operand word or byte that
may reside in a register or memory location, by the specified count in the
instruction and inserts zeroes in the shifted position.
– The result is stored in the destination operand.

• SAR: Shift Arithmetic Right

– This instruction performs right shift on the operand word or byte, that may be
register or memory location by the specified count in the instruction.
– It inserts the most significant bit of the operand in the newly inserted position.
The result is stored in the destination operand.
– This shift operation shifts the operand through the carry flag.
– All the condition code flags are affected.

• Immediate operand is not allowed in any of the shift instruction.

86
 Logical instructions

SHL/SAL: Shift Logical/Arithmetic Left

SHR: Shift Logical Right

87
 Logical instructions

SAR: Shift Arithmetic Right

• ROR: Rotate Right without Carry

− This instruction rotates the contents of the destination operand to the right
(bitwise) either by one or by the count specified in CL Excluding carry.
− The least significant bit is pushed in to the carry flag and simultaneously it is
transferred in the most significant bit position at each operation.
− The remaining bits are shifted right by the specified position.
− The PF, SF and ZF flags are left unchanged by rotate operation.
− The operand may be a register or a memory location but it cannot be an
immediate operand.

88
 Logical instructions
• ROL: Rotate Left without Carry
• This instruction rotates the content of destination operand to the left by the specified
count (bit-wise) excluding carry.
• The most significant bit is pushed in to the carry flag as well as the least significant
bit position at each operation.
• The remaining bits are shifted left subsequently by the specified count position.
• The PF, SF and ZF flags are left unchanged in this rotate operation.
• The operand may be a register or a memory location.

• RCR: Rotate Right through Carry

• This instruction rotates the contents (bit-wise) of the destination operand right by the
specified count through carry flag.
• For each operation the remaining bits are shifted right by the specified count position.
• The SF, PF and ZF are left unchanged.
• The operand may be register or memory location.

• RCL: Rotate Left through Carry

• This instruction rotates (bit-wise) the contents of the destination operand left by the
specified count through the carry flag.
• For each operation the carry flag is pushed in to LSB, and the MSB of the operand is
pushed in to carry flag.
• The remaining bits are shifted left by the specified position.
• The SF, PF and ZF are left unchanged.
• The operand may be register or memory location.

89
 Logical instructions
ROR: Rotate Right
without Carry

ROL: Rotate Left

without Carry

RCR: Rotate Right

through Carry

RCL: Rotate Left

through Carry

90
 String Manipulation Instruction
• A series of data bytes or words available in memory at consecutive
location, to be referred to collectively or individually, are called as byte
string or word string.
• For example a string of a character may be or located in consecutive
memory location where each character may be represented by itsASCII
equivalent.
• For referring to string, two parameters are required (a) starting or end
address of string (b) length of string.
• The length of string usually stored as a count in CX register.
• The incrementing or decrementing of pointer in case of 8086 string
instruction depends upon the direction flag status.
• If it is a byte string operation the index register are updated by one.
• If it is word string operation the index register are updated by two.
• The counter in both cases, is decremented by one.

• REP: Repeat Instruction Prefix

– This instruction is used as a prefix to other instruction.
– The instruction to which the REP prefix is provided is executed repeatedly
until the CX register becomes Zero.
– When CX becomes zero the execution proceeds to the next instruction in
sequence.
91
 String Manipulation Instruction
• MOVSB/MOVSW: Move String Byte or String Word
– Suppose a string of bytes stored in a set of memory location to be moved to
another set of destination location.
– The starting byte of the source string is located in the memory location whose
address may be computed using SI (source index) and DS (data segment)
contents.
– The starting address of the destination location where this string has to be
relocated is given by DI (destination index) and ES (extra segment) contents.
– The starting address of source string is 10H*DS+[SI], while the starting
address of the destination string is 10H*ES+[DI].
– The MOVSB/MOVSW instruction moves a string of bytes /words pointed to by
DS:SI (source) pair to the memory location pointed to by ES:DI pair
(destination).
– The length of the byte string or word string must be stored in CX register.
– No flags are affected by this instruction.

– After the MOVS instruction is executed once, the index register are
automatically updated and CX is decremented.
– The incrementing or decrementing of pointer i.e. SI and DI depend upon the
direction flag DF.
– If DF is 0, the index register are incremented, otherwise they are decremented
in case of all the string manipulation instruction.

92
 String Manipulation Instruction
1. Example for MOVSB 2. Example for MOVSB
– MOV AX, 2000H – MOV AX, 5000H
– MOV DS, AX – MOV DS, AX
– MOV AX, 3000H – MOV AX, 3000H
– MOV ES,AX – MOV ES,AX
– MOV CX, 00FFH – MOV CX, 00FFH
– MOV SI, 1000H – LEA SI, SOURCE_STRING
– MOV DI, 2000H – LEA DI, DESTIN_STRING
– CLD – CLD
– REP MOVSB – REP MOVSB

93
 String Manipulation Instruction
• CMPS: Compare String Byte or String
– The CMPS instruction can be used to compare two string of bytes or
words.
– The length of the string must be stored in a register CX.
– If both the byte or word string are equal, zero flag is set.
– The flags are affected in same way as CMP instruction.
– The DS:SI point to the two string.
– The REP instruction prefix is used to repeat the operation till CX
becomes zero
• SCAS: Scan String Byte or String Word
– This instruction scans string of byte or words for an operand byte or
word specified in the register AL orAX.
– The string is pointed to by ES; DI register pair.
– The length of the string is stored in CX.
– The DF controls the mode for scanning of the string.
– Whenever a matched to the specified operand, is found in the string,
execution stops and zero flag is set.
– If no match is found, the zero flag is reset.

94
 String Manipulation Instruction
• Example for CMPSB 2. Example for SCAS
– MOV AX, 2000H
– MOV DS, AX – MOV AX, 5000H
– MOV AX, 3000H – MOV ES, AX
– MOV ES,AX – MOV CX, 00FFH
– MOV CX, 00FFH – LEA DI, DESTIN_STRING
– MOV SI, 1000H – CLD
– MOV DI, 2000H – REPNE SCASW
– CLD
– REP CMPSB

95
 String Manipulation Instruction
• LODS: Load String Byte or String Word
– The LODS instruction loads the AL /AX register by the content of a string pointed to by
DS;SI register pair.
– The SI is modified automatically depending upon DF.
– The DF plays exactly to same role as in case of MOVSB/MOVSW instruction.
– If it is a byte transfer (LODSB), the SI is modified by one and if it is a word transfer
(LODSW ), the SI is modified bye two.
– No other flags are affected by this instruction.

• STOS: Store String Byte or String Word

– The STOS instruction stores the AL/AX register contents to a location in string pointed
by ES:DI register pair.
– The DI is modified accordingly. No flags are affected by this instruction.
– The direction flag controls the string instruction execution.
– The source index SI and destination index DI are modified after each iteration
automatically. If DF is 1, then the execution follows auto decrement mode.
– In this mode SI and DI are decremented automatically after each iteration (by 1 or 2
depending upon byte or word operation).
– Hence, in auto decrement mode, the string are referred to by their ending addresses.
– If DF =0, then execution follows auto increment mode.
– In this mode SI and DI are incremented automatically after each iteration (by 1 or 2
depending upon byte or word operation).
– After each iteration, hence the string, in this case, are refer to by their starting
addresses.

96
 Control transfer or Branching Instruction
• The control transfer instructions transfer the flow of execution of the
program to a new address specified in the instruction directly or indirectly.

• When this type of instruction is executed, the CS and IP registers get

loaded with new values of CS and IP corresponding to the location where
the flow of execution is going to transferred.

• Unconditional control transfer (Branch) instruction

– In case of unconditional control transfer instructions, the execution control is
transferred to the specified location independent of any status or condition.
– The CS and IP are unconditionally modified to the new CS and IP.

• Conditional control transfer (Branch) instruction

– In the conditional control transfer instructions, the control is transferred to the
specified location provided the result of the previous operation satisfies a
particular condition.
– Other wise, the execution continues in normal flow sequence.
– The results of the previous operations are replicated by condition code flags.

97
 Control transfer or Branching Instruction
• Unconditional Branch Instructions
– CALL Unconditional Call
• This instruction is used to call a subroutine from a main program.
• There are again two types of procedures depending upon whether
it is available in the same segment (Near CALL, i.e. +/- 32K
displacement) or in other segment (FAR CALL, i.e. anywhere
outside the segment).
• The modes for them are called as intrasegment and intersegment
addressing modes respectively.
• On execution, this instruction stores the incremented IP (i.e.
address of the next instruction) and CS onto the stack and loads
the CS and IP registers, respectively, with the segment and offset
addresses of the procedure to be called.
• In case of NEAR CALL it pushes only IP register and in case of
FAR CALL it pushes IP and CS both onto the stack.
• The NEAR and FAR CALLS are discriminated using opcode.

98
 Control transfer or Branching Instruction
• RET: Return From the Procedure
– At each CALL instruction, the IP and CS of the next instruction is
pushed onto stack, before the control is transferred to the procedure.
– At the end of the procedure, the RET instruction must be executed.
– When it is executed, the previously stored content of IP and CS along
with flags are retrieved into the CS, IP and flag register from the stack
and execution of the main program continues further.
– The procedure may be a near or far procedure. In case of a FAR
procedure, the current contents of the SP points to IP and CS atthe
time of return.
– While in case of a NEAR procedure, it points to only IP.

– Depending upon the type of procedure and the SP contents, RET

instruction is of four types:-
1. Return within segment.
2. Return within segment adding 16 bit immediate displacement to the SP
contents.
3. Return intersegment.
4. Return intersegment adding 16 bit immediate displacement to the SP
contents.

99
 Control transfer or Branching Instruction
• INT: Interrupt Type N
– In the interrupt structure of 8086/8088, 256 interrupts are
defined corresponding to the types from 00H to FFH.
– When an INT N instruction is executed, the TYPE byte N
is multiplied BY 4 and the contents of IP and CS of the
interrupt service routine will be taken from the
hexadecimal multiplication (N * 4) as offset address and
0000 as segment address.

• INTO: Interrupt on Overflow

– This command is executed, when the overflow flag OF set.
– The new contents of IP and CS are taken from the
address 0000:0010 as explained in INT type instruction.
– This is equivalent to a Type 4 interrupt instruction.
100
 Control transfer or Branching Instruction
• JMP: Unconditional Jump:
– This instruction unconditionally transfers the control of execution to the
specified address using an 8 bit or 16 bit displacement (intrasegment relative,
short or long) or CS:IP (intersegment direct far).
– No flags are affected by this instruction.
– Corresponding to the methods of specifying jump addresses, the JUMP
instruction may have the following three formats.

• IRET: Return from ISR

– When an interrupt service routine is to be called, before transferring control to
it, the IP, CS and flag register are stored on to the stack to indicate the
location from where the execution is to be continued, after the ISR is
executed.
– So at the end of each ISR, when IRET is executed, the values of IP, CS and
flags are retrieved from the stack to continue the execution of the main
program.
– The stack is modified accordingly.
101
 Control transfer or Branching Instruction
• LOOP: Loop Unconditionally
– This instruction executes the part of the program from the label or address
specified in the instruction up to the loop instruction, CX number of times.
– The following sequence explains the execution.
– At each iteration, CX is decremented automatically.
– In other words, this instruction implements DECREMENT COUNTER and
JUMP IF NOT ZERO structure.

• Condition Branch instructions

– When these instructions are executed, execution control is transferred to
address specified relatively in the instruction, provided the condition implicit in
the opcode is satisfied.
– If not the execution continues sequentially.
– The conditions, here, means the status of condition code flags.
– These type of instructions do not affect any flag.
– The address has to be specified in the instruction relatively in terms of
displacement which must lie within 80H to 7FH bytes from the address of
branch instruction.
– In other words, only short jumps can be implemented using conditional branch
instructions.
– A label may represent the displacement, if it lies within above specified range.

102
Control transfer or Branching Instruction

103
Control transfer or Branching Instruction

•LOOP: Loop Conditionally

104
 Flag Manipulation and Processor Control Instructions
• These instructions control the functioning of the available hardware inside
the processor chip.
• These are categorized into two types;

– (a) flag manipulation instructions and

– (b) machine control instructions.

• The flag manipulation instructions directly modify some of the flags of

8086.
• The machine control instructions control the bus usage and execution.
• These instructions modify the Carry (CF), Direction (DF) and Interrupt (IF)
flags directly.
• The DF and IF, which may be modified using the flag manipulation
instructions, further control the processor operation; like interrupt
responses and auto increment or auto decrement modes.
• Thus, the respective instructions may also be called machine or
processor control instructions.
• The other flags can be modified using POPF and SHAF instructions,
which are termed as data transfer instructions,

105
Control transfer or Branching Instruction
Flag manipulation Instructions
Sr. No. Instruction Function
1 CLC Clear carry flag
2 CMC Complement carry flag
3 STC Set carry flag
4 CLD Clear direction flag
5 STD Set direction flag
6 CLI Clear interrupt flag
7 STI Set interrupt flag

Flag manipulation Instructions

Sr. No. Instruction Function
1 WAIT Wait for test input pin to go low
2 HLT Halt the processor
3 NOP No operation
4 ESC Escape to external devices like numeric co-processor
5 LOCK Bus lock instruction prefix.

106
Assembler Directives and Operators
 Assembler Directives and Operators
• To make the programming on microprocessor simpler,
assemblers are used. The main role of the assembler is to
convert the assembly language program in to the machine
language program and in 8086 since the hand coding is a
tedious job mostly people follow the assembler for
programming the microprocessor.
• For completing the task of the assembly, assembler needs
some hints from the programmer i.e. the required storage of
particular constant or variable, logical names of the
segments, types of different subroutines or modules, end of
file etc.
• Such hints are given by the assembler directives.
• Another type of hint which helps the assembler to assign a
particular constant with a label or initialize particular memory
locations or labels with constants is an operator. 108
 Assembler Directives and Operators
• DB: Define Byte
– It is used to reserve byte or bytes of memory locations in the available memory
space.
• DW: Define Word (1 – word = 2 – bytes)
– It is used to reserve word or words of memory locations in the available memory
space.
• DD: Define Double Word (1 – double word = 4 – bytes)
– It is used to reserve word or words of memory locations in the available memory
space.
• DQ: Define Quad Word (1 – quad word = 8 – bytes)
– It is used to reserve two words of memory locations in the available memory
space.
• DT: Define Ten Bytes
– It is used to reserve ten bytes of memory locations in the available memory
space.
• Usage:
– RANKS DB 01H,02H,03H
– WORDS DB 1234H,0250H,03ABH
– LABEL1 DQ 1234567887654321H
– PLAYERS_RANKS DT 01H,02H,03H, 31H,22H,03H 21H,32H,07H 10H,
109
 Assembler Directives and Operators
• Assume: Assume logical segment name
– It is used to indicate the start of a logical segment
– ASSUME DS: DATA it implies that the start of a new segment named
DATA and its base address is to be initialized to DS.
• END - END directive is placed after the last statement of a
program to tell the assembler that this is the end of the
program module. The assembler will ignore any statement
after an END directive. Carriage return is required after the
END directive.
• ENDP - ENDP directive is used along with the name of the
procedure to indicate the end of a procedure to the
assembler
• Example:
– SQUARE_NUM PROCE ; It start the procedure
– ;Some steps to find the square root of a number
– SQUARE_NUM ENDP ;Hear it is the End for the procedure

110
 Assembler Directives and Operators
• ENDS - This ENDS directive is used with name of
the segment to indicate the end of that logic
segment.
– Example:
– CODE SEGMENT ;Hear it Start the logic
– ;segment containing code
– ; Some instructions statements to perform the logical operation
– CODE ENDS ;End of segment named as CODE

• ENDS - This ENDS directive is used with name of

the segment to indicate the end of that logic
segment.
– Example:
– CODE SEGMENT ;Hear it Start the logic segment containing code
– ; Some instructions statements to perform the logical operation
– CODE ENDS ;End of segment named as CODE
111
 Assembler Directives and Operators
• EQU - This EQU directive is used to give a name to some
value or to a symbol. Each time the assembler finds the
name in the program, it will replace the name with the value
or symbol you given to that name.
– Example:
• FACTOR EQU 03H ; you has to write this statement at the starting
of your program and later in the program you can use this as
follows
• ADD AL, FACTOR ; When it codes this
• instruction the assembler will code it as ADDAL, 03H

• The advantage of using EQU in this manner is, if FACTOR is

used many no of times in a program and you want to change
the value, all you had to do is change the EQU statement at
beginning, it will changes the rest of all.

112
 Assembler Directives and Operators
• EVEN - This EVEN directive instructs the assembler to
increment the location of the counter to the next even
address if it is not already in the even address.
– If the word is at even address 8086 can read a memory in 1 bus cycle.
– If the word starts at an odd address, the 8086 will take 2 bus cycles to
get the data.
– A series of words can be read much more quickly if they are ateven
address.
– When EVEN is used the location counter will simply incremented to
next address and NOP instruction is inserted in that incremented
location.

• Example:
– DATA1 SEGMENT
– ; Location counter will point to 0009 after assembler reads next
statement
– SALES DB 9 DUP(?) ;declare an array of 9 bytes
– EVEN ; increment location counter to 000AH
– RECORD DW 100 DUP( 0 ) ;Array of 100 words will start from an
even address for quicker read
– DATA1 ENDS
113
 Assembler Directives and Operators
• EXTERN: External and PUBLIC: public
– The directive EXTERN informs the assembler that the names,
procedures and labels declared after this directive have already been
defined in some other assembly language modules.
• GROUP: Group the Related Segment
– This directive is used to form logical groups of segments with similar
purpose or type. This directive is used to inform the assembler to form
a logical group of the following segment names.
• PROGRAM GROUP CODE, DATA, STACK
• LABEL: label
– The Label directive is used to assign a name to the current content of
the location counter. When the assembly process starts, the
assembler initializes a location counter to keep track of memory
location assigned to the program.
• LENGTH: Byte Length of a label
– This directive is not available in MASM. This is used to refer to the
length of data array or string.
– MOV CX, LENGTH ARRAY

114
 Assembler Directives and Operators
• LOCAL
– The labels, variables, constants or procedures declared LOCAL in a
module are to be used only by the particular module.
– LOCAL a, b, DATA, ARRAY, ROUTINE
• NAME: Logical Name of a Module
– The NAME directive is used to assign a name to an assembly
language program module. The module, may now referred to by its
declared name.
• OFFSET: Offset of a Label
– When the assembler comes across the OFFSET operator along with a
label, it first computes the 16-bit displacement (also called as offset
interchangeably) of the particular label, and replaces the string
OFFSET LABEL by the computed displacement. This operator is used
with arrays, strings, labels and procedures to decide their offset in
their default segments.

• CODE SEGMENT
• MOV SI, OFFSET LIST
• CODE ENDS
• DATA SEGMENTS
• LIST DB 10H
• DATA ENDS 123
 Assembler Directives and Operators
• ORG: Origin
– The ORG directives directs the assembler to start the memory
allotment for the particular segments, block or code from the declared
address in the ORG statement.
– If an ORG 200H address in code segment is present at the starting of
the code segment of that module then the code will start from 200H
address in code segment.
• PROC: Procedure
– The PROC directives marks the start of named procedure in the
statement.
– Also the types NEAR or FAR specify the type the procedure i.e.
whether it is to be called by the main program located within 64k of
physical memory or not.
• PTR: Pointer
– The POINTER operator is used to declare the type of a label, variable
or memory operand.
– The operator PTR prefixed by either BYTE or WORD.
– If prefix is byte then the particular label, variable or memory operand is
treated as an 8-bit quantity, while if word is the prefix, then it is treated
as a 16-bit quantity.
116
 Assembler Directives and Operators
• PUBLIC
– The PUBLIC directive is used along with the Extern directive.
– This informs the assembler that the labels, variables constants, or procedures
declared PUBLIC may be accessed by other assembly modules to form their
codes, but while using the PUBLIC declared labels, variables, constants or
procedures the user must declare them externals using the extern directive.

• SEGMENT: Logical Segment

– The SEGMENT directive marks the starting of logical segment.
– The started segment is also assigned a name, i.e. label, by this statement.
• [Link] SEGMENT GLOBAL
;Start of segment named [Link], that can be accessed by any other module.
• [Link] ENDS ; END of [Link] logical segment.

• SHORT
– The SHORT operator indicates to the assembler that only one byte is required
to code the displacement for a jump (i.e. displacement is within -128 to +127
bytes from address of the byte next to the jump opcode).
• JMP SHORT LABEL

117
 Assembler Directives and Operators
• TYPE
– The TYPE operator directs the assembler to decide the data type of
the specified label and replaces the ‘TYPE’ label by the decided data
type.
• GLOBAL
– The labels, variables, constants or procedures declared GLOBAL may
be used by other modules of the program. Once a variable is declared
GLOBAL, it can be used by any module in the program.
• FAR PTR
– This directive indicates the assembler that the label following FAR
PYTR is not available within the same segment and the address of the
label is of 32- bits i.e. 2-bytes offset followed two byte segment
address.
• NEAR PTR
– This directive indicates that the label following NEAR PTR is in the
same segment and needs only 16-bit i.e. 2-byte offset to address it.

118
Interrupts
In 8086 microprocessor following tasks are performed when
microprocessor encounters an interrupt:

[Link] value of flag register is pushed into the stack. It means that
first the value of SP (Stack Pointer) is decremented by 2 then the
value of flag register is pushed to the memory address of stack
segment.
[Link] value of starting memory address of CS (Code Segment) is
pushed into the stack.
[Link] value of IP (Instruction Pointer) is pushed into the stack.
[Link] is loaded from word location (Interrupt type) * 04.
[Link] is loaded from the next word location.
[Link] and Trap flag are reset to 0.
Types of Interrupt
Hardware Interrupts –

Hardware interrupts are those interrupts which are caused by any

peripheral device by sending a signal through a specified pin to the
microprocessor. There are two hardware interrupts in 8086
microprocessor. They are:

(A) NMI (Non Maskable Interrupt) – It is a single pin non maskable hardware interrupt
which cannot be disabled. It is the highest priority interrupt in 8086
microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt. IP
is loaded from word location 00008 H and CS is loaded from the word location
0000A H.

(B) INTR (Interrupt Request) – It provides a single interrupt request and is activated by
I/O port. This interrupt can be masked or delayed. It is a level triggered interrupt. It can
receive any interrupt type, so the value of IP and CS will change on the interrupt type
received.
Software Interrupts –
These are instructions that are inserted within the program to
generate interrupts. There are 256 software interrupts in 8086
microprocessor. The instructions are of the format INT type
where type ranges from 00 to FF. The starting address ranges
from 00000 H to 003FF H. These are 2 byte instructions. IP is
loaded from type * 04 H and CS is loaded from the next
address give by (type * 04) + 02 H.
Some important software interrupts are:
(A) TYPE 0 corresponds to division by zero(0).
(B) TYPE 1 is used for single step execution for debugging of
program.
(C) TYPE 2 represents NMI and is used in power failure
conditions.
(D) TYPE 3 represents a break-point interrupt.
(E) TYPE 4 is the overflow interrupt.
8086 Emulator for Lab Experiments
Address Generation in 8086 Emulator

Segment Base Address: offset Segment Base Address: offset

SS: SP/BP
DS: DI/SI Code segment: IP
ES:DI/SI 0100:0000
CS: IP

Physical Address= Segment base address *10H +offset

Physical address= Code Segment(CS)*10H+ IP
Physical address= 0100*10+0000
= 01000
 Architecture [2]: Physical Address Generation
• For example, if the segment address is 1005H and the offset is 5555H,
then the physical address calculated as below:

Particulars Hex Value Binary Value

Segment 1005H 0001 0000 0000 0101

Address (16 bit)
Offset Address 5555H 0101 0101 0101 0101
(16 bit)
Shifted by 4 – 10050H 0001 0000 0000 0101 0000
bits (20 bit)
Addition 0001 0000 0000 0101 0000
+ 0101 0101 0101 0101
Physical 155A5H 0001 0101 0101 1010 0101
Address (20 bit)

12
6