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I/O Organization in Computer Architecture

The document covers Input-Output Organization in computer architecture, detailing concepts such as I/O modules, programmed I/O, interrupt-driven I/O, and Direct Memory Access (DMA). It includes definitions, comparisons, and the architecture of I/O systems, highlighting the roles of various components like device controllers and I/O channels. Additionally, it discusses the types of interrupts and their handling processes, as well as the differences between memory-mapped I/O and isolated I/O.
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100% found this document useful (2 votes)
446 views9 pages

I/O Organization in Computer Architecture

The document covers Input-Output Organization in computer architecture, detailing concepts such as I/O modules, programmed I/O, interrupt-driven I/O, and Direct Memory Access (DMA). It includes definitions, comparisons, and the architecture of I/O systems, highlighting the roles of various components like device controllers and I/O channels. Additionally, it discusses the types of interrupts and their handling processes, as well as the differences between memory-mapped I/O and isolated I/O.
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

MJ-3T: Computer Architecture

Module VI: Input-Output Organization

Prepared & Guided By : Souvik Chakraborty , [Link](C.S)

2-Mark Questions (Short Answer – 20 Questions)


1. What is an I/O module?
An I/O module is a hardware unit that connects the CPU and memory with peripheral
devices, handling data transfer and control signals between them.

2. Define programmed I/O.


Programmed I/O is a data transfer method where the CPU controls all aspects of I/O
operations through software instructions without external interrupts.

3. What is interrupt-driven I/O?


In interrupt-driven I/O, the CPU is interrupted when the I/O device is ready, allowing
better CPU utilization than programmed I/O.

4. What is Direct Memory Access (DMA)?


DMA is a technique that allows I/O devices to transfer data directly to/from memory
without involving the CPU.

5. Define I/O channel.


An I/O channel is a specialized processor used for handling I/O operations independently
from the CPU.

6. What are external devices?


External devices are peripheral components like keyboards, monitors, printers, or disk
drives connected to the computer system.

7. What is the role of a device controller?


A device controller manages the interface between a system’s I/O devices and the CPU,
sending and receiving data or control signals.

8. Differentiate between input and output devices.


Input devices send data to the computer (e.g., keyboard), while output devices receive
and display data from the computer (e.g., monitor).

9. What is a control bus in I/O?


The control bus carries control signals used to manage I/O operations such as read, write,
and interrupt requests.

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10. Mention one advantage of DMA over interrupt-driven I/O.
DMA reduces CPU overhead during large data transfers by bypassing the CPU.

11. What is an interrupt vector?


An interrupt vector is a memory location or table that stores the address of an interrupt
service routine (ISR).

12. What is polling in I/O systems?


Polling is a technique where the CPU repeatedly checks the status of an I/O device to see
if it's ready for communication.

13. What is the role of an I/O interface?


An I/O interface facilitates communication between the CPU and peripheral devices.

14. Define synchronous data transfer.


Synchronous data transfer happens when data is transmitted at regular intervals,
synchronized by a clock signal.

15. Define asynchronous data transfer.


Asynchronous transfer occurs without a shared clock, using start and stop bits for
synchronization.

16. What is a buffer in I/O systems?


A buffer is a temporary memory area used to store data during I/O transfers to handle
speed mismatches.

17. Mention one function of an interrupt controller.


It prioritizes multiple interrupt requests and sends them to the CPU based on predefined
rules.

18. What is an interrupt service routine (ISR)?


ISR is a special function executed in response to an interrupt signal to handle the I/O
device.

19. Define I/O mapping.


I/O mapping is the method of assigning memory addresses to I/O devices for data access.

20. What is memory-mapped I/O?


In memory-mapped I/O, devices share the address space with memory, allowing standard
memory instructions to access I/O devices.

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5-Mark Questions (Medium Answer – 10 Questions)
1. Differentiate between programmed I/O and interrupt-driven I/O.
o Programmed I/O: CPU polls device until it's ready; inefficient for large
operations.
o Interrupt-Driven I/O: Device interrupts CPU when ready; more efficient and
allows multitasking.

| Feature | Programmed I/O | Interrupt-Driven |


|----------------|----------------|------------------|
| CPU Involvement | High | Low |
| Efficiency | Low | High |
| CPU Utilization | Poor | Better |

2. Explain the concept and working of Direct Memory Access (DMA).


DMA allows peripherals to access main memory without CPU intervention.
o Steps:
1. CPU initializes DMA controller.
2. DMA controller transfers data directly.
3. After completion, DMA signals CPU via interrupt.
o Advantage: Frees CPU for other tasks.

3. Describe the structure and function of an I/O module.


I/O modules contain:
o Control Logic: Coordinates data transfer.
o Data Register: Temporary storage.
o Status Register: Indicates device readiness.
o Address Decoder: Identifies device addresses.
They manage communication between CPU, memory, and devices.

4. Explain the role of an I/O interface in computer systems.


The I/O interface ensures compatibility between the CPU and I/O devices through:
o Signal conversion
o Handshaking
o Data buffering
o Device control (using control and status signals)

5. Describe the steps in an interrupt-driven I/O operation.


1. CPU initiates I/O operation.
2. CPU continues other tasks.
3. I/O device finishes and sends an interrupt.
4. CPU halts current task, saves context.
5. Executes ISR.
6. Resumes previous task.

6. What are the functions of an I/O channel?

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o Handles complex I/O tasks independently.
o Supports multiple I/O operations.
o Reduces CPU load.
o Performs error checking and data formatting.
o Example: Used in mainframes for parallel I/O.

7. Explain polling and its limitations.


o CPU repeatedly checks device status.
o Drawback: Wastes CPU time if device is idle.
o Suitable only for low-speed or non-critical I/O.
o Inefficient compared to interrupts or DMA.

8. Differentiate between memory-mapped I/O and isolated I/O.

Feature Memory-Mapped I/O Isolated I/O


Address Space Shared with memory Separate
Instruction Set Same as memory ops Special I/O instructions
Flexibility More flexible Limited

9. Explain synchronous vs. asynchronous data transfer.


o Synchronous: Data sent at regular intervals using a clock; faster but requires
clock matching.
o Asynchronous: Data sent with start/stop bits; more flexible but slower.

| Type | Clock | Speed | Complexity |


|-------------|-------|-------|------------|
| Synchronous | Yes | High | High |
| Async | No | Low | Low |

10. What are the types of interrupts in I/O systems?

 Hardware Interrupts: Triggered by devices (e.g., keyboard, mouse).


 Software Interrupts: Initiated by programs (e.g., system calls).
 Maskable/Non-Maskable:
o Maskable: Can be ignored.
o Non-maskable: High-priority, cannot be disabled (e.g., hardware failures).

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1. Explain Programmed I/O, Interrupt-Driven I/O, and
Direct Memory Access (DMA) with comparisons.
🔹 Programmed I/O:

 In this method, the CPU continuously checks (polls) the I/O device status until it becomes ready
for data transfer.
 It wastes CPU time because the CPU remains idle while waiting.

Diagram:

CPU → I/O Device → Memory (CPU controls all steps)

Drawbacks:

 Inefficient
 CPU is tied up with I/O task

🔹 Interrupt-Driven I/O:

 The CPU starts the I/O operation and continues with other tasks.
 When the device is ready, it sends an interrupt signal to CPU.
 The CPU pauses, handles the interrupt via an Interrupt Service Routine (ISR), and then resumes
the previous task.

Advantages:

 Better CPU utilization


 Less busy waiting

🔹 Direct Memory Access (DMA):

 DMA controller manages data transfer directly between I/O device and memory.
 CPU is involved only in initiating and completing the process.

Steps:

1. CPU sets up the DMA controller with memory address, device address, data size.
2. DMA transfers data independently.
3. On completion, it raises an interrupt.

Diagram:

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I/O Device ↔ DMA Controller ↔ Memory

CPU (only at start/end)

🔹 Comparison Table:
Feature Programmed I/O Interrupt I/O DMA

CPU Involvement High Moderate Low

Efficiency Low Moderate High

Use Case Simple peripherals Moderate data volume Large data transfers

Interrupt Usage No Yes Yes (only once complete)

2. Describe the architecture and working of an I/O module


with a diagram.
🔹 Components of I/O Module:

1. Data Register: Temporarily holds data during transfer.


2. Status/Control Register: Shows device readiness and control signals.
3. Address Decoder: Determines which device is being addressed.
4. Control Logic: Coordinates all internal module operations.
5. Interface Lines: Communicates with the device and the system bus.

Diagram:

┌────────────────────────────────────────┐
│ I/O Module │
│ ┌────────────┐ ┌────────────────────┐ │
│ │ Data Reg │ │ Control & Status │ │
│ └────────────┘ └────────────────────┘ │
│ ┌────────────┐ ┌────────────────────┐ │
│ │ Addr Dec. │ │ Control Logic │ │
│ └────────────┘ └────────────────────┘ │
└────────────────────────────────────────┘
↑↑↑↑ ↑↑↑↑
System Bus Peripheral Device

🔹 Working:

 The CPU sends address and control signals via the system bus.
 The I/O module decodes the address and checks the status.
 If ready, it performs data transfer between device and CPU/memory.

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 Supports modes like:
o Programmed I/O
o Interrupt-Driven I/O
o DMA (if enabled)

3. Explain the types of interrupts and how they are handled


in a computer system.
🔹 Types of Interrupts:

1. Hardware Interrupts:
o Generated by external hardware (e.g., keyboard, mouse).
o Example: Keypress → Signal to CPU.
2. Software Interrupts:
o Triggered by programs using instructions (e.g., INT in x86).
o Used for system calls, exceptions.
3. Maskable Interrupts:
o Can be ignored/disabled by the CPU.
o Useful for non-critical devices.
4. Non-Maskable Interrupts (NMI):
o Cannot be ignored.
o Used for critical errors like hardware failures.

🔹 Interrupt Handling Process:

1. Device sends an interrupt request (IRQ) to the CPU.


2. CPU finishes current instruction.
3. CPU saves current context (PC, registers).
4. CPU identifies the interrupt vector (address of ISR).
5. Executes Interrupt Service Routine (ISR).
6. Restores saved state and resumes interrupted task.

Diagram:

Device Ready → IRQ → CPU → Save Context → ISR → Restore Context → Resume

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4. Compare memory-mapped I/O and isolated I/O with
examples.
Feature Memory-Mapped I/O Isolated I/O (Port-Mapped)

Address Space Shares memory address space Separate I/O address space

Access Method Uses standard memory instructions Uses special I/O instructions (e.g., IN, OUT)

Number of Instructions Fewer (reuses memory instructions) More (additional I/O instructions)

Speed Faster, simpler programming Slightly slower

Example Instruction MOV AL, [PORT_ADDR] IN AL, 60h

Complexity Low High

🔹 Example:

 Memory-Mapped I/O:
Device at address 0xFFFF
CPU: MOV A, [0xFFFF]
 Isolated I/O:
Device port 60h
CPU: IN AL, 60h

5. Explain the role and architecture of an I/O channel. How


does it enhance system performance?
🔹 I/O Channel:

 A dedicated processor that offloads I/O responsibilities from the main CPU.
 Used in high-performance systems (e.g., mainframes).

🔹 Types:

1. Selector Channel:
o Handles one device at a time.
o Fast and simple.
2. Multiplexer Channel:
o Can handle multiple slower devices simultaneously.
3. Block Multiplexer Channel:
o Switches between devices for block-level I/O.

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🔹 Architecture:

CPU ←→ Main Memory


↑ ↑
| |
↓ ↓
I/O Channel ←→ I/O Devices

 I/O channel acts as an intermediary.


 It handles device commands, data transfer, and error handling.

🔹 Benefits:

 Reduces CPU burden


 Allows overlapping of computation and I/O
 Enables parallelism in I/O operations
 Better throughput and responsiveness

XXXXX END XXXXX

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Common questions

Powered by AI

An interrupt vector is a system mechanism used to direct the CPU to the appropriate interrupt service routine (ISR) based on the interrupt request received. It allows for organized handling of multiple interrupts by storing addresses of ISRs at predefined locations in memory. When an interrupt occurs, the CPU uses the vector to quickly locate and execute the correct ISR, enabling efficient prioritization and resolution of multiple simultaneous events without confusion or error, enhancing system responsiveness .

An interrupt service routine (ISR) is executed in response to an interrupt signal to manage I/O events. Functions of an ISR include saving the current CPU context, handling the specific I/O device requirements (such as reading or writing data), clearing the interrupt flag, and finally restoring the CPU's context to resume interrupted tasks seamlessly. This structure ensures the efficient management of interrupts without significant disruption to CPU operations .

Synchronous data transfers rely on a shared clock signal to coordinate timing, resulting in faster data transmission but requiring precise clock synchronization, which can increase complexity. Conversely, asynchronous transfers do not share a clock; they instead use start and stop bits for synchronization, offering more flexibility and simpler implementation but generally slower data transfer rates due to the additional overhead of these control bits .

Interrupt-driven I/O is more efficient than programmed I/O as it allows the CPU to focus on executing other tasks instead of waiting for I/O device readiness. The CPU is only interrupted upon completion of an I/O task, substantially improving overall CPU utilization and reducing idle times compared to programmed I/O, which involves continuous polling and CPU involvement .

An I/O channel is a dedicated processor that offloads I/O tasks from the main CPU, used in high-performance environments. It handles device commands, data transfer, and error management, functioning as an intermediary between the CPU, main memory, and peripheral devices. This delegation allows parallel processing of computation and I/O tasks, reduces the CPU’s workload, and improves overall system throughput and responsiveness by enabling concurrent operations .

Polling is a method where the CPU continuously checks the status of an I/O device to determine readiness for data transfer, which can lead to inefficient use of CPU resources as it spends time actively waiting. Compared to interrupt-driven I/O, which allows the CPU to perform other tasks until interrupted by a device, and DMA, which transfers data without CPU involvement, polling is less efficient and wastes CPU cycles, making it suitable only for non-critical or low-speed I/O applications .

Memory-mapped I/O shares the address space with memory, allowing the use of standard memory instructions for data access, which can simplify programming and result in faster operation. In contrast, isolated I/O uses a separate address space for I/O devices and requires special I/O instructions such as IN and OUT, making the instruction set more complex but providing clear separation between memory and I/O operations .

An interrupt controller manages multiple interrupt requests by prioritizing them according to predefined rules, ensuring higher priority interrupts are handled before lower ones. It also resolves conflicts and determines which interrupt should be sent to the CPU first. This is crucial for maintaining system stability, preventing data loss, and ensuring timely responses to important events, particularly in environments with numerous and diverse peripheral devices generating interrupts .

Direct Memory Access (DMA) allows peripherals to access main memory directly without continuous CPU intervention, resulting in higher efficiency by freeing up CPU resources for other tasks. In contrast, interrupt-driven I/O still involves the CPU to handle each interrupt, although it is more efficient than programmed I/O as it allows the CPU to execute other instructions while waiting for an I/O operation to complete. This means DMA typically requires less CPU involvement compared to interrupt-driven I/O, where the CPU must actively respond to each interrupt with an ISR .

Buffers act as temporary storage areas that accommodate data during I/O transfers, smoothing out the speed discrepancies between fast components like CPUs and slower peripheral devices. By doing so, buffers prevent data bottlenecks and allow faster components to continue operating without waiting for slower counterparts to catch up, leading to more efficient data processing and system performance .

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