High Level Language --> Assembly Language --> Machine Language
Fetch Decode Execute Cycle
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Von Neumann Architecture: Uses same memory for program and Data
8085: Microprocessor
8051: Microcontroller
8085: 8-Bit processor, can address 64KBytes of memory, 40 Pins, +5v for Power, Max
frequency = 3MHz
6 Pin Groups:
a.) Address Bus (16 Bit Unidirectional) {16 Bit as per 64KB Ext. Memory}
b.) Data Bus (8 Bit Bidirectional)
c.) Control and Status signals
d.) Power Supply and Frequency
e.) Externally Initiated Signals
f.) Serial IO Ports
AD0-AD7: Address and Data Pins Multiplexed
8085 has 6 registers: B,C,D,E,H,L
Apart from these has one Accumulator(A), one Flag Register (8-Bit), Stack Pointer
(16-Bit), PC (16-Bit)
To use Register Indirect Mode, we need pair of two registers since each register is
individually 8 Bit: Allowed Pairs are BC,DE,HL. By default the pair used is HL
{H=High, L=Low}
5 Condition Bits in the Flag Register:
a.) Sign(S)
b.) Zero(Z)
c.) Auxiliary Carry(AC)
d.) Parity(P)
e.) Carry(CY)
Memory Addressing: Of two types:
a.) Direct: Memory Add. like 2050H directly given in instruction
b.) Indirect: HL pair (Memory Pointer register) used
Input Output Addressing: 8-Bit address of port is specified in instruction:
Read/Write from that
Types of Instruction according to size:
a.) 1-Byte Instruction: Opcode, Operand in Same byte
b.) 2-Byte Instruction: 1st Byte: Opcode, 2nd Byte: Operand
c.) 3-Byte Instruction: 1st Byte: Opcode, 2nd & 3rd Byte: Operand
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8051: 4KB internal ROM (Code), 128 Bytes internal RAM (Data)
64KB external Code memory (Only Read via PSEN) and 64KB external data memory
(Read,write by RD,WR)
EA_Bar = 0 i.e. EA = 1 => External Code Memory (0-64K)
EA_Bar = 1 i.e. EA = 0 => External (4K-64K) + Internal Code Memory (0-4K)(ROM)
External Memory can be both Data and Code memory
Bit Address Max = F7h
Bit Address:
20h-2Fh Bytes are bit addressable
Thus Bit Address 00h - 7Fh correspond to 20.0 and 2F.7
After this, bit address 80h corresponds to 80.0 (LSB of 80h SFR)
SFR which are not Bit Addressable:
TMOD,TL0,TL1,TH0,TH1,PCON,DPH,DPL,SP
SFRs and Upper 128 Bytes of RAM share the same address, to differentiate:
Upper 128 Bytes of RAM: Indirect Addressing only
SFRs: Direct Addressing only
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Addressing Modes:
a.) Register
b.) Memory Direct
c.) Memory Indirect
d.) Immediate
e.) Relative (SJMP)
f.) Absolute (AJMP)
g.) Long (LJMP)
h.) Indexed: Base (DPTR/PC) + Offest (Acc)
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Endianess:
Little Endian: MSB of Data in higher address [2007h => Address 31h will have 20 and
30h will have 07]
Big Endian: MSB of Data in lower address [2007h => Address 30h will have 20 and 31h
will have 07]
ASCII: A = 41h a=61h
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Von Neumann Architecture: Common Bus for Data, Instruction
Harvard Architecture: Separate Data, Code memory. Expensive since two buses.
Instruction bus may remain idle. Traffic not balanced
Modified Harvard Architecture: Constants stored with instructions in ROM. Traffic
is balanced better. 2 Memory operations per bus. (1 Instruction Read, 1 Constant
Read, 1 Data Read, 1 result write per instruction)
Fetch, MOVC can access external ROM (External Code Memory)
MOVX can access external RAM (External Data Memory)
Stack Pointer is initialized to 07 at power on
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Overflow Flag: For addition/subtraction 60H+70H = D0H has MSB = 1 and thus treated
as -ve, to indicate this OV flag will be set (i.e. wrong sign due to operation)
For multiplication OV is set if result is >255 and the upper byte is placed in B
For division OV is set if division by 0 is done
Carry Flag can be accessed by C
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Push: Pre-Increment SP; Write to address pointed by SP
Pop: Post-Decrement SP; Extract value from address pointed by SP
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MOVX A,@Ri => Upper byte using Port commands, lower byte using Ri
INC,DEC: No Flag affected
DPTR: Only INC no DEC
DA: ADD 6 to nibble if it is >9 or generated carry during addition:
i.e. ADD 6 to Upper Nibble if it is >9 or C = 1
ADD 6 to Lower Nibble if it is >9 or AC = 1
DIV AB: Puts Quotient in A and Remainder in B
CALL instr: Pushes PC to Stack (Lower Byte first)
RET: Pops (Higher Byte first) and copies to PC
RETI works just like RET, accept that it also restores interrupt
enable values to their original settings.
(Interrupts may be automatically disabled based on their priority
levels while an interrupt handler runs. These need to be
re-enabled when the handler terminates.)
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P0 Will write the value of AND of P0_PIN_OLD_VALUE and P0_LATCH_NEW_VALUE
i.e P0_PIN_NEW_VALUE = P0_PIN_OLD_VALUE AND P0_LATCH_NEW_VALUE
However P1,P2,P3 will write the same value as the latch value
i.e. P1_PIN_NEW_VALUE = P1_LATCH_NEW_VALUE | P2_PIN_NEW_VALUE = P2_LATCH_NEW_VALUE
| P3_PIN_NEW_VALUE = P3_LATCH_NEW_VALUE