Syllabus of 2nd Semester, 2025

COMPUTER ARCHITECT
Course Title Course Code EE3500614 Section 057
URE
Electronics Engineerin Credit-Theory
Department Level 3rd year 3.0 - 3.0 - 0.0
g Major - Practice
Class Hours &
Tue 09:00(75) 107-8403, Thu 09:00(75) 107-8403
Classroom
Office 406, 8th Engineering Buil
Counsel Hours 1:00-2:45, Tue & Thu
Fitzgerald Sungkyung Par (Counsel room) ding
Lecturer
k
Telephone +82|051-510-2368 E-mail fspark@[Link]

ㆍ대면
Lesson ㆍTeacher-centered learning, ETC(Online material is utilized.)
Style

Mid-term exam + final exam = 85% (final exam may have a higher weighting factor), attendance
Evaluation (attitude with lateness penalty) + pop quiz(zes) & Q&A with homeworks = 15%, but these are subject to
Method change without notice at the lecturer's discretion.
* Students with disabilities can request an extension of the exam hour, and they can take exams by
getting writing assistance or by using a computer.

Competitors Logic circuits (2nd year)

and Knowledge (Digital System Design (3rd year) will be of help.)

1. To have a solid understanding of the organization and the architecture of computer systems
2. To have a sound understanding of each component in a computer system, including memory, CPU, I/
O, instruction set architecture, and system software
Objective 3. To learn how to improve the performance and reduce the complexity of computer systems through p
ipelining and parallelism
4. To grasp the basics of register transfer level (RTL) representations with Verilog hardware description
language (HDL)
The new decade from around 2020 has opened up a golden age of computer architecture and system
on a chip (SoC) which is evolving into heterogeneous chiplet integration for reaching beyond the
traditional Moore's law.
Recently, a family of microprocessors has been blooming in an open-source fashion, similar as Linux is
in the operating system domain.
Microprocessor (which includes a central processing unit or CPU) is a component that can execute a set
of instructions (which is a low-level software to which a program in a high-level language like C is
compiled via an assembly language).
This course will give a solid understanding on the essentials of the architecture and the organization of
computer systems which comprise one or more central processing units (CPUs), on-chip memories (e.g.,
caches and scratchpad memories mainly in SRAM technology), off-chip memory (e.g., main memory in
DRAM technology), basic input-output peripherals (IOPs), and so on.
Lecture The CPU is subdivided into the datapath and the control unit (or the control path).
Overview The course will deal with key performance measures of computer systems, pipelining and parallelism,
the instruction set architecture (or the ISA which serves as a bridge between the CPU hardware and
software), the assembly language, the software stack, memory hierarchy, cache memory, basic I/O
peripheral, and more.
You will learn that various tradeoffs basically exist between performance (or speed) and complexity of
every computer system or each building block in it.
(cf. The topic of AMBA buses & on-chip interconnects will be dealt with in another course
"Introduction to SoC Design" presented in the same semester, namely, in the 3rd year.)
* Students with disabilities can negotiate with the Disabled Student's Academic Support Center regarding
course materials and assignments.
 Course and Core competencies

Explore new
BNU Globalize ourvision Respect partners Accelerate innovation Transform the frame
knowledge
8Point Core
Competency O O O O

Core competencies according to subject matter

Department Core Competencies Training Method

Innovative engineering capability

The capability to view problems in the academic and i Solid understanding and treatment of logic and
04 ndustrial fields of electronic engineering from a new p hardware concepts in the context of clocking
erspective and suggest creative and challenging alternat and timing
ives
Enabling the students to properly assess and e
Creative problem-solving capability
valuate various computer systems in considera
05 The capability to learn knowledge from various academ
tion of tradeoffs between performance and co
ic disciplines to solve problems creatively
mplexity

Textbooks and References

Behrooz Parhami,『Computer Architecture : From Microprocessors to Supercomputers』

1 주교재
-Oxford University Press(2005)
Patterson, David A.,『Computer Organization and Design : The Hardware/software Inter
Linked 2 부교재
face』-Morgan Kaufmann Publishers In(2008)

3 부교재 M. Morris Mano,『Logic and Computer Design Fundamentals』-Prentice Hall(2008)

(주교재) Computer Architecture (Parhami)

(부교재1) Some online materials
Direct
(부교재2) Computer Organization and Design (Patterson)
(부교재3) Logic and Computer Design Fundamentals (Mano)
 Week Lecture Plan

Week Lesson and Lab Contents Challenges and Other Notes

[Orientation and Education on Academic Misbehavior(e.g

. Cheating, Plagiarism) and Safety Education on Experi Schedule is subject to change.
ment and Practice] Introduction to digital computer syst Pop quizzes and Q&A may appear during the
1 Week
ems course.
Computer system technology & computer performance Homework may be given during the course.
(MIPS, execution time, and more)
Supplementary training (for the theory taught
in class) can be carried out personally or spo
ntaneously in the computer room of the electr
onics engineering department (located in room
2 Week Instructions & addressing
s 8310 & 8311 in the 8th engineering building
).
Instruction set architecture (ISA) is the key to
pic in week 2.

3 Week Procedures & data Software stack explanation

Interpretation of assembly programs

Assembly language programs Toolchain (consisting of compiler, assembler, li
4 Week
(Basic S/W for processor) nker, loader, debugger, library archive, instruc
tion set simulator or ISS, and more)

5 Week Instruction set variations RISC vs. CISC comparison

MIPS ISA
6 Week Instruction set variations (cont'd)
RISC-V ISA (as an open-source architecture)
Instruction fetch, instruction decoding, instructi
on execution, memory access, and write back
to the register file or RF
7 Week Instruction execution steps
H/W components of the datapath - ALU, regis
ter file (RF), & multiplexers
Single-cycle processor architecture
Main contents that will be taught prior to the
mid-term exam will be software (ISA, assembl
y instructions, etc.) whereas those after the m
8 Week Mid-term exam
id-term exam will be hardware (CPU's datapat
h & control unit, pipeline stages, cache memo
ry, main memory, I/O, etc.)
Control unit design is based on the finite-stat
9 Week Control unit synthesis e machine (FSM).
Multicycle processor architecture
Concept of pipelining, pipelining examples, and
10 Week Pipelined data paths
the 5-stage pipelined processor architecture

11 Week Pipelined data paths (cont'd) MIPS processor analysis

How to deal with or circumvent hazards (such

as RAW hazard or read-after-write hazard) -
12 Week Pipeline performance limits
Use of stall or bubble, bypass path (or forwar
ding path), and so forth.
Need for memory hierarchy
13 Week Cache Basics of the cache memory
SRAM based on-chip memory
Cache structures - direct mapped cache, set-
associative cache, & fully associative cache
14 Week Cache (cont'd)
Cache replacement & write policies
Cache hit & miss example analysis
15 Week DRAM as (off-chip) main memory
(Appointed Main memory concepts & I/O programming Basic I/O operations at the assembly language
make-up class
week) level
 Week Lecture Plan

Week Lesson and Lab Contents Challenges and Other Notes

Students had better do some self-study on op

erating systems (& compilers) (which actually l
16 Week Final exam ie under the computer engineering department
's curriculum) for full coverage of the comput
er arhictecture topics.