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High-Performance Low-Power SRAM Decoder

This document details the design and evaluation of mixed-logic address decoders for SRAM arrays using TSMC 28nm CMOS technology, focusing on a hybrid approach that combines pass-transistor logic and CMOS inverters. The results demonstrate significant improvements in propagation delay, power dissipation, and transistor count compared to traditional CMOS decoders. The methodology is scalable and applicable for ultra-low-power VLSI systems.

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Chiranjeevi varma P
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8 views2 pages

High-Performance Low-Power SRAM Decoder

This document details the design and evaluation of mixed-logic address decoders for SRAM arrays using TSMC 28nm CMOS technology, focusing on a hybrid approach that combines pass-transistor logic and CMOS inverters. The results demonstrate significant improvements in propagation delay, power dissipation, and transistor count compared to traditional CMOS decoders. The methodology is scalable and applicable for ultra-low-power VLSI systems.

Uploaded by

Chiranjeevi varma P
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

gn and Implementation of a High-Performance Low-Power Static Decoder for S

Authors: Donghao Xia, Yuanxin Tian, Mengfan Xu, Yuejun Zhang, Liang Wen

Institution: [Insert your Institution Name Here]

Date: June 13, 2025

Abstract
This project presents the design and evaluation of mixed-logic address decoders for SRAM arrays

using TSMC 28nm CMOS technology. It proposes a hybrid approach combining pass-transistor

logic (PTL) and CMOS inverters to reduce power consumption, delay, and transistor count.

Hierarchical decoders (2-4, 3-8, 4-16, 5-32) were built in Verilog, simulated using Cadence Spectre,

and validated with Monte Carlo analysis.

Tools and Technology


- Technology Node: TSMC 28nm CMOS

- Simulation Tool: Cadence Spectre

- Layout Tool: Cadence Virtuoso

- SPICE Model: BSIM4 (TT, SS, FF corners)

- Transistor Specs: Wn/Wp = 100nm, Ln/Lp = 30nm

Methodology
1. Designed PTL-based AND and NAND gates with full swing.

2. Built hierarchical decoders using 2-4 and 3-8 blocks.

3. Verified using RTL simulation and transient SPICE analysis.

4. Performed Monte Carlo simulation (2000 samples).

5. Compared results against traditional CMOS decoders.

Results Summary
- Propagation Delay Improvement: Up to 34%

- Power Dissipation Reduction: Up to 11%


- Power-Delay Product (PDP): Up to 60% improvement

- Transistor Count Reduction: >14% across all decoder sizes

Simulation Flow in Cadence Virtuoso


1. Load the TSMC 28nm PDK and create project libraries.

2. Design PTL logic gates and create symbols for reuse.

3. Build hierarchical decoders in schematic editor.

4. Run ADE-L/XL simulations with transient and Monte Carlo analysis.

5. Use Direct Plot and Calculator to measure delay and power.

Conclusion
Mixed-logic decoder designs combining PTL and CMOS offer significant improvements in

performance and efficiency for SRAM applications. The methodology is scalable and suitable for

ultra-low-power VLSI systems.

References
[1] Turi, M., et al. "Low-power address decoders using selective precharge." IEEE JSSC, 2018.

[2] Changkun, S., et al. "Transient current limiting NMOS decoder design." IEEE Trans. Circuits

Syst., 2020.

[3] Kumar, V., et al. "Dynamic style tree decoder for low-power SRAM." Microelectronics Journal,

2021.

[4] Kang, S.-M. & Leblebici, Y. CMOS Digital Integrated Circuits, McGraw-Hill, 2014.

[5] Rabaey, J., et al. Digital Integrated Circuits, Pearson, 2003.

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