5888 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 21, NO.

8, AUGUST 2025

Enhanced Protection Algorithm for

Zonal DC Microgrids
Arya Arun Sondoule , Student Member, IEEE, Premalata Jena , Senior Member, IEEE,
and Narayana Prasad Padhy , Senior Member, IEEE

Abstract—Conventional protection methods are con- solar photovoltaic arrays and wind energy conversion systems,
strained for effectively identifying and classifying faults enabling the transition to a more sustainable and environmen-
within dc microgrid setups because of the integration of di- tally friendly energy infrastructure [2]. DC microgrids have a
verse power electronic-based generators and dc loads. For
dc microgrids configured in zonal topology with bidirec- broad range of potential applications, which makes them ideal
tional power flow, designing effective protection becomes for a wide spectrum of applications in the commercial, industrial,
even more complex. Ensuring reliable power supply to con- and residential domains [3].
sumers while preventing the unnecessary disconnection While dc microgrids offer many advantages, their widespread
of renewable resources underscores the importance of se-
adoption faces key challenges that must be addressed to en-
lectivity in protection schemes. Addressing this challenge
requires advanced, intelligent fault detection schemes. This sure reliable and safe operation. The absence of natural zero-
article proposes a high-speed fault identification algorithm crossings in dc waveforms complicates fault detection and isola-
built upon the current derivative signals at both line termi- tion, requiring robust protection schemes to prevent disturbances
nals. Upon fault detection, the type of fault is determined by and equipment damage [4]. In addition, short circuits in dc
the current derivative characteristics on the positive and microgrids can cause rapid fault current increases due to dc
negative poles of either side of a line. MATLAB/Simulink
simulations of a zonal dc microgrid with various gener- bus capacitor-discharge, posing significant risks if not quickly
ating units and loads validate the developed algorithm, isolated [5]. Therefore, effective fault identification and isola-
considering a range of fault conditions, including internal, tion are essential for maintaining system integrity and safety,
external, high-resistance, and noisy conditions. Simulation requiring robust protection measures to ensure reliability and
results demonstrate the ability of the technique to seg- stability.
regate internal and external faults and accurately classify
them. Furthermore, the suggested scheme is evaluated on
a hardware testbed, confirming its efficacy in real-world dc
microgrid applications. A. Literature Review
Index Terms—DC microgrid, fault classification, fault de- Safeguarding against short-circuit faults presents a pivotal
tection, microgrid protection, zonal dc microgrid. hurdle for the extensive adoption of dc microgrids. To tackle this
obstacle, the authors in [6] and [7] introduce current derivative-
based protection methods for low-impedance faults in dc micro-
I. INTRODUCTION
grids. However, these methods struggle to distinguish between
C MICROGRIDS provide a simpler, more efficient, and high-resistance faults and substantial load fluctuations. Baran
D reliable approach to power distribution than traditional ac
microgrids by minimizing energy conversion stages and reduc-
and Mahajan [8] implemented an overcurrent-based protection
method for rapid fault detection in low-voltage dc distribution
ing line losses [1]. The modular nature of dc microgrids allows systems. However, this approach may cause extended fault clear-
for easier integration of renewable sources of energy, including ance times or unnecessary disconnections of larger sections of
the network in complex dc microgrids.
Received 19 November 2024; revised 7 February 2025; accepted 20 Polarity-based protection techniques are presented in [9],
March 2025. Date of publication 1 May 2025; date of current version [10], [11], and [12]. In [9], voltage polarity at one cable end
9 July 2025. This work was supported by the Department of Science
and Technology, Goverment of India, under Grant SER-1801-EED and is utilized for fault detection and classification, while Sharma
Grant SER-1851-EED. Paper no. TII-24-6098. (Corresponding author: et al. [10] employed transient power polarity at both ends to
Premalata Jena.) identify faults. However, selecting optimal time windows for
Arya Arun Sondoule is with the Department of Electrical Engineering,
Indian Institute of Technology Roorkee, Roorkee 247667, India (e-mail: sampling presents challenges in balancing threshold levels and
aa_sondoule@[Link]). detection speed. A current-based fault detection algorithm is
Premalata Jena is with the Department of Electrical Engineering and introduced in [11], which identifies faults by monitoring and
Center for Sustainable Energy, Indian Institute of Technology Roorkee,
Roorkee 247667, India (e-mail: [Link]@[Link]). analyzing current behavior at line terminals using intelligent
Narayana Prasad Padhy is with the Department of Electrical Engineer- electronic devices (IEDs). Rao and Jena [12] proposed a protec-
ing, Indian Institute of Technology Roorkee, Roorkee 247667, India, and tion method that extracts voltage, current, and current derivatives
also with the Malaviya National Institute of Technology Jaipur, Jaipur
302017, India (e-mail: nppadhy@[Link]). at both cable terminals and compares the signs of estimated resis-
Digital Object Identifier 10.1109/TII.2025.3556028 tance at both ends to differentiate faulted segments. This method
1941-0050 © 2025 IEEE. All rights reserved, including rights for text and data mining, and training of artificial intelligence and similar technologies.
Personal use is permitted, but republication/redistribution requires IEEE permission. See [Link]
for more information.

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 SONDOULE et al.: ENHANCED PROTECTION ALGORITHM FOR ZONAL DC MICROGRIDS 5889

requires numerous variables and a robust communication system

and may fail if high-impedance faults coincide with constant
power loads, as terminal signs could remain unchanged.
In addition to [12], the authors in [13] and [14] presented
resistance-based dc microgrid protection schemes. Rao and Jena
[13] suggested a fault identification algorithm for low-voltage
dc microgrids based on resistance, striving to measure both the
overall line resistance and the line resistance till the fault point.
However, its accuracy may be impacted by noise in voltage
and current signals. Yadav and Tummuru [14] outlined another
resistance-based fault identification technique for dc microgrid
systems. However, this scheme is limited by its inability to
distinguish high-resistance faults from sudden load changes.
In addition to [9], Bhargav et al. [15] employed an external
reactor. By utilizing the voltage across the external reactor
and monitoring the grounding resistor current at the relay, this
scheme identifies faults in the dc microgrid through an itera- Fig. 1. Eight bus zonal dc microgrid.
tive process. However, during high-resistance faults, both of
these parameters do not cross the threshold. Multiparameter-
based fault detection schemes are proposed in [16] and [17]. C. Contributions
Sondoule et al. [16] utilized the derivatives of circuit vari-
The key contributions of this article are outlined as follows:
ables, such as current, voltage, and resistance, whereas Ab-
1) This method achieves 200% effectiveness compared to
dali et al. [17] employed a multiple-criterion approach that
single-sided current derivative-based techniques and of-
necessitates a large database, resulting in longer fault detection
fers greater reliability than polarity-based schemes rely-
times.
ing on current derivatives.
2) It requires minimal computation time for fault identifi-
B. Research Gaps and Motivation cation and classification and reliably detects faults with
resistances up to 50 Ω, outperforming many existing
Most protection algorithms struggle with high-resistance and
techniques.
close-in fault detection in zonal dc microgrids. Particularly, ex-
3) It shows strong noise resilience, as summing current
isting current derivative (di/dt)-based protection methods often
derivative signals from both ends cancels out much of
struggle in events of high-resistance faults and load variations,
the noise component, improving its effectiveness in fault
reducing reliability under varying load conditions. While some
detection.
protection algorithms perform well in simpler dc microgrid
4) It effectively identifies close-in faults in dc microgrids, a
setups, they may cause delays or unnecessary disconnections
scenario where numerous existing methods often fail.
in more complex configurations, such as zonal topologies with
The rest of this article is organized as follows: Section II
bidirectional power flow. These limitations, especially in noisy
outlines the configuration of the zonal dc microgrid. Section III
or high-impedance environments, underscore the need for im-
contains the suggested protection technique and its correspond-
proved fault detection methods to enhance dc microgrid protec-
ing flowchart. Section IV showcases simulation outcomes, com-
tion reliability and efficiency.
parison with existing techniques, and hardware experimental
Hence, this article suggests a technique for fault identification
verification. Finally, Section V concludes this article.
and classification in dc microgrids through current derivative
analysis. The fault detection process involves utilizing the di/dt
II. ZONAL DC MICROGRID SYSTEM CONFIGURATION
signals at the terminals of the lines in the dc microgrid. During
external faults or load-switching events on the microgrid, the An eight-bus, 1200 V [10], bipolar zonal dc microgrid is em-
sum of di/dt signals from both ends of the line tends to approach ulated in MATLAB/Simulink software to validate the presented
zero. However, this scenario differs for internal faults. While protection technique, as depicted in Fig. 1. This setup incorpo-
higher fault resistance reduces variation in current and di/dt rates two zones inside the zonal dc microgrid, with various load
characteristics of IEDs on a faulted line, using the sum of types and battery energy storage systems (BESSs). Each zone
di/dt signals from both ends as a trigger significantly improves is linked to two redundant dc buses, as illustrated in Fig. 1. The
high-resistance fault tolerance. zonal dc microgrid is linked with multiple distributed generators,
To enhance the credibility of the suggested technique, fault such as PV systems, and energy storage units. Boost converters
classification is also performed using the sum of di/dt character- with perturb and observe maximum power point tracking tech-
istics at both poles of each line end: if this sum exceeds either nique are used with the PV units, and bidirectional converters
pole’s individual di/dt signal, then the fault is classified as line- are used with the BESS units for efficient energy management.
to-ground; otherwise, as line-to-line. The suggested technique Differential mode passive electromagnetic interference (EMI)
is validated using a zonal dc microgrid system. filters are used at both the PV and BESS units to mitigate

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 5890 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 21, NO. 8, AUGUST 2025

TABLE I
ZONAL DC MICROGRID SYSTEM DATA

Fig. 3. DC two-bus circuit experiencing a line-to-ground fault.

Fig. 4. DC two-bus circuit experiencing a line-to-line fault.

Fig. 3, is used
 di dia dib
= + . (1)
dt dt dt
Fig. 3 illustrates a two-bus equivalent circuit in the event
of a line-to-ground fault, comprising two voltage sources with
Fig. 2. IED connectivity layout in the zonal dc microgrid. line-to-ground voltages Valg at bus-a and Vblg at bus-b. These
voltages generate fault currents ia and ib , respectively. The two
line-to-ground voltages are expressed as follows:
high-frequency noise. Also, voltage source converters (VSCs) dia
at bus-1 and bus-4 connect the dc microgrid to the conventional valg = ia mR + mL + (ia + ib )Rf (2)
dt
ac grid, enhancing overall dependability.
The grid VSCs and BESS bidirectional converters operate dib
vblg = ib (1 − m)R + (1 − m)L + (ia + ib )Rf (3)
in voltage regulation mode [13], maintaining a system voltage dt
of 1200 V. The droop control strategy is applied for managing where R represents the dc line resistance, L signifies the dc line
the load-sharing among multiple energy sources. IEC 61850 inductance, and m denotes the distance between fault point and
communication guidelines are used for local communication bus-a. The voltage drop along line ab can be obtained using (2)
between the various units in the microgrid. A bipolar solid and (3)
grounding with terra neutral (TN) configuration is employed
to enhance service continuity. Line current measurements are dia dib
valg −vblg = ia mR+mL −ib (1 − m)R−(1−m)L .
conducted using LA25P-13022 current sensors. System data of dt dt
the eight-bus dc zonal microgrid are outlined in Table I. (4)
IEDs with solid-state circuit breakers (SSCBs) are installed For a line-to-line fault, the corresponding equivalent circuit is
at both line ends for fault protection. Fig. 2 illustrates the illustrated in Fig. 4. Here, the voltages at bus-a and bus-b are
connectivity layout of the IED utilized in this study. Each IED expressed as follows:
receives current data from a current sensor linked to one line
terminal and via advanced communication infrastructure from dia
vall = 2ia mR + 2mL + (ia + ib )Rf (5)
the other end. Upon receiving the data, the IEDs process it and dt
transmit the command signal to the SSCBs. dib
vbll = 2ib (1 − m)R + 2(1 − m)L + (ia + ib )Rf . (6)
dt
III. PROPOSED PROTECTION ALGORITHM From (5) and (6), the voltage drop in line ab during a line-to-line
fault can be written as
A. Fault Detection
dia
Fault detection in a dc line is achieved by deploying
 di sensors vall − vbll = 2ia mR + 2mL − 2ib (1 − m)R
at both line terminals. These sensors monitor the dt
dt signal,
which serves as a diagnostic indicator for fault conditions. To dib
− 2(1 − m)L . (7)
compute this signal, a two-bus equivalent circuit, as shown in dt

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 SONDOULE et al.: ENHANCED PROTECTION ALGORITHM FOR ZONAL DC MICROGRIDS 5891

Fig. 6. Current behavior in dc two-bus circuit experiencing a line-to-line

Fig. 5. Current behavior in dc two-bus circuit experiencing a line-to- fault.
ground fault.

By using (12) and (13), the relation between di/dt signals at the
Equation (7) can be rewritten in terms of line-to-ground voltages IEDs on the positive and negative poles of bus-a of the faulted
as line can be derived as
dia diap dian
vall − vbll = 2ia mR + 2mL − 2ib (1 − m)R > (14)
dt dt dt
dib Hence, for a line-to-ground fault on either pole of the line ab,
− 2(1 − m)L (8)
dt the following relation holds true
 diapn  
To generalize for both fault types, the equations for line-to- diap dian
ground faults (4) and line-to-line faults (8) are combined to > ∨ (15)
dt dt dt
derive the following generalized equation:
where
valg − vblg = ia mR + mL
dia
− ib (1 − m)R  diapn diap dian
dt = + . (16)
dt dt dt
dib
− (1 − m)L (9) Fig. 6 depicts the two-bus equivalent circuit featuring the
dt positive and negative poles for a line-to-line fault. In this con-
 di
Hence, dt for both line-to-ground faults and line-to-line faults dition, the fault current passes through both the poles; hence,
can be derived from (1) and (9) as follows: the currents passing through the positive pole and the negative
pole of line ab during a line-to-line fault as seen by bus-a are
 di valg − vblg − (ia + ib )mR + ib R + L di b

= dt
(10) expressed as
dt mL
 di iap = −ian (17)
Now, by substituting di b
dt from (3) into (10), dt is computed
as Using (12) and (17), the relationship of di/dt signals observed
 di   by the IEDs at the positive pole and the negative pole of bus-a
1 valg vblg (ia +ib )Rf of the faulted line can be derived as
= + − (ia + ib )R−
dt L m 1−m m(1 − m) diap dian
(11) =− (18)
dt dt
 di
When dt surpasses the threshold (ζ), an internal fault is
Therefore, for a line-to-line fault on line ab, by using (16) and
detected, triggering a trip signal to the SSCBs. (18), the following relation is derived:
 diapn  di dian 
ap
B. Fault Classification < ∨ (19)
dt dt dt
Fault classification distinguishes between line-to-ground and  diapn
Since dt will be approximately zero.
line-to-line faults. Fig. 5 shows the two-bus equivalent circuit, Using (15) and (19), the fault is classified as either an unsym-
including the positive and negative poles, for a line-to-ground metric line-to-ground fault or a symmetric line-to-line fault. If
fault scenario.  diapn
dt at a bus exceeds the di/dt characteristics of its positive
By backward finite approximation [18] or negative pole, then a triggering signal is generated, indicating
di i(t + Δt) − i(t) Δi a line-to-ground fault; otherwise, the fault is classified as a
= lim = (12) line-to-line fault.
dt Δt→0 Δt Δt
During a line-to-ground fault, the current passing through the
C. Flowchart
faulty pole of the line (positive in Fig. 5) significantly exceeds the
current passing through the nonfaulted pole of the line (negative Fig. 7 shows the flowchart of the suggested technique. First,
in Fig. 5), leading to the following expression for a fault at the the IEDs on a line measure currents
 di from each terminal. Sub-
di
positive pole of line ab: sequently, the IEDs calculate dt using (11). When the dt
signal for a line exceeds the threshold, the suggested algorithm
iap > ian (13) identifies an internal fault and triggers the fault classification

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 5892 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 21, NO. 8, AUGUST 2025


Fig. 8. di/dt for variations in fault locations and loading conditions.

Fig. 7. Flowchart of the suggested protection algorithm.

 di
Fig. 9. Line-to-ground fault on line 23. (a) Current. (b) di/dt. (c) dt .
 di
(d) di/dt: both poles. (e) dt : both poles of bus-2. (f) Trip and classifier
signals.
 diapn
process. Next, dt is calculated using (16). If the criterion
outlined in (15) is met, then the fault is classified as a line-to-
ground fault; if not, then it is classified as a line-to-line fault if should exceed the set threshold during internal faults and remain
the criterion in (19) is satisfied. Upon detecting an internal fault, at
zero for external faults. However, in practical scenarios, the
di
the IEDs isolate the faulted part by sending a trip signal to the dt signal deviates slightly from zero during load switching
associated SSCBs. and external faults.
Generally, for a differential protection technique, the selection
of threshold depends on numerous factors [19]. These being the
D. Threshold Analysis
 di noise and measuring error in the signal, the charging current
The threshold (ζ) for fault detection is dependent on dt of the line, and communication delay. Hence, to establish a
characteristics of the faulted line. According to (1), these char- threshold, these factors are put into consideration. The permis-
acteristics depend on the di/dt signals of both the sending and sible measurement error for current signals should not exceed
receiving terminals of the line under evaluation. Furthermore, 3% [20]. Hence, for the current signal, a measurement error of
di
(11) indicates that the dt characteristics depend on fault 3% is kept in mind while setting the threshold. In addition, a
resistance,bus voltage, line current, and fault location on the 35 dB signal-to-noise ratio (SNR) signal is introduced to the
di
line. The dt signal is low for high-resistance faults, which is current signals in the event of a line-to-ground fault to decide
why it is used as the determining case for deciding the threshold the threshold. Therefore, by considering all the aforementioned
value. Therefore, to establish a threshold level, a high-resistance factors, a threshold value of ζ = 10A/50μs is established to
fault F is simulated on line 23 of the zonal dc microgrid, as activate the protection algorithm for any internal fault exhibiting
displayed in Fig. 1, exhibiting a 50 Ω fault resistance, while a fault resistance of up to 50 Ω.
altering the loading
 di and distance of fault occurrence on the line.
The obtained dt for all tested scenarios is shown in 
Fig. 8. IV. RESULTS AND DISCUSSION
di
On detailed examination of Fig. 8, the minimum dt of
11.459A/50μs is obtained during a 0.4 per unit fault distance A. Line-to-Ground Fault
and 120% loading condition. Hence, for effective identification A positive line-to-ground fault exhibiting a fault resistance
of internal faults within the zonal dc microgrid, the threshold
 di of 0.1 Ω is simulated midway along line 23 to validate the
magnitude needs to be set below 11.45A/50μs. Ideally, dt developed fault detection technique. Fig. 9(a) and (b) displays

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 SONDOULE et al.: ENHANCED PROTECTION ALGORITHM FOR ZONAL DC MICROGRIDS 5893

 di
Fig. 10. Line-to-line fault on line 23. (a) Current. (b) di/dt. (c)
 di dt . Fig.
11. External line-to-ground fault  on line 23. (a) Current. (b) di/dt.
di di
(d) di/dt: both poles. (e) dt : both poles of bus-2. (f) Trip and classifier (c) dt . (d) di/dt: both poles. (e) dt : both poles of bus-2. (f) Trip
signals. and classifier signals.

shows that the surge in currents at IED23 and IED32 occurs in

the current and di/dt signals,respectively, at IED23 and IED32 . opposite directions, as expected for external faults. Since the
di
As evident in Fig. 9(c), the dt signal at line 23 exceeds the fault is not on line 23, the overall current entering this line exits
threshold ζ, triggering a tripping action that effectively isolates almost entirely with negligible losses.
the faulted segment. As evident in Fig. 11(b), the di/dt signals at both IEDs are
Since the fault occurs on the positive pole, the di/dt char- similar in magnitude
acteristics on the positive pole undergo a significantly greater  di while being opposite in direction, resulting
in a near-zero dt on line 23, as seen in Fig. 11(c), which
disruption than the negative pole, as evidenced by Fig. 9(d). does not exceed the threshold or trigger the tripping mechanism
By utilizing the fault classification logic from Section III-B,
 di23pn [see Fig. 11(f)]. As no fault is detected, the fault classifier
dt is obtained as displayed in Fig. 9(e), allowing the fault remains inactive, and hence no fault classification signal is
to be classified as a line-to-ground fault by utilizing (15), as generated, proving that the scheme does not isolate unfaulted
depicted in Fig. 9(f). sections. Similar results are observed during islanding instances,
confirming the method’s reliability.
B. Line-to-Line Fault
Referring to Fig. 1, a line-to-line fault is emulated at t = D. Close-in Fault
1.00 s, 500 m from IED23 on line 23 of 1 km length. The results To evaluate the impact of a close-in fault on the zonal dc
acquired on simulating this line-to-line fault are depicted in microgrid system, a positive line-to-ground fault exhibiting a
Fig. 10. The currents seen at IED23 and IED32 are displayed 0.1 Ω fault resistance is emulated at 10 m from IED23 (0.01%
in Fig. 10(a). A symmetrical line-to-line fault produces a signif- of the line length). Fig. 12(a) and (b) shows that IED23 , being
icantly higher di/dt rise than an unsymmetrical line-to-ground closer to the fault, experiences a larger current and di/dt change
fault, asobserved in the di/dt signals in Fig. 10(b). than IED32 , which is farther away.
di
The dt characteristic for line 23 rises well above the This does not influence the efficiency of the
presented protec-
threshold, as displayed in Fig. 10(c), reliably detecting the fault tion method. As observed in Fig. 12(c), the di
on the faulted
dt
and raising a trip signal [see Fig. 10(f)]. Unlike line-to-ground line exceeds the threshold, triggering the fault isolation process
faults, this type of fault disturbs the signals at both the positive [see Fig. 12(f)]. Fig. 12(d)–(f) confirms that the fault classifi-
pole and the negative pole equally but in opposite directions, as cation also works effectively, demonstrating that the proposed
 diapn
indicated in Fig. 10(d). When dt is calculated using (16) scheme handles close-in faults reliably.
per the fault classification scheme, the opposing signals cancel
each other, as shown in Fig. 10(e), correctly identifying the fault E. High-Resistance Fault
as a line-to-line fault [see Fig. 10(f)].
The durability of the developed zonal dc microgrid fault detec-
tion and classification technique is tested using a high-resistance
C. External Fault
line-to-ground fault with a 50 Ω fault resistance, midway along
An external line-to-ground fault F1 with 0.1 Ω fault resistance line 23. The increased fault resistance reduces the fault current,
is initiated midway along line 12 to evaluate the selectivity of as displayed in Fig. 13(a), causing many conventional methods,
the suggested fault identification and classification technique, including overcurrent, differential, and polarity-based methods
and the responses of IEDs on line 23 are observed. Fig. 11(a) to fail under such conditions.

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 5894 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 21, NO. 8, AUGUST 2025

Fig.
12. Close-in line-to-ground fault  on line 23. (a) Current. (b) di/dt.  di
Fig. 14. Load switching on line 23. (a) Current. (b) di/dt. (c)
(c) di
dt . (d) di/dt: both poles. (e)
di
dt : both poles of bus-2. (f) Trip  di dt
and classifier signals. (d) di/dt: both poles. (e) dt : both poles of bus-2. (f) Trip and classifier
signals.

drop of 200 KW at bus-8 simulated at 1.00 s in the zonal dc

microgrid. The functionality suggested in this research relies on
the di/dt characteristics monitored by the IEDs situated on the
sending and receiving ends of line 23. Fig. 14(a) shows that the
current signals at both of these IEDs are opposite in direction.
Likewise, Fig. 14(b) reveals that the di/dt characteristics of these
IEDs also
 dioppose each other, leading to a cancellation effect
in the dt signal, calculated using (1), as seen in Fig. 14(c).
 di
This phenomenon resembles the dt characteristics observed
during the regular functioning of the zonal dc microgrid.
di
Therefore, as evident from Fig. 14(c), the dt signal does
not rise above the threshold as no significant variation can be
observed in the signal when the load drops. Hence, no trigger
signal is generated and the zonal dc microgrid works efficiently
without any disturbances. As there is no fault detected, the fault
 di
Fig. 13. High-resistance  on
line-to-ground fault
di
line 23. (a) Current.
classification scheme remains inactive, leading to the absence
(b) di/dt. (c) dt . (d) di/dt: both poles. (e) dt : both poles of bus-2.
(f) Trip and classifier signals. of a fault classification signal being generated, as evident in
Fig. 14(f).
From these results, it is validated that the proposed protection
In contrast, the proposed technique performs adequately for scheme functions appropriately under sudden load switching
high-resistance faults, as seen in Fig. 13. The key advantage of conditions and does not generate a trip signal, unlike in fault
the technique lies in its use of the sum of the di/dt characteristics cases.
from both the sending and receiving end IEDs as the triggering
parameter, as per (1), doubling the tolerance for high-resistance G. In Noisy Setting
faults compared to one-sided current-derivative-based methods.
The efficiency of the suggested protection method is assessed
This dual-end approach compensates for reduced di/dt due to
using input signals with an SNR of 35 dB, simulating a noisy
high resistance, maintaining accuracy and effectiveness even
environment. White Gaussian noise, which is commonly used
under challenging conditions. 
di to model real-world noise in power systems, is incorporated into
As illustrated in Fig. 13(c), the dt signal crosses the thresh- the current signals of the zonal dc microgrid to represent external
old, initiating faulty section isolation. In addition, Fig. 13(e)
EMI. A positive line-to-ground fault is simulated midway along
and (f) confirms that the fault classification algorithm remains
line 23 at 1 s. Fig. 15 shows that despite the noise in the current
effective even under high-resistance conditions.
signals, the suggested scheme accurately detects and classifies
the fault.
F. Load Switching Condition
The proposed method operates by summing the di/dt signals
The suggested fault identification and classification algorithm from both ends of the faulted line, calculating the overall rate of
di
is studied for a regular transient, specifically a sudden load change of current ( dt ), as per (1). This differential approach

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 SONDOULE et al.: ENHANCED PROTECTION ALGORITHM FOR ZONAL DC MICROGRIDS 5895

 di fault in noisy environmentondiline 23. (a) Cur-

Fig. 15. Line-to-ground
Fig. 17. (a) Radial dc microgrid. (b) Meshed dc microgrid.
rent. (b) di/dt. (c) dt . (d) di/dt: both poles. (e) dt : both poles of
bus-2. (f) Trip and classifier signals.

the entire range of fault resistances evaluated. Even under

conditions of high resistance, which could potentially dampen
fault-induced signals, the algorithm effectively identifies fault
conditions without delay.

I. Topology Change
To validate the applicability of the presented technique across
various dc microgrid configurations, its performance is evalu-
 di ated on two configurations: a radial dc microgrid and a meshed
Fig. 16. dt for varying fault resistances. (a) Line-to-ground fault.
(b) Line-to-line fault. dc microgrid, as illustrated in Fig. 17(a) and (b), respectively.
These test systems are analyzed for a line-to-ground fault with
a 0.1 Ω fault resistance.
helps mitigate the impact of noise on the individual current These dc microgrid configurations are designed with similar
measurements. The summation effectively cancels out a signif- technical specifications as the zonal dc microgrid, as described
icant portion of the high-frequency noise, making the method in Section II, and both operate at a rated voltage of 1200 V.
more resilient to noise in the fault detection process. Despite the A line-to-ground fault F2 is emulated midway along line 23 in
di/dt-based method being typically sensitive to noise, the results the radial dc microgrid [see Fig. 17(a)], with the fault analysis,
show that the algorithm maintains its integrity and accurately as shown in Fig. 18. Similarly, in the meshed dc microgrid
classifies the fault. [see Fig. 17(b)], a line-to-ground fault F3 is emulated mid-
way along line 12, with the corresponding results presented in
H. Variation in Fault Resistance Fig. 19.
The efficiency of the presented algorithm is assessed across a Figs. 18 and 19 demonstrate that the proposed fault identifi-
broad range of fault resistances, spanning from 0.01 to 50 Ω, for cation and classification scheme performs effectively and accu-
both line-to-ground and line-to-line faults at the midpoint of line rately in both radial and meshed dc microgrid configurations.
23 of the zonal dc microgrid. This evaluation aims to examine The results confirm that the technique consistently detects and
the impact classifies faults across different network topologies, ensuring
 diof varying fault resistance on its performance. robust protection. This highlights the versatility and adaptability
The dt signals observed for line-to-ground faults at various
fault-resistance values are illustrated in Fig. 16(a). Similarly, of the proposed technique, making it suitable for a wide range
 di of dc microgrid applications.
the dt signals for line-to-line faults under varying fault resis-
tances are shown in Fig. 16(b). The results reveal that the peak
of the di J. Comparative Analysis
dt signal decreases as the fault  resistance increases.
di
Despite this reduction in peak values, the dt signal reliably Table II presents a comparative analysis between the proposed
crosses the detection threshold (ζ) at the very first sampling fault detection scheme and existing unit protection techniques.
instance immediately after the fault occurs, irrespective of the Unlike several existing methods [13], [17], [22], [23], [27], [28],
resistance value for both types of faults. [29], the proposed scheme demonstrates the capability to detect
These findings demonstrate the robustness of the suggested close-in faults. In addition, the fault identification time of the
technique in promptly and reliably identifying faults across suggested technique is significantly shorter, being 98% faster

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 5896 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 21, NO. 8, AUGUST 2025

TABLE II
EVALUATION OF THE PROPOSED APPROACH AGAINST EXISTING PROTECTION METHODS

in [22], [24], and [25], 900% higher max Rf than those in [7]
and [28], 400% higher max Rf than those in [6], [27], and [29],
150% higher max Rf than that in [21], and 100% higher max
Rf than that in [26]. In addition, the computational complexity
of the suggested algorithm is significantly lower compared to the
methods in [12], [17], [21], [22], [23], [24], [25], [26], and [27].
The proposed approach can also identify faults in both ring and
radial dc microgrids, unlike the schemes presented in [13], [21],
[22], [26], [27], and [29], which may fall short during the same.
Moreover, it demonstrates superior stability when encountering
external disturbances, such as the de-energization of neighbor-
ing faulty lines, in contrast to methods proposed in [6], [24],
[25], [27], and [28]. Overall, the suggested method outperforms
current protection strategies based on the aforementioned case
studies.

 di
Fig. 18. Line-to-ground  di
fault in radial system on line 23. (a) Current.
K. Hardware Verification
(b) di/dt. (c) dt . (d) di/dt: both poles. (e) dt : both poles of bus-2.
(f) Trip and classifier signals. A hardware testbed for a zonal dc microgrid, as illustrated in
Fig. 20, serves as the real-time evaluation platform for testing
and validating the proposed protection technique. The setup in-
cludes a 1 kW doubly-fed induction generator (DFIG)-type wind
turbine emulator connected to the dc bus through a three-phase
inverter, and two 72 V, 24 Ah lithium-ion battery banks, each
with a 72/110 V bidirectional converter. The zonal dc microgrid
is also linked to the main ac grid at buses 1 and 4 via 3 KVA
autotransformers, delta-star step-up power transformers, and 5
KVA VSCs. These components ensure that the zonal dc micro-
grid operates at a voltage of 120 V and stays synchronized with
the conventional grid. The experimental setup utilizes control
circuits for all converters, which are executed on the LAB-
VIEW environment and connected via field-programmable gate
arrays SBRIO 9607. The MATLAB/Simulink software hosts the
di/dt-based fault identification and classification scheme, and
Control Desk 6.0 interfaces the code into the dSPACE 1104
processor. The testbed outputs are attenuated and fed into the
 di
Fig. 19. Line-to-ground  dion line 12. (a) Current.
fault in meshed system
analog-to-digital inputs of the dSPACE 1104, with LA 25-P
(b) di/dt. (c) dt . (d) di/dt: both poles. (e) dt : both poles of bus-2.
(f) Trip and classifier signals. sensors employed to measure currents. A 2 Ω, 0.5 H dc line
is used to connect buses 2 and 3, and BDD-2440-00 SSCBs are
used at the ends of this line. The connections and logic of the
than [22], 89.47% faster than [17], 88.23% faster than [28], hardware system are shown in Fig. 21.
50% faster than [24], and 33.33% faster than [7] and [23]. To validate the suggested scheme in a hardware environment,
Furthermore, the suggested algorithm can detect high-resistance an internal line-to-ground fault F4 , an internal line-to-line fault
faults with up to 50 Ω fault resistances (Rf ), outperforming F5 , and an external line-to-ground fault F6 are performed, each
established methods with 2400% higher max Rf than those with a 6 Ω fault resistance, as depicted in Fig. 21. In all of

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 SONDOULE et al.: ENHANCED PROTECTION ALGORITHM FOR ZONAL DC MICROGRIDS 5897

Fig. 22. Hardware Results. (a) Internal line-to-ground fault. (b) Internal
line-to-line fault. (c) External line-to-ground fault.

 di1pn
Also, the dt signals in Fig. 22 confirm that the faults are
accurately classified in each fault case.
Analysis of the simulation and hardware results shows that
the suggested algorithm detects the fault very quickly within
1 ms. Thus, the total fault-clearing time of the suggested al-
gorithm is determined as 2 ms. This duration encompasses the
Fig. 20. Component connections in the zonal dc microgrid hardware time taken for relay computation, 50 μs [30] operational time
test setup. of the SSCB, and a communication delay of <1 ms, as the
data are transmitted via advanced fiber optic communication
[27].

V. CONCLUSION
This article introduces a robust technique designed for detect-
ing and classifying faults within a zonal dc microgrid, employing
the IEC 61850
 dicommunication guideline. Detection of the fault
relies on dt signal generated by using information from
IED stationed at each end of the line  segment. A steady-state
di
condition yields almost zero value of dt signal, while tran-
sients result in nonzero magnitudes. Following fault detection,
 diapn
the fault classification is determined by calculating dt .
The suggested scheme can identify and categorize faults in less
than 2 ms, even when encountering fault resistances of up to
50 Ω. Moreover, it demonstrates resilience in noisy environ-
ments and during load-switching events. Comparative analyses
demonstrate the superiority of this technique over existing fault
Fig. 21. Zonal dc microgrid hardware configuration diagram. identification methods.
Comprehensive testing was conducted to check the efficacy of
the suggested algorithm across diverse fault scenarios, encom-
these cases, the current at both line terminals rises suddenly, as passing internal, external, close-in, high-resistance, and noisy
illustrated in Fig. 22. environments. Thorough simulations confirmed that the devel-
Fig. 22(a) and (b) demonstrates that for internal faults, cur- oped algorithm consistently and precisely detects and classifies
rents at both line terminals rise with the same polarity, while for all faults that may occur within the zonal dc microgrid. This
an external fault, the currentsrise with opposite polarities, as progress in fault recognition shows considerable promise for
di
displayed in Fig. 22(c). The dt characteristics on the faulted improving the dependability and security of the zonal dc micro-
line as monitored by a digital signal oscilloscope generate fault grid. Validation on a hardware testbed confirms the correctness
detection triggers only for internal faults, as seen in Fig. 22. of the algorithm.

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 5898 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 21, NO. 8, AUGUST 2025

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[13] G. K. Rao and P. Jena, “A novel fault identification and localization scheme Arya Arun Sondoule (Student Member, IEEE)
for bipolar DC microgrid,” IEEE Trans. Ind. Inform., vol. 19, no. 12, received the [Link]. degree in electrical en-
pp. 11752–11764, Dec. 2023. gineering from Rashtrasant Tukadoji Maharaj
[14] N. Yadav and N. R. Tummuru, “A real-time resistance based fault detection Nagpur University, Nagpur, India, in 2018, and
technique for zonal type low-voltage DC microgrid applications,” IEEE the [Link]. degree in power and energy sys-
Trans. Ind. Appl., vol. 56, no. 6, pp. 6815–6824, Nov./Dec. 2020. tems from the Indian Institute of Engineer-
[15] R. Bhargav, B. R. Bhalja, and C. P. Gupta, “Novel fault detection and ing Science and Technology, Shibpur, India, in
localization algorithm for low-voltage DC microgrid,” IEEE Trans. Ind. 2020. He is currently working toward the Ph.D.
Informat., vol. 16, no. 7, pp. 4498–4511, Jul. 2020. degree in power system engineering with the
[16] A. A. Sondoule, P. Jena, and N. P. Padhy, “Decision level fusion-based Department of Electrical Engineering, Indian In-
faulty section identification for medium voltage Zonal DC microgrid,” stitute of Technology Roorkee, Roorkee, India.
in Proc. IEEE 3rd Int. Conf. Sustain. Energy Future Electr. Transp., His research interests include dc microgrids, fault analysis, fault de-
Bhubaneswar, India, 2023, pp. 1–6. tection, microgrid protection, and zonal microgrids.

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 SONDOULE et al.: ENHANCED PROTECTION ALGORITHM FOR ZONAL DC MICROGRIDS 5899

Premalata Jena (Senior Member, IEEE) re- Narayana Prasad Padhy (Senior Member,
ceived the [Link]. degree in electrical engineer- IEEE) received the Ph.D. degree in power sys-
ing from Utkal University, Bhubaneswar, India, tems engineering from Anna University, Chen-
in 2001, and the [Link]. and Ph.D. degrees nai, India, in 1997.
in power system engineering from the Depart- He is currently the Director of the Malviya
ment of Electrical Engineering, Indian Institute National Institute of Technology, Jaipur, India,
of Technology (IIT) Kharagpur, Kharagpur, India, and the Mentor Director of the Indian Institute of
in 2006 and 2011, respectively. Information Technology Kota, Kota, India, along
Since 2012, she has been an Assistant Pro- with Professor (HAG) (on-lien) with the Depart-
fessor with the Department of Electrical Engi- ment of Electrical Engineering, Indian Institute
neering, IIT Roorkee, Roorkee, India, where she of Technology (IIT) Roorkee, Roorkee, India.
is currently a Professor. She is also with the Centre for Sustainable He was the Dean of Academic Affairs, Institute, NEEPCO, 92 Batch
Energy, IIT Roorkee as a joint faculty. Her research interests include and Ravi Mohan Mangal Institute Chair Professors, IIT Roorkee. He is
power system protection, microgrid protection, and issues due to the the National lead of many national and international projects, such as
integration of renewables with the existing power grid. DSIDES, ID-EDGe, and HEAPD. He is also part of other international
Dr. Jena was the recipient of the SERB-POWER Fellowship-2022 projects, namely, Indo-US UI-ASSIST and Indo-U.K. ZED-I. He has
from SERB, New Delhi, Women Excellence Award-2017 from DST, New authored and coauthored more than 200 research articles in reputed
Delhi, Young Engineer Award, Indian National Academy of Engineering, international journals and conference proceedings. His research inter-
and POSOCO Power System Award, Power Grid Corporation of India ests include power system analysis, demand side management, energy
Ltd., India, in 2013. market, network pricing, ac-dc smart grid, and application of machine
learning techniques in power systems.
Dr. Padhy is also a Fellow of the Indian National Academy of En-
gineers, Institution of Electronics and Telecommunication Engineers,
India, Institution of Engineering and Technology, and Institution of Engi-
neers India. He was the recipient of the IEEE Smart Cities Award 2022,
IEEE PES Outstanding Engineers Award 2018, Boyscast Fellowship,
and the Humboldt Experienced Research Fellowship in the years 2005
and 2009, respectively.

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