Digital Logic Design

Chapter Five:
Counters and Registers
 COUNTER
 Flip-flops can be connected together to perform counting operations. Such a group
of flip-flops is a counter.
 The number of flip-flops used and the way in which they are connected determine
the number of states (called the modulus) and also the specific sequence of states
that the counter goes through during each complete cycle.
 Counters are classified into two broad categories according to the way they are clo
a. Asynchronous and
b. Synchronous.
 In asynchronous counters, commonly called ripple counters, the first flip-flop is
clocked by the external clock pulse and then each successive flip-flop is clocked by
the output of the preceding flip-flop.
 In synchronous counters, the clock input is connected to all of the flip-flops so that
they are clocked simultaneously_
 Within each of these two categories, counters are classified primarily by the type of
sequence, the number of states, or the number of flip-flops in the counter.

2
 a) ASYNCHRONOUS COUNTER OPERATION
 The term asynchronous refers to events that do not have a fixed time relationship with each
other and, generally, do not occur at the same time.
 An asynchronous counter is one in which the flip-flops (FF) within the counter do not change
states at exactly the same time because they do not have a common clock pulse.
A 2-Bit Asynchronous Binary Counter
 Figure below shows a 2-bit counter connected for asynchronous operation. Notice that the
clock (CLK) is applied to the clock input (C) of only the first flop-flop, FF0, which is always the
least significant bit (LSB).
 The second flip-flop, FFI, is triggered by the Qo output of FF0.
 FF0 changes state at the positive-going edge of each clock pulse, but FF1 changes only when
triggered by a positive-going transition of the Qo output of FF0.
 Therefore, the two flip-flops are never simultaneously triggered, so the counter operation is
asynchronous.
 Asynchronous counters are also
known as ripple counters.

3
 Cont…
 The Timing Diagram: Let's examine the basic operation of the asynchronous counter of
Figure above by applying four clock pulses to FFO and observing the Q output of each flip-
flop.
 Figure below illustrates the changes in the state of the flip-flop outputs in response to the
clock pulses.
 Both flip-flops are connected for toggle operation (J = 1, K = 1) and are assumed to be
initially RESET (Q LOW).

Table :Binary state sequence for the counter

Timing diagram for the counter of Figure above
 Since it goes through a binary sequence, the counter in above is a binary counter.
 It actually counts the number of clock pulses up to three, and on the fourth pulse it recycles
to its original state (Qo = 0, Q, = 0).
 The term recycle is commonly applied to counter operation; it refers to the transition of the
counter from its final state back to its original state. 4
 Cont….
• A 3-Bit Asynchronous Binary Counter :- The state sequence for a 3-bit binary counter is
listed in Table 8-2, and a 3-bit asynchronous binary counter is shown in Figure below(a).
• The basic operation is the same as that of the 2-bit counter except that the 3-bit counter has
eight states, due to its three flip-flops.
• A timing diagram is shown in Figure below(b) for eight clock pulses. Notice that the counter
progresses through a binary count of zero through seven and then recycles to the zero state.
• This counter can be easily expanded for higher count, by connecting additional toggle flip-
flops.

Digital logic design by Nigatu A 5

 Cont…
 Propagation Delay:- Asynchronous counters are commonly referred to as ripple counters for
the following reason: The effect of the input clock pulse is first "felt" by FF0.
 This effect cannot get to FFI immediately because of the propagation delay through FFO.
Then there is the propagation delay through FF1 before FF2 can be triggered.
 Thus, the effect of an input clock pulse "ripples" through the counter, taking some time, due
to propagation delays, to reach the last flip-flop.
 To illustrate, notice that all three flip-flops in the counter of Figure below change state on
the leading edge of CLK4. This ripple clocking effect is shown in Figure below for the first
four clock pulses, with the propagation delays indicated.
 This cumulative delay of an asynchronous counter is a major disadvantage in many
applications because it limits the rate at which the counter can be clocked and creates
decoding problems.
 The LOW-to-HIGH transition of Qo
occurs one delay time (tPLH) after
the positive-going transition of the
clock pulse.
 Thus, it takes three propagation de-
lay times for the effect of the clock
pulse, CLK4, to ripple through the
counter and change Q2 from LOW
to HIGH. 6
 MOD Number
• The counter in Figure above(with 3 FFs) has 8 distinctly different states (000 through 111),
thus, it is a MOD-8 ripple counter.
• Recall that the MOD number ¡s always equal to the number of states that the counter goes
through in each complete cycle before it recycles back to its starting state.
• The MOD number can be increased simply by adding more FF lo the counter.
• That is, MOD number = 2N where N is the number of FFs
• Example:- A counter is needed that will count the number of items passing on a conveyor
belt. A photocell and light source combination is used to generate a single pulse
each time an item crosses its path. The counter must be able to count as many as
two thousand items. How many FFs are required?
COUNTERS WITH MOD NUMBERS <2N
 The basic asynchronous counter of Figure below is limited to MOD numbers that are
equal to 2N where Nis the number of FFs.
 This value is actually the maximum MOD number that can be obtained using N flip-flops.
 The basic counter can be modified to produce MOD numbers less than 2N by allowing the
counter to skip slates that are normally part of the counting sequence.
 One of the most common methods for doing this is illustrated in Figure below, where a
three-bit counter is shown.

7
 Cont…

 Example :-Construct a MOD-6 counter that will count from 000 (zero) through 110
(decimal 6), show also the timing diagram and glitch or spikes.
 Solution:

8
 Timing diagram
• .

• Example :-Construct a MOD-10 counter that will count from 0000 (zero) through 1001
(decimal 9), show also the timing diagram and glitch or spikes.
• Example :-Construct a MOD-13 counter that will count from 0000 (zero) through 1100
(decimal 12), show also the timing diagram and glitch or spikes.
• Example :-Construct a MOD-14 counter that will count from 0000 (zero) through 1101
(decimal 13), show also the timing diagram and glitch or spikes.
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 ASYNCHRONOUS DOWN COUNTER
• All of the counters we have looked at thus far have counted upward from zero; that
is, they were UP COUNTERS.
• It is a relatively simple matter to construct asynchronous (ripple) down counters, which will
count downward from a maximum count to zero.
• The input pulses are applied to the A flip-flop. The A’ output serves as the CLK
input for the B flip-flop; the B’ output serves as the CLK input for the C flip-flop.

Digital logic design by Nigatu A 10

 B) SYNCHRONOUS COUNTER OPERATION
• The term synchronous refers to events that have a fixed time relationship with each other.
• A synchronous counter is one in which all the flip-flops in the counter are clocked at the
same time by a common clock pulse.
A 3-Bit Synchronous Binary Counter
 A 3-bit synchronous binary counter is shown in Figure below, and its timing diagram is shown
in Figure below.

Digital logic design by Nigatu A 11

 A 4-Bit Synchronous Binary Counter
• Figure below(a) shows a 4-bit synchronous binary counter, and Figure below(b) shows its
timing diagram.
• This particular counter is implemented with negative edge-triggered flip- flops.

Digital logic design by Nigatu A 12

 Cont…
• The problems encountered with ripple counters are caused by the accumulated FF
propagation delays; stated another way, the FFs do not all change states simultaneously in
synchronism with the input pulses.
• These limitations can be overcome with the use of synchronous or parallel counters in which
all of the FFs are triggered simultaneously (in parallel) by the clock input pulses.
• If we compare the circuit arrangement for this synchronous counter with its asynchronous
counterpart , we can see the following notable differences:
 The CLK inputs of all of the FFs are connected together so that the input clock
signal is applied to each FF simultaneously.
 Only flip-flop A, the LSB, has its J and K inputs permanently at the HIGH level.
The J, K inputs of the other FFs are driven by some combination of FF outputs.
 The synchronous counter requires more circuitry than does the asynchronous
counter.
Advantage of Synchronous Counters over Asynchronous
• In a parallel counter all of the FFs will change states simultaneously; that is, they are
all synchronized to the input clock pulses.
• Thus, unlike the asynchronous counters, the propagation delays of the FFs do not add
together to produce the overall delay.
• Instead, the total response time of a synchronous counter like the one in Figure above is the
time it takes one FF to toggle plus the time for the new logic levels to propagate through a
single AND gate to reach the J, K inputs.
• Thus, a synchronous counter can operate at a much higher input frequency. of course, the
circuitry of the synchronous counter is more complex than that of the asynchronous counter.
13
 DESIGN OF SYNCHRONOUS COUNTERS
General Model of a Sequential Circuit
• Before proceeding with a specific counter design technique, let's begin with a general
definition of a sequential circuit or state machine: A general sequential circuit consists of a
combinational logic section and a memory section (flip-flops), as shown in Figure below.
• In a clocked sequential circuit, there is a clock input to the memory section as indicated.

14
 Cont…
• Counters are a special case of clocked sequential circuits. In this section, a general design
procedure for sequential circuits is applied to synchronous counters in a series of steps.
• A summary of steps used in the design of this counter follows. In general, these steps can be
applied to any sequential circuit.
1. Specify the counter sequence and draw a state diagram.
2. Derive a next-state table from the state diagram.
3. Develop a transition table showing the flip-flop inputs required for each transition. The
transition table is always the same for a given type of flip-flop.
4. Transfer the J and K states from the transition table to Karnaugh maps. There is a
Karnaugh map for each input of each flip-flop.
5. Group the Karnaugh map cells to generate and derive the logic expression for each flip-
flop input.
6. Implement the expressions with combinational logic. and combine with the flip-flops to
create the counter.
• State Diagram:-The information available in a state table can be represented graphically in
a state diagram.
• In this type of diagram, a state is represented by a circle, and the transition between states is
indicated by directed lines connecting the circles.
• The binary number inside each circle identifies the state of the flip-flops.
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 Cont…
• Example:-Design a synchronous counter for a 3-bit Gray code counter.
• Step 1: State Diagram

Next-state
State diagram table for 3-
for a 3-bit Gray bit Gray
code code
counter. counter.

• Step 2: Next-State Table :-The next state is the state that the counter goes to from its present
State upon application of a clock pulse (shown as above)
• Step 3: Flip-Flop Transition Table :-Table below is a transition table for the J-K flip-flop. All
possible output transitions are listed by showing the Q output of the flip-flop going from
present states to next states.
 To design the counter, the transition
table is applied to each of the flip-
flops in the counter, based on the
next-state table above.

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 Cont…
• Step 4: Karnaugh Maps :- Karnaugh maps can be used to determine the logic required for
the J and K inputs of each flip-flop in the counter.
• The completed Karnaugh maps for all three flip-flops in the counter are shown in Figure
below. The cells are grouped as indicated and the corresponding Boolean expressions for
each group are derived.

Fig: Karnaugh maps

for present-state
J and K inputs.

Digital logic design by Nigatu A 17

 Cont…
• Step 5: logic Expressions for Flip-Flop Inputs :-From the Karnaugh maps of Figure above you
obtain the following expressions for the J and K inputs of each flip-flop:

• Step 6: Counter Implementation :-The final step is to implement the combinational logic from the
expressions for the J and K inputs and connect the flip-flops to form the complete 3-bit Gray code
counter as shown in Figure below.

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 Cont…
• Example:- Design a counter with binary count sequence shown in the state diagram of Figure
below. Use J-K flip-flops.

• Example:- Design 4-Bit Synchronous Decade Counter to produce a BCD counting sequence
of the following binary sequence. Use J-K flip-flops.
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0,…
• Example:- Design a counter to produce the following binary sequence. Use J-K flip-flops.
1, 4, 3, 5, 7, 6, 2, 1, …
• Example:- Design a synchronous counter to produce the following binary sequence. Use J-K
flip-flops.
0, 9, 1, 8, 2, 7, 3, 6, 4, 5, 0, . 19
 REGISTERS
• A register is a group of flip-flops capable of storing one bit of
information.
• An n-bit register has a group of n flip-flops and is capable of I1 A1
CP
storing any binary information of n bits.
• In addition to flip-flops, registers can have combinational gates
that perform certain data-processing tasks.
I2 A2
• The flip-flops hold binary information and the gates control
when and how new information is transferred into the register.
• The simplest possible register is one that consists of only flip-
flops without any external gates.
I3 A3
• Figure below shows such a register constructed with four D-
type flip-flops and a common clock-pulse input.
• The common clock input triggers all flip-flops on the rising
edge of each pulse, and the binary data available at the four A4
inputs are transferred into the 4-bit register.
I4

• The clear input is useful for clearing the register to all 0's prior
to its clocked operation.
Clear
• Note that the clock signal enables the D input but that the Fig. 4-bits register
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clear input is independent of the clock.
 Register load
• The transfer of new information into a register is referred
 to
The
as adifference
loading thebetween
register. computer architecture
and computer organization:
• If all the bits of the register are loaded simultaneously
with a single clock pulse, we say that the loading is done
in parallel.
• A clock transition applied to the Clock inputs of the
register of Fig. above will load all four inputs I1 through I4
in parallel.
• In this configuration, the clock must be
inhibited(prevented) from the circuit if the content of the
register must be left unchanged.
• In other words, the Clk input act as an enable signal that
controls the loading of new information into the register.
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 Register with Parallel Load
 Most digital systems have a master clock
generator that supplies a continuous train of
clock pulses.
 A 4-bit register with a load control input using D
FFs is shown in Fig. below.
 The Clock inputs receive clock pulses at all
times.
 The purpose of the buffer gate in the clock input
is to reduce the power requirement from
master-clock generator(to increase “fan-out”).
 In this register, the operation of the register is
controlled by the load input.
 Load Input
 1 : Four input transfer
 0 : Input inhibited, Feedback from output
to input( no change)
• Note that the clock pulses are applied to the
Clock input at all times. Fig. Register with parallel Load
using D flip-flops
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 Shift Registers
• A register capable of shifting its binary information in one or both directions is called a
shift register.
• Shift registers are constructed by connecting flip-flops in cascade, where the output of
one flip-flop is connected to the input of the next flip-flop.
• All flip-flops receive common clock pulses that initiate the shift from one stage to the
next.
• The simplest possible shift register is one that uses only flip-flops, as shown in Fig. below.

Fig. 4-bit shift register

• The serial input determines what goes into the leftmost position during the shift and
• The serial output is taken from the output of the rightmost flip-flop.
• The register in Fig. above shifts its contents with every clock pulse.
• If we want to control the shift, we must control the Clock input of the register.
• If, however, the shift register in Fig. above is used, the shift can easily be controlled by
means of an external AND gate, as shown in what follows. 23
 Serial Transfer(Cont’d)

•
 Amanipulated
digital system is said to operate in a serial mode when information is transferred and
The difference between computer architecture
one bit at a time.
and
• The computer
information organization:
is transferred one bit at a time by shifting the bits out of the source
register into the destination register.
• The serial transfer from register A to register B is done with shift registers, as shown in
the block diagram of Fig. (a).
 The serial output (SO) of register A goes
to the serial input (SI) of register B.

 To prevent the loss of information

stored in the source register, the A
register is made to circulate by
connecting the serial output to its
serial input terminal.
 The initial content of register B is shifted out through its serial output and is lost unless
it is transferred to a third shift register.
• The shift control input determines when and by how many times the registers are
shifted.
• This is done by the AND gate that allows clock pulses to pass into the CP terminals only
when the shift control is 1 24
 Cont’d

•  E.g.
The Suppose the shift between
difference registers have four bits each.
computer architecture
• Theand computer
control unit that organization:
supervises the transfer must enables the shift
registers, through the shift-control signal, for a fixed time duration
equal to four clock pulses. This is shown in the timing diagram of Fig.
(b).
• For n-bits register, n-clock pulses are required to transfer all n-bits.

(b).timing diagram
25
 Cont’d
• The shift-control signal is synchronized with the clock and changes value just
 after
Thethedifference
positive edge ofbetween
a clock pulse. computer architecture
• The
and nextcomputer organization:
four clock pulses find the shift-control signal in the 1 state, so the
output of the AND gate connected to the CP terminals produces four pulses, T1.
T2, T3, and T4.
• E.g. : Assume that the binary content of A before the shift is 1011 and that of B,
0010. after the fourth shift, what would be the contents of both register A and
register B?

 After the fourth shift, both registers A and B have the value 1011.
 Thus, the content of A is transferred into B, while the content of A remains
unchanged.
26
 Cont’d
• The difference between serial and parallel modes of operation
 should
The difference between
be apparent from computer architecture
this example.
and computer organization:
Serial transfer mode Parallel transfer mode
 The operation is slower  The operation is faster
 Only one bit is transferred  All bits transferred
during one clock-pulse simultaneously during one
clock-pulse
 For n-bits register, n-clock  For n-bits register, 1-clock
pulses are required to pulse is required to
transfer all n-bits. transfer all n-bits.

 Require less hardware  Require more hardware

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 Bidirectional Shift Register with Parallel load
 A register capable of shifting in one direction only is called a
unidirectional shift register
 A register that can shift in both directions is called a bidirectional
shift register
 The most general shift register has all the capabilities listed below:
 An input for clock pulses to synchronize all operations.
 A shift-right operation and a serial input line associated with the
shift-right.
 A shift-left operation and a serial input line associated with the
shift-left.
 A parallel load operation and n input lines associated with the
parallel transfer.
 n parallel output lines.
 A control state that leaves the information in the register
unchanged even though clock pulses are applied continuously.
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 Cont’d
• If the register has both shift and parallel-
load capabilities, it is called a shift register
with parallel load.
• A 4-bit bidirectional shift register with
parallel load is shown in Fig. below.
• Each stage consists of a D flip-flop and a 4
x 1 multiplexer.
• The two selection inputs S1 and So select
one of the multiplexer data inputs for the D
flip-flop.
• The selection lines control the mode of
operation of the register according to the
function table shown in Table below.
Mode Operation
S1 S0
0 0 No Change
0 1 Shift right(down)
1 0 Shift left(up)
1 1 Parallel load 29