ASSIGNMENT NO.
01(UNIT-1)
Course Outcome-1, Session 2021-22
SUB: COMPUTER ORGANIZATION & ARCHITECTURE (KCS-302)
Q.1. Represent the given conditional control statement by two register transfer statements with
control functions
If ( p=1 ) , then R 1 ← R 2 else if ( Q=1 ) then R 1 ← R 3
Q.2 What do you understand by the term micro-operation? Explain register and arithmetic types of
micro-operation. Show the hardware realization of decrement micro-operation i.e. α : A ← A−1.
Q.3 A register hold an 8-bit binary number 11011001. Determine the operand 'B' and the logic micro
operation to be performed in order to change the value of 'A' to (i) 00100110 and (ii) 01101101
Q.4 Draw the block diagram of Arithmetic Logic Unit (ALU) to perform the following operations. (use
MUX) ( Assume the length of data)
(i) AND (ii) NOR (iii) NAND (iv) XNOR
Q.5 Explain the different shift operations with example.
Q.6 Design a hardware circuit by using common bus architecture to implement the following register
Transfer languages .
P : A 1← A 2
Q : A 2← A 3
R: A4← A1
S:A 3← A 4, A1← A 4
Where A1, A2,A3, A4 are one bit register.
Q.7 Give the hardware realization of 4-bit arithmetic circuit capable of doing addition, subtraction,
increment, decrement etc. Give the function table and explain its operation.
Q.8 Draw a block diagram of a 4-bit binary adder-subtractor. Then , explain its operation in detail.
Q.9 What is micro operation? List and briefly explain the most commonly encountered arithmetic
operations.
Q.10 Design a 4-bit arithmetic circuit which is capable of performing the following micro-operations:
Addition (with and without carry)
Subtraction (with and without carry)
Increment
Decrement
and Transfer
Substantiate the circuit diagram with the help of an example.
Q.11 Draw the logic diagram of a logic circuit capable of performing X-OR, NOR, NAND, complement
operation of two bits A and B . During complement operation, the circuit should be capable of
complementing B.
Q.12 Draw a diagram of bus system for four registers of 4-bits each. The bus is to be constructed with
multiplexers.
Q.13 A digital computer has a common bus system for 8 registers of 8-bits each. The bus is constructed
with multiplexers.
(i) How many selection inputs are there in each multiplexers?
(ii) What size of multiplexers are needed?
(iii) How many multiplexers are there in the bus?
Q.14 A digital computer has a common bus system for 16 registers of 32-bits each. The bus is
constructed with multiplexers.
(i) How many selection inputs are there in each multiplexers?
(ii) How many multiplexers are there in the bus?
Q.15 An register B has the control function for load, clear and increment operation are given below:
LD ( B )=PT 0 + P T 2 +Q S T 3
CLR ( B )=PT 1 + P QT 3
INR ( B )=S T 3
where P, Q, S are control variables and T 0 ,T 1 , T 2 , T 3are timing sequences. Draw the control gate
circuitry for register B.
ASSIGNMENT NO.02
Course Outcome-2, Session 2021-22
SUB: COMPUTER ORGANIZATION & ARCHITECTURE (KCS-302)
Q.1. Add the following in 2's complement system using 8-bits (a) +9 to +6 (b) +19 to -24 and
(c) -48 to -80
Q.2 Perform the following operations in 2's complement system using 8-bits (a) subtract -17 from -17
(b) subtract +21 from -13 and (c)subtract -36 from -15
Q.3 Perform the following operations (a) multiply 111 by 101 (b) multiply 1101 by 101.101 and
(c)multiply 1101 by 110.010
Q.4 The content of a 4-bit shift register is initially 1101. The register is shifted 6 times to the right,
with serial input being 101101. What is the content of the register after each shift?
Q.5 With the neat flow chart discuss the procedure for floating point multiplication. Explain with the
help of an example.
Q.6 Show the step-by-step multiplication process using Booth's Algorithm, when +14 is multiplied by
-14. Assume 5-bit registers that hold signed numbers.
Q.7 Explain how addition and subtraction of floating point operations are carried out with an example
and show the algorithm/flow chart.
Q.8 Multiply -7 with +3 by using Booth's multiplication Algorithm. Give the flow table of the
multiplication.
Q.9 Give a flow table for the register contents used in implementing Booth's algorithm for the
multiplier=-6 and multiplicand =+5 .
Q.10 Using 8-bit 2's compliment representation of negative numbers, perform the following
computations: (i) -35+(-11) (ii) 19-(-4)
Q.11 Discuss addition and subtraction algorithm with the help of flowchart.
Q.12 An 8-bit register contains the binary value 10010110. What is the register value after following
shift micro operations:
(i) Arithmetic shift left
(ii) Circular shift left
(iii) Arithmetic shift Right
(iv) Logical shift left
Q.13 Explain the basic principle of Booth's algorithm for multiplication of signed 2's compliment
numbers. Give the algorithm in flowchart.
Q.14 Show the step-by-step multiplication using Booth's algorithm for the following multiplication:
(12)x(-9)
Q.15 Determine the single error-correcting code for the information code 10110 for odd parity.
Q.16 The code word 0011001 is transmitted and that 0010001 is received. The receiver does not know
what was transmitted and must look for proper parities to determine if the code is correct.
Designate any error that has occurred in representation if even-parity is used.
ASSIGNMENT NO.03
(Control Unit and Process Organization-CO3) Session: 2021-22
SUB: COMPUTER ORGANIZATION & ARCHITECTURE (KCS-302)
1) What do you mean by control unit? Describe briefly a Hardwired control unit. Also give its
timing diagram.
2) Briefly describe the execution of a complete instruction with the help of fetch and execute
phase.
3) Describe briefly a micro-programmed control unit.
4) What is microinstruction? Describe the microinstruction format.
5) Explain the difference between a micro-programmed control unit and Hardwired control unit.
what are their relative advantages and disadvantages?
6) Distinguish between a control memory and main memory used in a digital computer? Why
control memory is necessary? Show the organization of a Microprogrammed control unit and
explain its operation.
7) What do you mean by the term Microprogram sequence? Explain the role played by it.
8) With a neat block diagram explain the function of a microprogram sequencer.
9) What do you mean by fetch cycle, instruction cycle, machine cycle, interrupt acknowledgement
cycle?
10) To show how the number of address affects a computer program, we will evaluate the
arithmetic statement X =( A∗B )∗(C + D) using three, two, one or zero address instruction.
11) Evaluate the following arithmetic expressions using 3-address, 2-address, 1-address and 0-
address instructions to show the effects on computer program.
X =( A + B )∗(C−D)
12) A two word instruction is stored in memory at an address designated by symbol W. The address
field of the instruction (stored at W+1) is designated by the symbol Y. The operand used during
the execution of the instruction is stored at an address symbolized by Z. An index register
contains the value X. State how Z is calculated from the other addresses if the addressing mode
of the instruction is (a) Direct (b) Indirect (c) Relative and (d) Indexed
w Instruction
W+1 Address=Y
Z Operand
XR
X
Figure 12.1 Memory content
13) The two-word instruction at address 200 and 201 is a " load to Ac" instruction with an address
field equal to 500. The first word of the instruction specifies the operation code and mode , and
the second word specifies the address part. PC has the value 200 for fetching this instruction.
The context of processor register R1 is 400, and the content of an index register XR is 100. Ac
receives the operand after the instruction is executed. The Figure 12.1 lists a few pertinent
addresses and show the memory content at each of these addresses. Find the effective address
and operand that must be loaded into Ac for each possible mode.
200 Load to AC Mode
201 Address=500
202 Next Instruction
399 450
400 700
500 800
600 900
702 325
800 300
PC=200
R1=400
XR=100
AC
Figure 13.1 Numerical data for addressing mode
14) Write a program to evaluate arithmetic expression X =( A−B )∗( ( C−D∗E
F )/G)
a) Using a general register computer with three address instructions.
b) Using a general register computer with two address instructions.
c) Using a general register computer with one address instructions.
d) Using a general register computer with zero address instructions.
15) Justify the statement “ stack computer consists of an operation code only with no address
field".
16) If a computer has 128 operation codes and 512k addresses, how many bits would be required
for (i) Single address instruction (ii) Two address instruction.
17) What are interrupts? Explain different type of interrupts.
18) What is the difference between a direct and an indirect address instructions? How many
references to memory are needed for each type of instruction to bring an operand in to a
processor register?
19) A computer has a memory unit with 256K words of 32bits each. A binary instruction code is
stored in one word of memory. The instructions has four parts : an indirect bit, an operation
code, a register code part to specify one of 64 registers and an address part.
i. How many bits are there in the operation code, the register part and the address part?
ii. Draw the instruction word format and indicate the number of bits in each part.
iii. How many bits are there in the data and address inputs of the memory?
20) Discuss in brief (with their advantage and disadvantage ):
RISC(Reduced instruction set computer)
CISC (Complex instruction set computer)
21) An instruction is stored at location 300 with its address field at location 301. The address field
has the value 400. A processor register R1 contains the number 200. Evaluate the effective
address if the addressing mode of the instruction is
(a) Direct
(b)Register Indirect
(c) Relative
(d) Index with R1 as index register
(e) Immediate
22) To show how the number of address affects a computer program, we will evaluate the following
arithmetic statement using three, two, one or zero address instruction:
a) X=(A+B*C)*(C-D*E)/F
b) X=(A/B+C*D)/(D*E-F+C/A)
c) X=A*(B+C*(D+E))/(F*(G+H))
d) X=(A+B*C)/(D-E*F+G*H)
23) Convert the following arithmetic expressions form infix notation to Reverse Polish
Notation(RPN)
a) A+B*A+(B*E+A*D)
b) A*[C+(B*D)+(A*E)]
c) A*B+C*D+E*F
d) A+B*[C*D+E8(F+G)]
e) [A*(B+C*(D+E))]/(F*(G+H))