MODULE 2: FIELD EFFECT TRANSISTOR

FIELD EFFECT TRANSISTOR:

The field effect transistor is a three terminal unipolar semiconductor device in which current is
controlled by an electric field. There are two types of FET

a) Junction Field Effect Transistor (JFET)

b) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or Insulated Gate Field Effect
Transistor (IGFET)

MOSFET is further subdivided into 2 types.

a) Depletion Type MOSFET

b) Enhancement Type MOSFET

DIFFERENCE BETWEEN BJT & FET:

BJT FET
1. BJT is a bipolar device 1. FET is a unipolar Device
2. BJT is a current controlled device 2. FET is a voltage controlled device
3. BJT have comparatively low input 3. FET have high input impedance (due to
impedance (due to forward bias) reverse bias)
4. BJT have high noise level. 4. FET has low noise level.
5. For BJT, the gain is characterized by 5. For FET, gain is characterized by trans-
voltage gain. conductance.
6. BJT is less thermal stable. 6. FET has better thermal stability.
7. BJT are comparatively larger in size. 7. FET is usually smaller than BJT hence
particularly useful in integrated circuit.
8. BJT has higher voltage gain. 8. FET has lower voltage gain than BJT as it
depends upon the trans-conductance.

JUNCTION FIELD EFFECT TRANSISTOR (JFET):

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FABRICATION OF N-CHANNEL JFET:

1. A narrow bar of N-type semiconductor material is taken. At its middle part, two havily doped p-
type regions are formed by diffusion.
2. The junction form two P-N diodes or gates. The area between the gates is called a channel.
3. One end of the N-type bar is called as source terminal ‘S’.
4. The other end of the N-type bar is called as drain terminal ‘D’.
5. The souce and drain terminal may be interchanged.
6. When a potential difference is established between source and drain, a current flows from one
end to the other end in N-type material.
7. This current consists of majority carriers i.e. electrons.
8. Following notations for FET should be remembered.
a) SOURCE: The source ‘S’ is the terminal through which majority carrier enter the bar.
b) DRAIN: The drain ‘D’ is the terminal through which the majority carrier leave the bar.
c) GATE: These are heavily doped regions which forms two P-N junctions.

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 d) CHANNEL: The space between two gates through which majority carriers pass.

OPERATION OF N-CHANNEL FET:

1. When no volatges are applied, the

depletion regions were uniformly
distributed.
2. As a positive voltage is applied across
the channel and the gate is connected
directly to the source to establish the
condition 𝑉𝐺𝑆 = 0𝑉. Then the width of
the depletion region starts increasing.
3. As 𝑉𝐷𝐷 is applied , the electrons are
drawn to the drain terminal, hence a
current will flow in a defined direction.

4. The path of charge flow clearly define that 𝐼𝐷 = 𝐼𝑆

5. The depletion region is wider near the top of both the P-type material.

6. Assume a uniform resistance in the N-channel, we can break down the resistance into some
division.
7. The upper region of the P-type material will be reverse biased by 1.5V comparision with the
lower region.
8. We know from the diode operation, the greater the applied reverse bias, the wider is the
depletion region. Hence the depletion region is shown like this.
9. As 𝑉𝐷𝑆 increases and approaches a level referred as 𝑉𝑃 , the depletion region will widen, causing
a reduction in channel width. The reduced path of conduction causes the resistance to increase.
10. When two depletion region touch the condition is referred to as pinch-off.

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 11. The level of 𝑉𝐷𝑆 that establishes this condition is known as pinch-off voltage and denoted as 𝑉𝑃
12. In actuallity pinch-off suggests, the current 𝐼𝐷 is pinched off and drop to 0V, but in reality a very
small channel still exists, with a very high current density. Hence the 𝐼𝐷 doesn’t drop at pinch-off
but maintains the saturation level.

13. 𝐼𝐷𝑆𝑆 is the maximum drain current for a JFET and is defined by the condition 𝑉𝐺𝑆 = 0𝑉 and
𝑉𝐷𝑆 ≥ |𝑉𝑃 |
14. The voltage from gate to source 𝑉𝐺𝑆 is the controlling voltage of JFET. The reason to apply –ve
bias 𝑉𝐺𝑆 is to establish depletion region similar to those obtained with 𝑉𝐺𝑆 = 0𝑉 but at lower
level of 𝑉𝐷𝑆 . Hence saturation level can be achieved at lower 𝑉𝐷𝑆 .

TRANSFER CHARACTERISTICS:

In BJT 𝐼𝐶 = 𝛽𝐼𝐵 𝑤ℎ𝑒𝑟𝑒 𝛽 = 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝑎𝑛𝑑 𝐼𝐵 = 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 𝑣𝑎𝑟𝑖𝑎𝑏𝑙𝑒

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 𝑉𝐺𝑆 2
𝑆𝑖𝑚𝑖𝑙𝑎𝑟𝑙𝑦 𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − ) 𝑤ℎ𝑒𝑟𝑒 𝑉𝐺𝑆 = 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 𝑣𝑎𝑟𝑖𝑎𝑏𝑙𝑒 𝑎𝑛𝑑 𝑉𝑃 & 𝐼𝐷𝑆𝑆 = 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝑉𝑃

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − ) (𝑆ℎ𝑜𝑐𝑘𝑙𝑒𝑦 ′ 𝑠 𝐸𝑞𝑢𝑎𝑡𝑖𝑜𝑛)
𝑉𝑃

Transfer Graph:

1. 𝑉𝐺𝑆 = 0𝑉 𝑡ℎ𝑒𝑛 𝐼𝐷 = 𝐼𝐷𝑆𝑆

2. 𝑉𝐺𝑆 = 𝑉𝑃 𝑡ℎ𝑒𝑛 𝐼𝐷 = 0
𝐼𝐷𝑆𝑆
3. 𝑉𝐺𝑆 = 0.5𝑉𝑃 𝑡ℎ𝑒𝑛 𝐼𝐷 = 4
𝐼𝐷𝑆𝑆
4. 𝑉𝐺𝑆 = 0.3𝑉𝑃 𝑡ℎ𝑒𝑛 𝐼𝐷 =
2

EXAMPLE: Draw the transfer graph for the N-channel device with 𝐼𝐷𝑆𝑆 = 12𝑚𝐴 𝑎𝑛𝑑 𝑉𝑃 = −6𝑉

EXAMPLE: Draw the transfer graph for the P-channel device with 𝐼𝐷𝑆𝑆 = 4𝑚𝐴 𝑎𝑛𝑑 𝑉𝑃 = 3𝑉

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IMPORTANT RELATIONSHIPS:

1. 𝑉𝐵𝐸 = 0.7 was often the key to initiating an analysis of a BJT. Here 𝐼𝐺 = 0 is often the starting
point for the analysis.
2. For BJT, 𝐼𝐵 is normally the first parameter to be determined, Here in JFET, 𝑉𝐺𝑆 is normally the
first parameter for the calculation.

DEPLETION TYPE MOSFET:

Construction of N-channel Depletion Type MOSFET:

1. A slab of P-type material is formed from a silicon base referred as substrate.

2. In some cases sources is connected to the substrate internally, where as in other cases the
fourth lead is made available hence many device provides an additional terminal.
3. The source and drain are connected through metallic contact to N-doped region.
4. The N-doped regions are linked by an N-channel.

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 5. The gate is also connected to a metal contact surface but remain insulated from the N-channel
by a thin 𝑆𝑖𝑂2 layer. Means there is no electrical connection between the gate terminal and the
channel of a MOSFET.
6. Due to high input impedance the 𝐼𝐺 = 0
7. The insulating layer between the gate and channel has resulted another name i.e. Insulated
Gate FET (IGFET).

OPERATION:

1. Gate to source voltage is set to zero.( 𝑉𝐺𝑆 = 0𝑉)

2. 𝑉𝐷𝑆 is applied, electrons are attracted towards the positive potential resulting a current, when
𝑉𝐺𝑆 = 0𝑉 𝐼𝐷𝑆𝑆 will flow.

3. When 𝑉𝐺𝑆 is negative, the negative potential pressure electrons towards P-type substrate and
attract holes from P-type substrate.
4. Depending on the magnitude of the negative bias established by 𝑉𝐺𝑆 , the level of recombination
of electron and holes will occurs and will reduce the number of free electron in the channel.
5. The more negative voltage, the higher will be the rate of combination resulting less current.
6. When 𝑉𝐺𝑆 is positive, the positive gate will draw additional electron from the P-Substrate and
establish new carriers.
7. As the gate to source voltage (i.e. 𝑉𝐺𝑆 ) continues to increase, it will result rapid increase in the
drain current.
8. Due to the rapid rise, the user must be aware of the maximum drain current rating as it
increases with a positive gate voltage, which may possibly exceed the maximum rating for the
device.
9. Due to application of the positive gate to source voltage it increases the level of free carriers in
the channel compared to that for the 𝑉𝐺𝑆 = 0𝑉

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 10. For this reason of positive gate voltage, transfer characteristics are often referred to as
enhancement region.
11. The region between cut-off and saturation level of 𝐼𝐷𝑆𝑆 referred to as the depletion region.

P-channel Depletion type MOSFET:

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ENHANCEMENT TYPE MOSFET:

Construction of N-channel Enhancement type MOSFET:

The construction of n-channel enhancement

type MOSFET is similar to the construction of
depletion type MOSFET. Here the channel
between the two n-doped regions is absent.
This is the primary difference between the
construction of depletion type and
enhancement type MOSFET.

OPERATION:

1. Although some positive 𝑉𝐷𝑆 is applied,

as the 𝑉𝐺𝑆 = 0𝑉 , no channel exists
hence the current through the device is
0A i.e. 𝐼𝐷 = 𝐼𝑆 = 0𝐴
2. As some positive voltage 𝑉𝐺𝑆 is applied
to the gate terminal, the positive
potential at the gate will pressure the
holes in the p-substrate. Electron in the
p substrate will be attracted to the
positive gate and accumulated in the
region near to the surface of 𝑆𝑖𝑂2 layer.
3. As 𝑉𝐺𝑆 increases in magnitude, the
concentration of electron near
𝑆𝑖𝑂2 surface increases.
4. 𝑉𝐺𝑆 has to be increased until the
induced N-type region can support the
flow of current.

5. The level of 𝑉𝐺𝑆 that results in the significant increase in drain current is called the threshold
voltage and represented as 𝑉𝑇 𝑜𝑟 𝑉𝐺𝑆(𝑇ℎ)

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 6. The current is nonexistent with 𝑉𝐺𝑆 =
0𝑉 and enhanced by the application of
positive gate to source voltage, this
type of MOSFET is called as
enhancement type MOSFET.
7. Both depletion and enhancement type
MOSFET have enhancement type
region.
8. If we keep 𝑉𝐺𝑆 as constant and increase
the 𝑉𝐷𝑆 then the drain current will
increase and reach the saturation level.

Applying KVL to the terminal

𝑉𝐷𝐺 = 𝑉𝐷𝑆 − 𝑉𝐺𝑆
𝐿𝑒𝑡 𝑉𝐺𝑆 = 8𝑉 𝑎𝑛𝑑 𝑉𝐷𝑆 = 2 𝑡𝑜 5𝑉 (𝑖. 𝑒. 𝑖𝑛𝑐𝑟𝑒𝑎𝑠𝑖𝑛𝑔 𝑓𝑟𝑜𝑚 2 𝑡𝑜 5𝑉)
𝑉𝐷𝐺 𝑑𝑟𝑜𝑝𝑠 𝑓𝑟𝑜𝑚 − 6𝑉 𝑡𝑜 − 3𝑉
9. This reduction in gate to drain voltage will reduce the attractive force for free carriers, causes
reduction in channel width.

10. The channel will be reduced to the

point of pinch off and saturation
condition will be established.
11. But any further increase in 𝑉𝐷𝑆 at the
fixed value of 𝑉𝐺𝑆 will not affect the
saturation level of 𝐼𝐷 until breakdown
condition occurs.
𝑉𝐷𝑆(𝑆𝑎𝑡) = 𝑉𝐺𝑆 − 𝑉𝑇
12. For fixed 𝑉𝑇 ,higher the level of 𝑉𝐺𝑆 the
greater will be the saturation level of
𝑉𝐷𝑆
13. For 𝑉𝐺𝑆 less than the threshold voltage,
the drain current of an enhancement
type MOSFET is 0mA.
14. As 𝑉𝐺𝑆 increases from 𝑉𝑇 , the resulting
saturation level for 𝐼𝐷 also increases.

15. For 𝑉𝐺𝑆 > 𝑉𝑇 , the drain current is related to the applied gate to source voltage by the following
relationship.
𝐼𝐷 = 𝑘 (𝑉𝐺𝑆 − 𝑉𝑇 )2
𝑊ℎ𝑒𝑟𝑒 𝑘 = 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝑎𝑛𝑑 𝑖𝑡 𝑖𝑠 𝑎 𝑓𝑢𝑛𝑐𝑡𝑖𝑜𝑛 𝑜𝑓 𝑡ℎ𝑒 𝑐𝑜𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛 𝑜𝑓 𝑡ℎ𝑒 𝑑𝑒𝑣𝑖𝑐𝑒

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 𝐼𝐷(𝑜𝑛)
𝑘= 2
(𝑉𝐺𝑆(𝑜𝑛) − 𝑉𝑇 )

P-CHANNEL ENHANCEMENT TYPE MOSFET:

EXAMPLE:
Given 𝑉𝐺𝑆(𝑇ℎ) = 3𝑉 𝑉𝐺𝑆(𝑜𝑛) = 10𝑉 𝑎𝑛𝑑 𝐼𝐷(𝑜𝑛) = 3𝑚𝐴 then determine 𝑘 and draw the transfer
graph.
ANSWER:
𝐼𝐷(𝑜𝑛) 3𝑚𝐴 3𝑚𝐴
𝑘= 2 = =
(𝑉𝐺𝑆(𝑜𝑛) − 𝑉𝑇 ) (10 − 3)2 49𝑉 2
𝐴
= 0.061 × 10−3
𝑉2

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 QUESTIONS

1. Differentiate between enhancement & depletion type MOSFET

2. Discuss the difference between BJT and FET
3. Describe the drain curves and transfer curve of enhancement type Mode MOSFET.
4. Explain the structure of the depletion mode MOSFET and DMOSFET curves.
5. List the difference between
a) FET & BJT
b) E-MOSFET & D-MOSFET
c) JFET & MOSFET

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