Module-2
Fabrication
CMOS Fabrication And Layout
VLSI Design Flow
Introduction
CMOS Technologies
Layout design rules.
(1.5 and 3.1 to 3.3 TEXT 2).
MOSFET Scaling and Small-Geometry Effects
MOSFET Capacitances
(3.5 to 3.6 of TEXT 1)
CMOS Fabrication and Layout
• How the transistors are built.
• Designers need to understand the physical implementation of circuits
because it has a major impact on performance, power, and cost.
• Transistors are fabricated on thin silicon wafers that serve as both a
mechanical support and an electrical common point called the substrate.
• We can examine the physical layout of transistors from two perspectives.
One is the top view, obtained by looking down on a wafer.
• The other is the cross-section, obtained by slicing the wafer through the
middle of a transistor and looking at it edgewise.
• We begin by looking at the cross-section of a complete CMOS inverter.
• We then look at the top view of the same inverter and define a set of masks
used to manufacture the different parts of the inverter.
• The size of the transistors and wires is set by the mask dimensions and is
limited by the resolution of the manufacturing process.
• Continual advancements in this resolution have fueled the exponential
growth of the semiconductor industry.
Inverter Cross-Section
Fabrication Process
Fabrication Process Bare
substrate
Grow a protective
layer of oxide
The wafer is first oxidized
in a high-temperature
(typically 900–1200 °C)
furnace that causes Si and
O2 to react and become
SiO2 on the wafer surface
An organic
photoresist that
softens where
exposed to light is
spun onto the wafer
The softened
photoresist is
removed to
expose the oxide
The oxide is etched
with hydrofluoric
acid (HF) where it
is not protected by
the photoresist
The remaining
photoresist is stripped
away using a mixture
of acids called piranha
etch
Two ways to add
dopants are
diffusion and ion
implantation.
In the diffusion process, the wafer is placed in a furnace with a gas containing the dopants.
When heated, dopant atoms diffuse into the substrate.
With ion implantation, dopant ions are accelerated through an electric field and blasted into the
substrate.
Polycrystalline silicon.
Then the wafer is placed in a
reactor with silane gas (SiH4)
and heated again to grow the
polysilicon layer through a
process called chemical vapor
deposition.
The wafer is patterned with
photoresist and the
polysilicon mask (Figure
1.35(c)), leaving the
polysilicon gates atop the thin
gate oxide (Figure 1.37(b)).
Finally, the protective oxide
is stripped
Fabrication Process
Layout Design Rules
• Layout design rules describe how small features can be and
how closely they can be reliably packed in a particular
manufacturing process.
• Industrial design rules are usually specified in microns.
• This makes migrating from one process to a more advanced
process or a different foundry’s process difficult because not all
rules scale in the same way
• Mead and Conway [Mead80] popularized scalable design rules
based on a single parameter, , that characterizes the
resolution of the process.
• is generally half of the minimum drawn transistor channel
length.
Layout Design Rules
• For example, a 180 nm process has a minimum polysilicon width
(and hence transistor length) of 0.18 m and uses design rules
with = 0.09 m.
• Lambda-based rules are necessarily conservative because they
round up dimensions to an integer multiple of .
• Designers often describe a process by its feature size.
• Feature size refers to minimum transistor length, so is half the
feature size.
• A conservative but easy-to-use set of design rules for layouts
with two metal layers in an n-well process is as follows:
• Metal and diffusion have minimum width and spacing of 4 .
• Contacts are 2 × 2 and must be surrounded by 1 on the
layers above and below.
• Polysilicon uses a width of 2 .
Layout Design Rules
• Polysilicon overlaps diffusion by 2 where a transistor is
desired and has a spacing of 1 away where no transistor is
desired.
• Polysilicon and contacts have a spacing of 3 from other
polysilicon or contacts.
• N-well surrounds pMOS transistors by 6 and avoids nMOS
transistors by 6 .
Layout Design Rules
Layout Design Rules
In a 0.6 m process, this corresponds to an actual width of 1.2 m
and a length of 0.6 m.
• The power and ground lines are often called supply
Gate Layouts rails. Polysilicon lines run vertically to form
transistor gates. Metal wires within the cell connect
the transistors
• appropriately.
Stick Diagrams
• Because layout is time-consuming, designers need fast ways to
plan cells and estimate area before committing to a full layout.
• Stick diagrams are easy to draw because they do not need to be
drawn to scale.
Stick Diagrams
Stick Diagrams
Stick Diagrams