Parity Bit Generator and Checker
Name of The Student: - Siddharth Sankar Das (Regd. No.: -2301298697)
Name of The Student: - Bipad Bhanjan Panda (Regd No.: -2301298664)
Department: - Electronics & Communication Engineering
Guided By: - Prof. Jharana Behera
Introduction:
In digital communication systems, data integrity is a critical requirement. During transmission,
data can be affected by noise, interference, or other errors, leading to incorrect or corrupted
information reaching the receiver. To address this challenge, error detection mechanisms are
employed to identify any inaccuracies in the transmitted data. One of the simplest and most
widely used techniques is the parity check.
A Parity Bit Generator and Checker is a system designed to generate and validate parity bits to
ensure data integrity. The parity bit is an additional bit added to a data sequence to make the
total number of 1s in the sequence either even or odd, depending on the type of parity chosen.
Material:
Component Quantity Purpose
Used to calculate parity (even
XOR gate 2-4 or odd) by performing bitwise
XOR operations on input bits.
Additional logic gates to
AND, OR, NOT Gates 1 each create control logic for the
circuit, depending on design
needs.
Selects input data sources if
Multiplexer (MUX) 1 using multiple inputs in the
project.
Stores the parity bit in
D Flip-Flop 1 sequential circuits or holds
the state of the generated
parity bit.
Provides clock signal for
Oscillator 1 synchronous operations,
ensuring timing accuracy in
flip-flops.
Microcontroller 1 (Optional) Automates parity
calculation, checking, and
control logic (e.g., Arduino,
8051).
Methods:
1. Define Requirements:
o Determine the parity type (even or odd) and the number of input bits (e.g., 4-bit, 8-
bit).
o Choose between a hardware-based (logic gates) or microcontroller-based approach.
2. Design Circuit Logic:
o Use XOR gates for parity generation. XOR gates toggle based on the number of "1"s,
making them ideal for parity calculation.
o For even parity, configure the circuit to output "1" if there’s an odd number of "1"s
and "0" otherwise.
3. Construct the Parity Generator Circuit:
o Arrange XOR gates to process input bits, with the final output as the parity bit.
o Display the generated parity bit using an LED or seven-segment display.
4. Implement the Parity Checker:
o Use another XOR circuit to check the received data (including parity bit). If the
output is "0," the data is valid; otherwise, an error is detected.
5. Add User Interface:
o Use switches or a keypad for binary data input and LEDs for output display.
6. Test and Verify:
o Input various data values, check the parity, and verify correct error detection.
Keywords:
A. Input Data Lines
B. Parity Logic Circuit
C. Parity Bit Output
D. Output Data Line
E. Received Data with Parity
F. Parity Check Logic
G. Error Detection Output
H. Optional Correction Logic
Activities Duration (in Days)
Collection of Materials 5
Assembling of Parts 8
Testing of the Product 8
Closure & Report 9
Writing
Is it a product: Yes
Product Type: Physical Working Model
References:
"Digital Design" by M. Morris Mano and Michael D. Ciletti
"Fundamentals of Digital Logic with VHDL Design" by Stephen Brown and Zvonko
Vranesic
"Digital Principles and Applications" by Donald P. Leach, Albert Paul Malvino, and
Goutam Saha
"Error Detection and Correction Codes: Theory and Applications" by Shu Lin and Daniel
J. Costello