Chapter 15 Frequency Dividers

A frequency divider inputs a signal with a certain frequency f and outputs a

signal with the frequency f where n is an integer.. The simplest kind of
n
frequency dividers is a divide by 2 frequency divider. In this circuit, the frequency is
halved. We introduced such a concept in Chapter 14. We will introduce many other
frequency dividers in this chapter.

15-1
Section 15.1 A Divide by 2 Frequency Divider

In this section, we shall introduce a divide by 2 frequency divider We will use a

D-Flip Flop circuit. The output Q .terminal is connected back to the output terminal
D as shown in Fig. 15.1-1. As we can see, the only input is the clock signal. In
other words, the signal at the output terminal Q is the clock signal with its frequency
halved.

D D Q Q

CLK Q Qb

CLK

Fig. 15.1-1 The schematic diagram of a divide by 2 frequency divider

We shall use the D-Flip Flop introduced in Chapter 14. The divide by 2
frequency divider circuit diagram is now shown in Fig. 15.1-2

R1

VDD 10n

VDD VDD VDD

M2_p1

M1_p1 M3_p1 M4_p1

tsp2

tsp1 M2_p2 Qb Q

CLK M1_p2 CLK M3_n1

D CLK N3 M4_n1
N2
M2_n1 tsp4
M1_n1
M3_n2
tsp3

M2_n2

Fig. 15.1-2 A divide by 2 frequency divider circuit using

a single clock D-Flip Flop

15-2
Experiment 15.1-1 A Divide by 2 Frequency Divider: Experiment

In this experiment, we used the circuit shown in Fig. 15.1-2. The program is in
Table 15.1-1 and the result is in Fig. 15.1-3. As indicated in Table 15.1-1, we set
Q to be high initially.

Table 15.1-1 Program for Experiment 15.1-1

Experiment 15.1-1
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post

VDD VDD 0 3.3V

VSS VSS 0 0V

M1_p1 tsp1 D VDD VDD PCH W=3u L=0.35u

M1_p2 N2 CLK tsp1 VDD PCH W=3u L=0.35u
M1_n1 N2 D VSS VSS NCH W=1u L=0.35u

M2_p1 tsp2 N2 VDD VDD PCH W=3u L=0.35u

M2_p2 N3 CLK tsp2 VDD PCH W=3u L=0.35u
M2_n1 N3 CLK tsp3 VSS NCH W=1u L=0.35u
M2_n2 tsp3 N2 VSS VSS NCH W=1u L=0.35u

M3_p1 Qb N3 VDD VDD PCH W=3u L=0.35u

M3_n1 Qb CLK tsp4 VSS NCH W=1u L=0.35u
M3_n2 tsp4 N3 VSS VSS NCH W=1u L=0.35u

M4_p1 Q Qb VDD VDD PCH W=15u L=0.35u

M4_n1 Q Qb VSS VSS NCH W=5u L=0.35u

R1 Qb D 10n

Vclk CLK 0 pulse(0v 3.3v 2us 0.1us 0.1us 4.9us 10us)

.ic V(Qb)=3.3V
.tran 0.01ns 50us
.END

15-3
 CLK

N2

N3

Qb

Fig. 15.1-3 Experimental result of Experiment 15.1-1

From Fig. 15.1-3, we can see that the output signal is not correct. We first
analyze the initial conditions of the circuit which is shown in Fig. 15.1-4

R1

VDD 10n

VDD VDD VDD

M2_p1

M1_p1 M3_p1 M4_p1

tsp2

tsp1 M2_p2 Qb Q
1 0
CLK M1_p2 CLK M3_n1
D 0 CLK N3 M4_n1
0 1 0
1 N2
0 M2_n1 tsp4
M1_n1
M3_n2
tsp3

M2_n2

Fig. 15.1-4 The initial conditions of the circuit in Experiment 15.-1

We then enlarge the output signals around t  2 as shown in Fig. 15.1-5

15-4
 CLK

N2

N3

Qb

Fig. 15.1-5 Fig. 15.1-3 enlarged around t  2

Consider Inverter 3. As the clock rises slightly, the following events happen:

(1) Q falls slightly.

(2) Q is fed back to Stage 1 and causes N 2 to rise sharply because Stage 1 atcs
like an inverter.
(3) Since N 2 and the clock signals are both low, Stage 2 acts as an inverter
and N 3 starts to fall slightly.
(4) Q rises slightly.

From the above discussion, we can see that Q oscillates. This is called the
racing phenomenon. We can see that this is caused by the slow rising of the clock.
If the clock rises sharply, Q will fall sharply and this is ideal because for a
frequency divider, we like the output to change state when and only when the clock
rises.

To solve the racing problem, we may connect two inverters to the output of the
clock so that the rise and fall times are both rather short as shown in Fig. 15.1-6.
The circuit diagram is shown in Fig. 15.1-7.

15-5
 R1

10n

Qb Q
D Q
CLK_in 2 1 2 1 CLK
CLK Q
NOT NOT
DFF
Fig. 15.1-6 The divide by 2 frequency divider with
two inverters added after the clock

R1

VDD 10n

VDD VDD VDD

M2_p1

M1_p1 M3_p1 M4_p1

tsp2

tsp1 M2_p2 Qb Q

CLK M1_p2 CLK M3_n1

D CLK N3 M4_n1
N2
M2_n1 tsp4
M1_n2
M3_n2
tsp3

M2_n2

VDD VDD

Mc_p1 Mc_p2

CLK_IN CLK_INV CLK

Mc_n1 Mc_n2

Fig. [Link] divide by 2 frequency divider with two inverters added after the clock

Experiment 15.1-2 Experiment with the Divide by 2 Frequency Divider with

Two Inverters Added after the Clock

In this experiment, the circuit is as show in Fig. 15.1-7. The program in Table
15.1-2 and the result is in Fig. 15.1-8 which is correct.

Table 15.1-2 Program for Experiment 15.1-2

Experiment 15.1-2
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT

15-6
.options nomod post

VDD VDD 0 3.3V

VSS VSS 0 0V

Mc_p1 CLK_INV CLK_IN VDD VDD PCH W=3u L=0.35u

Mc_n1 CLK_INV CLK_IN VSS VSS NCH W=1u L=0.35u
Mc_p2 CLK CLK_INV VDD VDD PCH W=15u L=0.35u
Mc_n2 CLK CLK_INV VSS VSS NCH W=5u L=0.35u

M1_p1 tsp1 D VDD VDD PCH W=3u L=0.35u

M1_p2 N2 CLK tsp1 VDD PCH W=3u L=0.35u
M1_n1 N2 D VSS VSS NCH W=1u L=0.35u

M2_p1 tsp2 N2 VDD VDD PCH W=3u L=0.35u

M2_p2 N3 CLK tsp2 VDD PCH W=3u L=0.35u
M2_n1 N3 CLK tsp3 VSS NCH W=1u L=0.35u
M2_n2 tsp3 N2 VSS VSS NCH W=1u L=0.35u

M3_p1 Qb N3 VDD VDD PCH W=3u L=0.35u

M3_n1 Qb CLK tsp4 VSS NCH W=1u L=0.35u
M3_n2 tsp4 N3 VSS VSS NCH W=1u L=0.35u

M4_p1 Q Qb VDD VDD PCH W=15u L=0.35u

M4_n1 Q Qb VSS VSS NCH W=5u L=0.35u

R1 Qb D 10n

Vclk CLK_IN 0 pulse(0v 3.3v 2us 0.1us 0.1us 4.9us 10us)

.ic V(Qb)=3.3V
.tran 0.01ns 50us
.END

15-7
 CLK

N2

N3

Q_bar

Fig. 15,1-8 The result of Experiment 15.1-1

Although the circuit works as a divide by 2 frequency divider, we still should pay
attention to the time around t  11s when the clock rises for the second time.
Note that in Fig. 15.1-5, at this moment, the clock is high while N2 is low.
Theoretically, N3 should be floating and thus should remain to be high. Yet, it
becomes low. To investigate this we enlarge the figure around t  11s as shown
in Fig. 15.1-9.

15-8
 Fig. 15.1-9 Fig. 15.1-5 enlarged around t  11s

From Fig. 15.1-9, we can see that the clock rises rather quickly to 1.2V which is
high enough for the PMOS M2-p1. N2 is high at this moment. Thus both clock
and N2 are high. Stage 2 acts like an inverter and N3 therefore starts to drop. This
in turn causes Q to drop sharply which is ideal.

The reader is hereby encouraged to compare Fig. 15.1-9 and Fig. 15.1-5. In Fig.
15.1-5, we can see that the clock signal rises, but too slowly. Q does drop, but
rather slowly. This causes the racing which must be avoided.

15-9
Section 15.2 Divide by 3 by Counting, Synchronous
Divide-by-3 Up Counter
In this sction, we shall introduce a divide by 3 frequency divider. This is a
synchronous divider as a clock signal is sent to two D-flip flops In addition to two
flip flops, there is a NOR gate. The circuit diagram is shown in Fig. 15.2-1 and an
illustration of its performance is in Fig. 15.2-2. It can be shown that this circuit is a
divide by3 frequency divider.

2
1 Q_A Q_B
3 NOR D Q D Q

CLK Q CLK Q

DFF_A DFF_B
CLK
Fig. 15.2--1 Synchronous Divide-by-3 Up Counter

CLK

DA

QA 0 1 0 0 1 0 0 1

QbA

QB 0 0 1 0 0 1 0 0

QbB

Count
0 1 2 0 1 2 0 1
Fig. 15.2-2 The performance of the circuit in Fig. 15.2-1

Let us now try to explain why this circuit works.

(1) Initially, CLK, QA and QB are all assumed to be 0 to start with. Therefore DA is
1..

(2) At [Link] first time CLK goes up. QA changes state to become 1 because DA
was 1 before. QB remains to be 0 because QA was 0 before. DA remains to be 0

15-10
because QA, one of the input signal to the NOR gate, is 1.

(3) At t2, the second time the clock goes up, QA becomes 0 because DA was 0 before
and QB becomes 1 because QA was 1 before. Therefore DA remains to be 0 because
QB ,one of the input signal to the NOR gate, is 1.

(4) At t3, the third time the clock goes up, QA remains to be 0 and QB changes to
become 0. Since both QA and QB are 0, DA becomes 1.

(5) At t4, the fourth time the clock goes up, QA changes to 1 because DA was1before
and QB remains to be 0 because . QA was 0 before. DA becomes 0 because . QA one
of the input signal to the NOR gate, is 1

(6) At t5, the fifth time the clock goes up, both QA and QB change states. QB rises to
become 1.

As one can see, the output of the circuit, namely QB remains to be in the same
state from t3 to t5. From t2 to t5, the input clock has four periods. But the output QB
has only three periods. Thus the circuit is a divide by 3 frequency divider.. We
admit that for the entire cycle consisting three periods, the high period time duration
is not equal to the low period duration. This is admissible for most applications.

Let us now try to explain why this is a divide by 3 frequency divider. The key
point is that QB is 0 from t3 to t4 and continues to be 0 from t4 to t5. If it is not so,
this circuit will not be a divide by 3 divider.. In the following, we shall explain why
QB continues to be 0 from t4 to t5.

(1) QB is 0 from t4 to t5 is due to the fact that QA is 0 from t3 to t4.

(2) QA is 0 from t3 to t4 because DA is 0 from t2 to t3.

(3) DA is 0 from t2 to t3 because QB, an input to the NOR gate, is 1 from t2 to t3.

From the above discussion, we can see that the NOR gate plays a critical role in
the divide by 3 frequency divider.

Experiment 15.2-1 An Experiment for the Divide by 3 Frequency Divider.

In this experiment, we tested a divide by 3 frequency divider based upon the

above discussion. The circuits are shown from Fig. 15.2-3 to Fig. 15.2-5. The
program is in Table 15.2-1 and the testing result is in Fig. 15.2-6. As can seen, the
circuit works.

15-11
 VDD

VDD VDD VDD

M2_p1

M1_p1 M3_p1 M4_p1

tsp2

tsp1 M2_p2 Qb Q

CLK M1_p2 CLK M3_n1

D CLK N3 M4_n1
N2
M2_n1 tsp4
M1_n1
M3_n2
tsp3

M2_n2

Fig. 15.2-3 The D Flip-Flop Subcircuit for Experiment 15.2-1

VDD

no_A Mo_p1

no_1

no_B Mo_p2

no_out

no_A Mo_n1 no_B Mo_n2

Fig. 15.2-4 NOR Gate Subcircuit for Experiment 15.2-1

15-12
 NOR Gate
Da Qa Db Qb

CLK CLK

TSPC DFFs_A TSPC DFFs_B

CLK in CLK input

inverter
Fig. 15.2-5 The circuit diagram of the divide by 3 frequency divider
for Experiment 15.2-1

VDD
VDD
VDD VDD VDD
M2_p1
Q_A
Mo_p1
M1_p1 tsp2 M3_p1 M4_p1
no_1
Q_B tsp1 M2_p2 Qb_A Q_A
Mo_p2
CLK M1_p2 CLK N3 CLK M3_n1 M4_n1
D_A
N2 M2_n1 tsp4
Mo_n1 Mo_n2
M1_n1 tsp3 M3_n2

M2_n2

VDD

VDD VDD VDD

M2_p1

M1_p1 tsp2 M3_p1 M4_p1

tsp1 M2_p2 Qb_B Q_B

CLK M1_p2 CLK N3 CLK M3_n1 M4_n1

D_B
N2 M2_n1 tsp4
VDD VDD
M1_n1 tsp3 M3_n2

M2_n2
Mc_p1 Mc_p2

CLK_IN CLK_INV CLK

Mc_n1 Mc_n2

Table 15.2-1 The program for Experiment 15.2-1

Experiment 15.2-1
.op
.OPTION POST

15-13
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global vdd vss
.param clk_freq = 1e6

VDD VDD 0 3.3V

VSS VSS 0 0V

Mc_p1 CLK_INV CLK_IN VDD VDD PCH W=3u L=0.35u

Mc_n1 CLK_INV CLK_IN VSS VSS NCH W=1u L=0.35u
Mc_p2 CLK CLK_INV VDD VDD PCH W=15u L=0.35u
Mc_n2 CLK CLK_INV VSS VSS NCH W=5u L=0.35u

.subckt TSPC D clk Qb Q

M1_p1 tsp1 D VDD VDD PCH W=3u L=0.35u
M1_p2 N2 CLK tsp1 VDD PCH W=3u L=0.35u
M1_n1 N2 D VSS VSS NCH W=1u L=0.35u

M2_p1 tsp2 N2 VDD VDD PCH W=3u L=0.35u

M2_p2 N3 CLK tsp2 VDD PCH W=3u L=0.35u
M2_n1 N3 CLK tsp3 VSS NCH W=1u L=0.35u
M2_n2 tsp3 N2 VSS VSS NCH W=1u L=0.35u

M3_p1 Qb N3 VDD VDD PCH W=3u L=0.35u

M3_n1 Qb CLK tsp4 VSS NCH W=1u L=0.35u
M3_n2 tsp4 N3 VSS VSS NCH W=1u L=0.35u

M4_p1 Q Qb VDD VDD PCH W=15u L=0.35u

M4_n1 Q Qb VSS VSS NCH W=5u L=0.35u
.ends TSPC

*NOR
.subckt NOR no_a no_b no_out
Mo_p1 no_1 no_a vdd vdd pch W=3u L=0.35u
Mo_p2 no_out no_b no_1 vdd pch W=3u L=0.35u
Mo_n1 no_out no_a vss vss nch W=1u L=0.35u
Mo_n2 no_out no_b vss vss nch W=1u L=0.35u
.ends NOR

.ic v(Qb_A)=3.3v v(Qb_B)=3.3v

xTSPC_A D_A clk Qb_A Q_A TSPC

xTSPC_B Q_A clk Qb_B Q_B TSPC
xNOR Q_A Q_B D_A NOR

Vclk CLK_IN vss pulse(0v 3.3v '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'

'0.4875/clk_freq' '1/clk_freq')

15-14
.tran '1/(10000*clk_freq)' '(9/clk_freq)'
.END

CLK

D_A

Q_A 0 1 0 0 1 0 0 1 0

Q_B 0 0 1 0 0 1 0 0 1

Fig. 15.2-6 The result of 15.2-1

15-15
Section 15.3 Synchronous Divide by 4 Johnson Counter
Frequency Divider
In this section, we shall introduce a synchronous divide 4 frequency divider It is
said to be synchronous because the clock signal is fed to both D Flip-Flops as shown
in Fig. 15.3-1. This is based upon the Johnson Counter.

F_out
D Q D Q

CLK Q CLK Q

DFF_A DFF_B
CLK
Fig. 15.3-1 Synchronous Divide by 4 Johnson Counter

In this circuit, the following points must be noted:

(1) For D Flip-Flop A, DA  QB

(2) For D Flip-Flop B, DB  QA .

This means that the output of D Flip-Flop A follows the inverse of the D
Flip-Flop B. We now explain why the circuit is a divide by 4 frequency divider.

(1) Assume that initially, Clock, QA and QB are all 0 to start with. This means that
DA  QB  1 initially.

(2) When the Clock goes up for the first time, QA will become 1 because QA follows
DA and DA  QB  1 previously.

(3) Because DB  QA , QB will remain to be 0 because QB follows

DB  Q A  0 .previously. This means that QB remains to be 1

(4) When the Clock goes up for the second time, QA will remain to be 1 because it
follows DA  QB and DA  QB is not changed.. Since QB follows DB  QA , QB
becomes 1 and QB becomes 0.

(5) When the Clock goes up for the third time, QA will drop to be 0 because it
follows DA  QB and QB  0 previously.. QB will remain to 1 as it follows
DB  QA and QA was 1 previously.

The above discussion is illustrated in Fig. 15.3-2.

15-16
 CLK

D_A

Q_A

Q_B

Fig. 15.3-2 An illustration of how the divide by 4 frequency divider

depicted in Fig. 15.3-1 works

Experiment 15.3-1 An Experiment of the Divide by 4 Johnson Connection

Frequency Divider

The circuit of the experiment is shown in Fig. 15.3-3. The program is in Table
15.3-1 and the result is in Fig. 15.3-3.

15-17
 VDD

VDD VDD VDD

M2_p1

M1_p1 tsp2 M3_p1 M4_p1

tsp1 M2_p2 Qb_A Q_A

CLK M1_p2 CLK N3 CLK M3_n1 M4_n1

D_A
N2 M2_n1 tsp4

M1_n1 tsp3 M3_n2

M2_n2

VDD

VDD VDD VDD

M2_p1

M1_p1 tsp2 M3_p1 M4_p1

tsp1 M2_p2 Qb_B Q_B

CLK M1_p2 CLK N3 CLK M3_n1 M4_n1

D_B
N2 M2_n1 tsp4
VDD VDD
M1_n1 tsp3 M3_n2

M2_n2
Mc_p1 Mc_p2

CLK_IN CLK_INV CLK

Mc_n1 Mc_n2

Fig. 15.3-3 The circuits for Experiment 15.3-1

Table 15.3-1 Program for experiment 15.3-1

Experiment 15.3-1
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global vdd vss
.param clk_freq = 1e6

VDD VDD 0 3.3V

VSS VSS 0 0V

Mc_p1 CLK_INV CLK_IN VDD VDD PCH W=3u L=0.35u

Mc_n1 CLK_INV CLK_IN VSS VSS NCH W=1u L=0.35u
Mc_p2 CLK CLK_INV VDD VDD PCH W=15u L=0.35u
Mc_n2 CLK CLK_INV VSS VSS NCH W=5u L=0.35u

.subckt TSPC D clk Qb Q

M1_p1 tsp1 D VDD VDD PCH W=3u L=0.35u
M1_p2 N2 CLK tsp1 VDD PCH W=3u L=0.35u

15-18
M1_n1 N2 D VSS VSS NCH W=1u L=0.35u

M2_p1 tsp2 N2 VDD VDD PCH W=3u L=0.35u

M2_p2 N3 CLK tsp2 VDD PCH W=3u L=0.35u
M2_n1 N3 CLK tsp3 VSS NCH W=1u L=0.35u
M2_n2 tsp3 N2 VSS VSS NCH W=1u L=0.35u

M3_p1 Qb N3 VDD VDD PCH W=3u L=0.35u

M3_n1 Qb CLK tsp4 VSS NCH W=1u L=0.35u
M3_n2 tsp4 N3 VSS VSS NCH W=1u L=0.35u

M4_p1 Q Qb VDD VDD PCH W=15u L=0.35u

M4_n1 Q Qb VSS VSS NCH W=5u L=0.35u
.ends TSPC

.ic v(Qb_A)=3.3v v(Qb_B)=3.3v

xTSPC_A D_A clk Qb_A Q_A TSPC

xTSPC_B Q_A clk D_A Q_B TSPC

Vclk CLK_IN vss pulse(0v 3.3v '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'

'0.4875/clk_freq' '1/clk_freq')

.tran '1/(10000*clk_freq)' '(9/clk_freq)'

.END

CLK

Q_A

Q_B

Fig. 15.3-3 The result of Experiment 15.3-1

15-19
Section 15.4 Asynchronous Divide-by-4 Frequency Divider

Fig. 15.4-1 shows an synchronous divide by 4 frequency divider. It is asynchronous

because the clock is only fed into the first D Flip-Flop. For the second D Flip-Flop,
its clock is Q A . Each D flip-flop is connected as a 2 frequency divider. Since two
D Flip-Flops are connected in serial, the whole circuit behaves like a divide by 4
frequency divider.

F_out
D Q D Q
CLK
CLK Q CLK Q

DFF_A DFF_B
Fig. 15.4-1 Asynchronous divide-by-4 frequency divider

Experiment 15.4-1

VDD

VDD VDD VDD

M2_p1

M1_p1 tsp2 M3_p1 M4_p1

tsp1 M2_p2 Qb_A Q_A

CLK M1_p2 CLK N3 CLK M3_n1 M4_n1

D_A
N2 M2_n1 tsp4
VDD VDD
M1_n1 tsp3 M3_n2

M2_n2
Mc_p1 Mc_p2

CLK_IN CLK_INV CLK

Mc_n1 Mc_n2 VDD

VDD VDD VDD

M2_p1

M1_p1 tsp2 M3_p1 M4_p1

tsp1 M2_p2 Qb_B Q_B

Q_A M1_p2 Q_A N3 Q_A M3_n1 M4_n1

D_B
N2 M2_n1 tsp4

M1_n1 tsp3 M3_n2

M2_n2

Fig. 15.4-1 The circuits for Experiment 15.4-1

Table 15.4-1 Program for Experiment 15.4-1

Experiment 15.4-1
.op

15-20
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global vdd vss
.param clk_freq = 1e6

VDD VDD 0 3.3V

VSS VSS 0 0V

Mc_p1 CLK_INV CLK_IN VDD VDD PCH W=3u L=0.35u

Mc_n1 CLK_INV CLK_IN VSS VSS NCH W=1u L=0.35u
Mc_p2 CLK CLK_INV VDD VDD PCH W=15u L=0.35u
Mc_n2 CLK CLK_INV VSS VSS NCH W=5u L=0.35u

.subckt TSPC D clk Qb Q

M1_p1 tsp1 D VDD VDD PCH W=3u L=0.35u
M1_p2 N2 CLK tsp1 VDD PCH W=3u L=0.35u
M1_n1 N2 D VSS VSS NCH W=1u L=0.35u

M2_p1 tsp2 N2 VDD VDD PCH W=3u L=0.35u

M2_p2 N3 CLK tsp2 VDD PCH W=3u L=0.35u
M2_n1 N3 CLK tsp3 VSS NCH W=1u L=0.35u
M2_n2 tsp3 N2 VSS VSS NCH W=1u L=0.35u

M3_p1 Qb N3 VDD VDD PCH W=3u L=0.35u

M3_n1 Qb CLK tsp4 VSS NCH W=1u L=0.35u
M3_n2 tsp4 N3 VSS VSS NCH W=1u L=0.35u

M4_p1 Q Qb VDD VDD PCH W=15u L=0.35u

M4_n1 Q Qb VSS VSS NCH W=5u L=0.35u
.ends TSPC

.ic v(Qb_A)=3.3v v(Qb_B)=3.3v

xTSPC_A Qb_A clk Qb_A Q_A TSPC

xTSPC_B Qb_B Q_A Qb_B Q_B TSPC

Vclk CLK_IN vss pulse(0v 3.3v '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'

'0.4875/clk_freq' '1/clk_freq')

.tran '1/(10000*clk_freq)' '(9/clk_freq)'

.END

15-21
CLK

Q_A

Q_B

Fig. 15.4-3 The result of Experiment 15.4-1

15-22
Section 15.5 A New Single Clock D-Flip Flop

The new single clock D Flip-Flop is now shown in Fig. 15.5-1. As can be seen, the
new circuit employs only three. instead of four, transistors in the second stage. The
top and bottom transistors are all controlled by the clock signal and the middle
transistor is controlled by the N2 signal coming out of Stage 1.

VDD VDD VDD

M1_p1 CLK M2_p1 M3_p1

tsp1 N3 Qb

CLK M1_p2 N2 M2_n1 CLK M3_n1

D

tsp2 tsp3

M1_n1 CLK M2_n2 M3_n2

Fig. 15.5-1 The new single clock D Flip-Flop

Since the new and old single clock D Flip-Flops are different only on the second
stage, we now display the second stages of the two circuits in Fig. 15.5-2

VDD

VDD

M2 _ p 1

CLK M2_p1 tsp2

M2 _ p 2
N3
CLK N3
N2 M2_n1 N2
M2 _ n 1

tsp2
tsp3
CLK M2_n2
M2 _ n 2

New Old
Fig. 15.5-2 The second stages of the new and old D Flip-Flops

Let us now analyze the new second stage circuit.

Case 1: Clock is high. In this case, the top transistor is cut off and the bottom

15-23
transistor can be conducting..

Case 1a: N2 is high. In this case, the inputs of the two NMOS transistors are
both high and therefore the output N3 is low.

Case 1b: N2 is low. In this case, the middle transistor is cutoff. Since both the
top and bottom transistors are cutoff, the output N3 is floating.

Case 2: Clock is low. In this case, the top transistor is on and the output N3 is
therefore high.

The performances of the two stages are illustrated in Table 15.5-1

Table 15.5-1 The performances of the second stages of the new and old circuits
N2 CLK N3 N2 CLK N3
1 1 0 1 1 0
0 1 floating 0 1 floating
1 0 1 1 0 floating
0 0 1 0 0 1

If we compare the performances of these two stages, we notice that there is only
difference. It occurs when N2 is high and the clock is low. For this case, N3 will
be high for the new circuit while it is floating for the old circuit.

If N3 is high, M3-p1 will be cutoff. If the clock has not fallen to zero, both
M3-n1 and M3-n2 are open. Thus Qb will not be floating as shown in Fig. 15.5-3
It will become low which is not desirable.

VDD VDD VDD

M1_p1 CLK M2_p1 M3_p1

tsp1 N3 Qb

CLK M1_p2 N2 M2_n1 CLK M3_n1

D

tsp2 tsp3

M1_n1 CLK M2_n2 M3_n2

Fig. 15.5-3 The entire circuit when N3 is high

This problem can be avoided by having a sharp clock rise and fall. Suppose the
clock falls sharply, M3-n1 will be open. Qb will therefore be floating which makes
our circuit work. To have a sharp colck, we simply add two inveters after the clock.

15-24
Experiment 15.5-1 The Testing of the New Single Clock D Flip-Flop

In this experiment, we used the circuit shown in Fig. 15.5-1 The program is in
Table 15.5-2 and the result is in Fig. 15.5-5. As indicated in Table 15.5-2, we set
Q to be high initially. From Fig. 15.5-5, we can see that this circuit is indeed a D
Flip-Flop as the output changes state only when the clock signal rises. Besides, the
output retains the state of the D signal before the clock rises.

VDD VDD VDD VDD

M1_p1 CLK M2_p1 M3_p1 M4_p1

tsp1 N3 Qb Q

CLK M1_p2 N2 M2_n1 CLK M3_n1

D M4_n1

tsp2 tsp3

M1_n1 CLK M2_n2 M3_n2

VDD VDD

Mc_p1 Mc_p2

CLK_IN CLK_INV CLK

Mc_n1 Mc_n2

Fig. 15.5-4 The circuit used in experiment 15.5-1

Table 15.5-2 Program for Experiment 15.5-1

Experiment X.1-1
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global VDD GND

.param l_nch = 0.35u

.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u
.param clk_freq = 1e6

*CLK input smooth

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*3'

15-25
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*1'
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*15'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*5'

*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*3'
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*3'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*1'

*Second stage
M2_p1 N3 clk vdd vdd pch L=l_pch W='w_pch*3'
M2_n1 N3 N2 tsp2 gnd nch L=l_nch W='w_nch*1'
M2_n2 tsp2 clk gnd gnd nch L=l_nch W='w_nch*1'

*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*3'
M3_n1 Qb clk tsp3 gnd nch L=l_nch W='w_nch*1'
M3_n2 tsp3 N3 gnd gnd nch L=l_nch W='w_nch*1'

*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*3'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*1'

.ic v(Qb)=3.3v

Vsupply VDD GND 3.3V

vclk_in clk_in gnd pulse (0 3.3 '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.4875/clk_freq' '1/clk_freq')
vdata D gnd pulse (0 3.3 '0.25/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'2*0.4875/clk_freq' '2*1/clk_freq')

.tran '1/(10000*clk_freq)' '(6/clk_freq)'

.END

15-26
 CLK

N2

N3

Qb

Fig. 15.5-5 The result of Experiment 15.5-1

We now take a look at Fig. 15.5-6 which shows the moment when N3 rises.
Since the clock falls sharply, M3-p1 is open because of the rising of N3 and M3-n1 is
also open because of the sharp falling of the clock. Therefore Qb is floating and this
is what we want.

CLK

N2

N3

Qb

15-27
 Fig. 15.5-6 A look at the time when N3 rises

Suppose we did not add the two inverters, the circuit works as shown in Fig.
15.5-7. This is not a D Flip-Flop circuit.

CLK

N2

N3

Qb

Fig. 15.5-7 The new circuit without two inverters

As shown in Fig. 15.5-8, if M3-n1 is not open because the clock rises too slowly,
This causes Qb to fall immediately which is not desirable.

15-28
 CLK

N2

N3

Qb

Fig. 15.5-8 A look at the moment of the circuit without two inverters added
when N3 rises

15-29
Section 15.6 A Divide by 8 Frequency Divider
Fig. 15.6-1 shows a schematic diagram of a divide by 8 frequency divider.
There are three D-Flip Flops. For each D-Flip Flop, the Qb terminal is connected to
D so that the D-Flip Flop is actually a divide by 2 frequency divider. Besides, each
Qb is sent to the next D-Flip Flop as an input.

Q0 Q1 Q2

D Q D Q D Q

CLK Qb Qb Qb

DFF_0 DFF_1 DFF_2

Fig. 15.6-1 A divide by 8 frequency divider

Fig. 15.6-2 shows the circuit of the D-Flip Flop which was introduced before.
Note that the clock is connected to two inverters.

15-30
 VDD VDD VDD VDD

CLK
M1_p1 M2_p1 M3_p1 M4_p1

tsp1 N3 Qb Q

Qb
CLK N2 M2_n1 CLK M3_n1 M4_n1
M1_p2

tsp2 tsp3

M1_n1 CLK M2_n2 M3_n2

VDD VDD

Mc_p1 Mc_p2

CLK_in CLK_b CLK

Mc_n1 Mc_n2

Fig. 15.6-2 The D-Flip Flop used in Experiment 15.6-1

Experiment 15.6-1: A Divide by 8 Frequency Divider

The D-Flip Flop circuit is shown in Fig. 15.6-1. The program is in Table 15.6-1.
The result of the experiment is in Fig. 15.6-3. As can be seen, this is indeed a divide
by 8 frequency divider.

Table 15.6-1 Program for Experiment 15.6-1

Experiment X.1-1
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global VDD GND

.param l_nch = 0.35u

.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u
.param clk_freq = 1e6

*CLK input smooth

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*1.5'
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*0.5'

15-31
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*3'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*1'

.subckt TSPC D clk Qb Q

*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*1.5'
M1_p2 N1 clk tsp1 vdd pch L=l_pch W='w_pch*1.5'
M1_n1 N1 D gnd gnd nch L=l_nch W='w_nch*0.5'

*Second stage
M2_p1 N2 clk vdd vdd pch L=l_pch W='w_pch*1.5'
M2_n1 N2 N1 tsp2 gnd nch L=l_nch W='w_nch*0.5'
M2_n2 tsp2 clk gnd gnd nch L=l_nch W='w_nch*0.5'

*Third stage
M3_p1 Qb N2 vdd vdd pch L=l_pch W='w_pch*1.5'
M3_n1 Qb clk tsp3 gnd nch L=l_nch W='w_nch*0.5'
M3_n2 tsp3 N2 gnd gnd nch L=l_nch W='w_nch*0.5'

*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*1.5'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.5'
.ic Qb 0v
.ends TSPC

xTSPC0 Qb_0 CLK Qb_0 Q_0 TSPC

XTSPC1 Qb_1 Qb_0 Qb_1 Q_1 TSPC
xTSPC2 Qb_2 Qb_1 Qb_2 Q_2 TSPC

Vsupply VDD GND 3.3V

vclk clk_in gnd pulse (0 3.3 '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.4875/clk_freq' '1/clk_freq')

.tran '1/(10000*clk_freq)' '(16/clk_freq)'

.END

15-32
 CLK

Qb_0

Q_0

Qb_1

Q_1

Qb_2

Q_2

Fig. 15.6-3 The result of Experiment 15.6-1

Let us take a detailed look at Fig. 15.6-3 and see how Q0 ,Q1 and Q 2 behave
as shown in Fig. 15.6-4

CLK

Q_0 0 1 0 1 0 1 0 1 0 1

Q_1 0 0 1 1 0 0 1 1 0 0

Q_2 0 0 0 0 1 1 1 1 0 0

Fig. 15.6-4 The behavior of Q0 ,Q1 and Q 2

As expected, the behavior of Q 0 is (01010101), that of Q1 is (00110011) and

finally that of Q 2 is (00001111). We may summarize this as shown in Table 15.6-2

15-33
 Table 15.6-2 The behavior of Q0 ,Q1 and Q 2
Q2 Q1 Q0 Count
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7

From Table 15.6-2, we can see that Q0 ,Q1 and Q 2 behaves as a binary counter.
This observation is quite important because it will lead us to a programmable
frequency divider. For instance, suppose we want to have a divide by 5 counter, we
simply wait the Q0 ,Q1 and Q 2 to count to 4. We then try to reset the circuit. All
of these techniques will be discussed in the following sections.

15-34
Section 15.7 A New TSPC D-Flip Flop with Set and Reset
In the later sections, we will introduce programmable frequency divider . In this
kind of frequency dividers, we need D-Flip Flop’s with set and reset. Fig. 15.7-1
shows a D-Flip Flop circuit which we introduced before.

VDD VDD VDD VDD

M1_p1 CLK M2_p1 M3_p1 M4_p1

tsp1 N3 Qb Q

CLK M1_p2 N2 M2_n1 CLK M3_n1

D M4_n1

tsp2 tsp3

M1_n1 CLK M2_n2 M3_n2

Fig. 15.7-1 A D-Flip Flop which we introduced before

Let us focus on the period during which the clock is high. As expected, if the
clock is high, Stage 3 is an inverter. In other words, Qb will be always opposite to
N3 when the clock is high. This is illustrated in Fig. 15.7-2 We should also note
that when the clock is high, Stage 2 is an inverter and N2 and N3 are opposite to each
other.

For most applications, outside changes always occur when the clock is high.
We therefore may have a D-Flip Flop with set and reset based upon the assumption
that the outside changes occur when the clock is high. Under certain conditions, the
set and reset will also work.

15-35
 CLK

1
N2
0
1
N3 0

1
Qb 0

1
Q 0

Fig. 15.7-2 Fig. 15.6-1 focusing the periods when the clock is high

From the above discussion, we obtain the conditions for set and reset as shown in
Table 15.7-1. Note that we assume clock signal is high for the following table.

Table 15.7-1 Set and reset conditions for a D-Flip Flop

N2 N3 Qb Q
Set 0 1 0 1
Reset 1 0 1 0

Fig. 15.7-3 shows a new TSPC D-Flip Flop with set and reset

15-36
 VDD

VDD
M0p_set
VDD
w=3u
VDD set set_b M2p_set
set M1p_set w=1u
w=0.5u CLK M0n_set
tsp1 M2_p1 VDD VDD
w=1u
w=0.4u
M1_p1 tsp3
w=0.4u rst M3_p1 M4_p1
M2p_rst
tsp2 w=0.5u w=2u
w=0.4u
CLK M1_p2 N3 Qb Q
D
w=2u N2 CLK
M2_n1 M3_n1
M4_n1
w=2u w=0.4u
w=3u
M1_n3 tsp4 tsp5
w=2u CLK M2_n2 M3_n2
set w=8u w=0.4u
M1n_set
w=1u set M3n_set
w=1u
VDD VDD rst M2n_rst
w=1u

Mc_p1 Mc_p2
CLK_IN CLK_INV CLK

Mc_n1 Mc_n2

Fig. 15.7-3 A D-Flip Flop circuit with set and reset

Let us first note that in the last stage which is an inverter reversing Qb to Q, there
is a new NMOS transistor labeled as M3-set. A set signal is applied to the gate of
this transistor. If this set signal is high, it will force terminal Qb to be low and
terminal Q to be high.

Yet, this is not enough. When the set signal applied to M3-set, we know that
Qb will be low. Suppose N3 is also low, it will cause trouble. In other words, N3
must be high when the set signal is applied. Let us take a look at the inverter
consisting of transistors MOp-set and Mon-set. When the high set signal is applied
to this inverter, set-b will be low. This will cause N3 to be high which is required as
indicated in Table 15.7-1.

The same argument applies to transistors M1p-set and M1n-set. When a high
set signal is applied to these two transistors, it will cause N2 to be low which is again
required as shown in Table 15.7-1.

Experiment 15.7-1 Experiments of the D-Flip Flop with Set and Reset Circuit
in Fig. 15.7-3.

The program for this experiment is in Table 15.7-2.

Table 15.7-2 Program for Experiment 15.7-1

Experiment X.2-1-1
.op
.OPTION POST
.PROTECT

15-37
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global VDD GND

.param l_nch = 0.35u

.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u
.param clk_freq = 1e6
.param set_time = 10
.param rst_time = 10

*CLK input smooth

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*3'
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*1'
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*15'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*5'

*Set Signal
M0p_set set_b set vdd vdd pch L=l_pch W='w_pch*3'
M0n_set set_b set gnd gnd nch L=l_nch W='w_nch*1'
M1n_set N2 set gnd gnd nch L=l_nch W='w_nch'
M2p_set N3 set_b vdd vdd pch L=l_pch W='w_pch'
M3n_set Qb set gnd gnd nch L=l_nch W='w_nch'

*Reset Signal
M2n_rst N3 rst gnd gnd nch L=l_nch W='w_nch'

*First stage
M1p_set tsp1 set vdd vdd pch L=l_pch W='w_pch*0.5'
M1_p1 tsp2 D tsp1 vdd pch L=l_pch W='w_pch*0.4'
M1_p2 N2 clk tsp2 vdd pch L=l_pch W='w_pch*2'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*2'

*Second stage
M2_p1 tsp3 clk vdd vdd pch L=l_pch W='w_pch*0.4'
M2p_rst N3 rst tsp3 vdd pch L=l_pch W='w_pch*0.4'
M2_n1 N3 N2 tsp4 gnd nch L=l_nch W='w_nch*2'
M2_n2 tsp4 clk gnd gnd nch L=l_nch W='w_nch*8'

*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*0.5'
M3_n1 Qb clk tsp5 gnd nch L=l_nch W='w_nch*0.4'
M3_n2 tsp5 N3 gnd gnd nch L=l_nch W='w_nch*0.4'

*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*2'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*3'

15-38
.ic v(Qb)=3.3v

Vsupply VDD GND 3.3V

vclk_in clk_in gnd pulse (0 3.3 '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.4875/clk_freq' '1/clk_freq')
vdata D gnd pulse (0 3.3 '0.25/clk_freq''0.025/clk_freq' '0.025/clk_freq'
'2.4*0.4875/clk_freq' '2.4*1/clk_freq')
vset set gnd pulse (0 3.3 'set_time/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.01*0.4875/clk_freq' '10*1/clk_freq')
vrst rst gnd pulse (0 3.3 'rst_time/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.01*0.4875/clk_freq' '10*1/clk_freq')

.tran '1/(100000*clk_freq)' '(6/clk_freq)'

.END

.param set_time = 2.8

CLK
D
Set
Reset
N2
N3
Qb
Q

Fig. 15.7-4 Set = 1 at T=2.8us

.param rst_time = 0.8

15-39
CLK
D
Set
Reset
N2
N3
Qb
Q

Fig. 15.7-5 Reset = 1 at T=0.8us

15-40
Section 15.8 A 3 Bit Programmable K-Fout System Based
upon a Frequency Divider

In this section, we will introduce a programmable fout system. We are

given a clock. Our system has to send out a exceedingly short pulse
whenever k periods of the clock have passed. We call such a system a
K-Fout system. The performance of a 5-Fout system is illustrated in Fig.
15.8-1.

Fig. 15.8-1 An illustration of a 5-Fout system

In Section 15.8, we introduced a divide by 8 frequency divider. We indicated that

the output terminals Q0 ,Q1 and Q 2 can be considered as a counter. In Section
15.7, we introduced a D-Flip Flop with set and reset signals. Combining these two
sections, we may have a 3-bit programmable frequency divider. Since we only use 3
D-Flip Flops, 1  k  7 . Whenever Q0 ,Q1 and Q 2 count to k, our system,
through the circuit consisting of XOR and NOR gates, sends out a rest signal. We
will explain why this reset signal is exceedingly short.

Fig. 15.8-1 shows the schematic diagram of a 3 bit programmable k-fout system.
We can see that we have added three constant voltage signals to the circuit. They are
n0, n1 and n2. Since we are designing a 5-Fout frequency divider, we set (n2,n1,n0) to
be (1,0,1). Suppose (Q2,Q1,Q0) reaches (101), we can see that all of the three XOR
gates will output 0. Thus the NOR gate will output 1. That is, a reset signal will be
sent out. We will see later why this reset signal is a short pulse.

15-41
 Q0 Q1 Q2

D Q D Q D Q
DFF_0 DFF_1 DFF_2
CLK Qb Qb Qb
R R R

n0
XOR
Q0

n1 Fout F_out
XOR NOR NOT NOT
Q1
n2
XOR
Q2

Fig. 15.8-1 The schematic diagram of a 3 bit programmable k-fout system

15-42
 VDD VDD VDD VDD

CLK
M1_p1 M2_p1 M3_p1 M4_p1

tsp1 Qb Q
rst
Qb M2p_rst
CLK CLK M3_n1 M4_n1
M1_p2 N3

N2 M2_n1
tsp3
tsp2
M1_n1 M3_n2
CLK M2_n2

rst M2n_rst
VDD VDD

Mc_p1 Mc_p2

CLK_in CLK_b CLK

Mc_n1 Mc_n2

Fig. 15.8-3 The D-Flip Flop with rest used in Experiment 15.8-1

Experiment 15.8-1: 3 Bit Programmable Frequency Divider

The following gives the values of n0,n1 and n2.。

.param n0_volt = 3.3
.param n1_volt = 0
.param n2_volt = 3.3

It can be seen that n0 , n1 , n2  (1,0,1) . Since the binary number 101 represents
5, we expect this experiment will produce a 5-fout system. The program is in
Table 15.8-1. The D-Flip Flop we use in this experiment is shown in Fig. 15.8-3.
Fig. 15.8-4 shows the values of n0,n1 and n2 and the result of this experiment is
shown in Fig. 15.8-5 As can be seen, this is indeed a 5-fout system.

Table 15.8-1 Program for Experiment 15.8-1

Experiment X.3-2
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global VDD GND

15-43
.param l_nch = 0.35u
.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u
.param clk_freq = 1e6

.param n0_volt = 3.3

.param n1_volt = 0
.param n2_volt = 3.3

*CLK input smooth

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*3'
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*1'
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*15'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*5'

.subckt TSPC_rst D CLK Q Qb rst

*Reset Signal
M2n_rst N3 rst gnd gnd nch L=l_nch W='w_nch'

*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*0.4'
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*2'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*2'

*Second stage
M2_p1 tsp2 clk vdd vdd pch L=l_pch W='w_pch*0.4'
M2p_rst N3 rst tsp2 vdd pch L=l_pch W='w_pch*0.4'
M2_n1 N3 N2 tsp3 gnd nch L=l_nch W='w_nch*2'
M2_n2 tsp3 clk gnd gnd nch L=l_nch W='w_nch*2'

*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*0.5'
M3_n1 Qb clk tsp4 gnd nch L=l_nch W='w_nch*0.4'
M3_n2 tsp4 N3 gnd gnd nch L=l_nch W='w_nch*0.4'

*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*1.5'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.5'
.ic v(Qb)=0v
.ends TSPC_rst

*NOR_3in
.subckt NOR nor_a nor_b nor_c NOR_out
Mn_a_p1 nor_1 nor_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mn_b_p1 nor_2 nor_b nor_1 vdd pch L=l_pch W='w_pch*0.5'
Mn_c_p1 NOR_out nor_c nor_2 vdd pch L=l_pch W='w_pch*0.5'
Mn_a_n1 NOR_out nor_a gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_b_n1 NOR_out nor_b gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_c_n1 NOR_out nor_c gnd gnd nch L=l_nch W='w_nch*0.5'

15-44
.ends NOR

*XOR_2in
.subckt XOR xor_a xor_b XOR_out
Mx_ain_p1 xor_ab xor_a vdd vdd pch L=l_pch W='w_pch*1.5'
Mx_ain_n1 xor_ab xor_a gnd gnd nch L=l_nch W='w_nch*0.5'
Mx_bin_p1 xor_bb xor_b vdd vdd pch L=l_pch W='w_pch*1.5'
Mx_bin_n1 xor_bb xor_b gnd gnd nch L=l_nch W='w_nch*0.5'
Mx1_p1 xor_1 xor_ab vdd vdd pch L=l_pch W='w_pch*0.5'
Mx1_p2 XOR_out xor_b xor_1 vdd pch L=l_pch W='w_pch*0.5'
Mx2_p1 xor_2 xor_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mx2_p2 XOR_out xor_bb xor_2 vdd pch L=l_pch W='w_pch*0.5'
Mx1_n1 XOR_out xor_a xor_3 xor_3 nch L=l_nch W='w_nch*0.5'
Mx2_n1 XOR_out xor_bb xor_3 xor_3 nch L=l_nch W='w_nch*0.5'
Mx1_n2 xor_3 xor_ab gnd gnd nch L=l_nch W='w_nch*0.5'
Mx2_n2 xor_3 xor_b gnd gnd nch L=l_nch W='w_nch*0.5'
.ends XOR

*Inverter
.subckt INV inv_in inv_out
Minv_p1 inv_out inv_in vdd vdd pch L=l_pch W='w_pch*1.5'
Minv_n1 inv_out inv_in gnd gnd nch L=l_nch W='w_nch*0.5'
.ends INV

*Subckt Circuit
xTSPC1 Qb_0 CLK Q_0 Qb_0 Fout TSPC_rst
xTSPC2 Qb_1 Qb_0 Q_1 Qb_1 Fout TSPC_rst
xTSPC3 Qb_2 Qb_1 Q_2 Qb_2 Fout TSPC_rst
xXOR1 n0 Q_0 ch1 XOR
xXOR2 n1 Q_1 ch2 XOR
xXOR3 n2 Q_2 ch3 XOR
xNOR ch1 ch2 ch3 Fout NOR
xINV1 Fout Fout_b INV
xINV2 Fout_b F_out INV

Vn0 n0 0 'n0_volt'
Vn1 n1 0 'n1_volt'
Vn2 n2 0 'n2_volt'

Vsupply VDD GND 3.3V

vclk_in clk_in gnd pulse (0 3.3 '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.4875/clk_freq' '1/clk_freq')

.tran '1/(10000*clk_freq)' '(20/clk_freq)'

.END

15-45
 n0

n1

n2

Fig. 15.8-4 n0, n1 and n2 voltages

CLK

F_out

Q0 0 1 0 1 0

Q1 0 0 1 1 0

Q2 0 0 0 0 1

Fig. 15.8-5 The result of Experiment 15.8-1

From Fig. 15.8-5, we can see that the last (Q2,Q1,Q0) is (100). Therefore the
next (Q2,Q1,Q0) will be (101)which is not shown in Fig. 15.8-5.. As discussed
before, this will cause all of the XOR gates to send out 0 and NOR gate to send out 1.

We now explain why the fout reset signal is so short. Note that it is sent out
whenever a certain condition of the values of Q0,Q1 and Q2 are satisfied. But the
fout signal is also the reset signal. After the reset signal is sent to the three D-Flip

15-46
Flops, all of the values of Q0,Q1 and Q2 are rest to 0. Thus the logic gates will not
send out a high signal. Instead, it will send out a low signal. This is why the fout
signal, which is also the reset signal, is so short. The situation is shown in Fig.
15.8-6.

CLK

F_out

Q0

Q1

Q2

Fig. 15.8-6

Section 15.9 A Divide by 6 Frequency Divider and a Divide

by 5 Frequency Divider
In this section, let us first consider a synchronous divide by 6 Johnson counter
frequency divider as shown in Fig. 15.9-1

Qb3 D Q Q1 D Q Q2 D Q Q3

Qb

DFF1 DFF2 DFF3

CLK
Fig. 15.9-1 Synchronous divide by 6 Johnson counter frequency divider

This divider is a synchronous one because the clock signal is fed into the three
D-flip flops simultaneously. Besides, the output of DFF3 is fed back to DFF1. A

15-47
very important property of these D-flip flops is that the output of a D-flip flop cannot
react immediately with the input. If so, it will cause the racing effect which may
cause serious trouble. Imagine that the clock rises and D1 senses this. If there is no
delay, Q1 immediately changes and finally, D1  Q3 immediately changes. This
will, as one can easily imagine, cause trouble. Therefore, we conclude that there
must be a delay within the D-flip flop.

We shall use an experiment to explain how this circuit works.

Experiment 15.9-1 An Experiment of a Synchronous Divide by 6 Johnson

Counter Frequency Divider.

The circuit diagram is as shown in Fig. 15.9-1. The D-flip flop circuit is shown in
Fig. 15.9-2. The program is Table 15.9-1 and the result of the experiment is in Fig.
15.9-3

VDD VDD VDD VDD

CLK
M1_p1 M2_p1 M3_p1 M4_p1

t s p1

N3 Qb Q

Qb
CLK N2 M2_n1 CLK M3_n1 M4_n1
M1_p2

t s p2 t s p3

M1_n1 CLK M2_n2 M3_n2

VDD VDD

Mc_p1 Mc_p2

CLK_in CLK_b CLK

Mc_n1 Mc_n2

Fig. 15.9-2 The D-flip flop circuit

Table 15.9-1 The program for Experiment 15.9-1

Experiment X.1-1
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global VDD GND

15-48
.param l_nch = 0.35u
.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u
.param clk_freq = 1e6

.param Mode_volt = 0

*CLK input smooth

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*1.5'
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*0.5'
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*3'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*1'

*DFF
.subckt TSPC_DFF D CLK Qb Q
*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*1.5'
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*1.5'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*0.5'
*Second stage
M2_p1 N3 clk vdd vdd pch L=l_pch W='w_pch*1.5'
M2_n1 N3 N2 tsp2 gnd nch L=l_nch W='w_nch*0.5'
M2_n2 tsp2 clk gnd gnd nch L=l_nch W='w_nch*1.5'
*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*1.5'
M3_n1 Qb clk tsp3 gnd nch L=l_nch W='w_nch*0.5'
M3_n2 tsp3 N3 gnd gnd nch L=l_nch W='w_nch*0.5'
*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*1.5'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.5'
.ic Qb 3.3
.ends TSPC_DFF

*NAND_2in
.subckt NANDN_a N_b N_out
Ma_p1 N_out N_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mb_p2 N_out N_b vdd vdd pch L=l_pch W='w_pch*0.5'
Ma_n1 N_out N_a nd_1 nd_1 nch L=l_nch W='w_nch*0.5'
Mb_n2 nd_1 N_b gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NAND

*Subckt Circuit
xDFF1 Qb_3 CLK Qb_1 Q_1 TSPC_DFF
xDFF2 Q_1 CLK Qb_2 Q_2 TSPC_DFF
xDFF3 Q_2 CLK Qb_3 Q_3 TSPC_DFF

Vsupply VDD GND 3.3V

vclk_in clk_in gnd pulse (0 3.3 '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.4875/clk_freq' '1/clk_freq')

15-49
.tran '1/(10000*clk_freq)' '(10/clk_freq)'
.END

CLK

Q1

Q2

Q3

Qb3

Fig. 15.9-3 The result of Experiment 15.9-1

From Fig. 15.9-3, we can see that the circuit is indeed a divide by 6 frequency
divider because the cycle of Q3 is 6 clock cycles long.

We should first observe the property that there is a delay mechanism in every
D-flip flop. Consider the first instance when the clock rises. From Fig. 15.9-3, we
can see that Q1 rises at this instance. Actually, it rises slightly after the clock rises.
This is why Q2 does not rise at this moment because so fat as D2  Q1 is concerned,
it rises after the clock is risen because in this circuit, the clock is fed into all of the
D-flip flops.

The function of the frequency divider can be explained by seeing how the
terminals of the D-flip flops behave. This behavior is summarized in table 15.9-2.

Table 15.9-2 The behavior of the terminals of the D-flip flops

of Experiment 15.9-1
D1= Qb3 Q1 Q2 Q3 Qb3 計數
1 0 0 0 1 0
1 1 0 0 1 1
1 1 1 0 1 2
0 1 1 1 0 3
0 0 1 1 0 4
0 0 0 1 0 5

15-50
 1 0 0 0 1 0
1 1 0 0 1 1

At t  0, D1  Q3  1 and (Q1 , Q2 , Q3 )  (0.0.0) . At t  1,

(Q1 , Q2 , Q3 )  (1,0.0) . After six clock cycles, D1  Q3  1 and (Q1 , Q2 , Q3 )  (0.0.0)
again. This is why this circuit is divide by 6 frequency divider. Fig. 15.8-4
illustrates the above discussion. It is important to note that in this diagram,
(0,0,1)  (0,0,0) .

Q1 Q2 Q3

000

001 100

011 110

111

Fig. 15.9-4 The changing of (Q1 , Q2 , Q3 ) for Experiment 15.9-1

A Synchronous Divide by 5 Frequency Divider

In the following, we shall introduce a synchronous divide by 5 frequency divider.
Fig. 15.9-5 shows the circuit diagram of it.

15-51
 Q3
Q2
D1 D Q Q1 D Q D3 D Q
NAND NAND
=Q2

Qb Qb2

DFF1 DFF2 DFF3

CLK

MC (High)

Fig. 15.9-5 A Synchronous Divide by 5 frequency divider

We shall explain why we need the MC signal. Since MC is high, the NAND
gate becomes an inverter as shown in Fig. 15.9-6. In fact, for practical purpose, we
may simply say that D3  Q2 .
Q3
Q2
NAND 1 D
D Q Q1 D Q D3 D Q
NOT
=Q2

Qb Qb2

DFF1 DFF2 DFF3

CLK
Fig. 15.9-6 An equivalent circuit of the circuit in Fig. 15.9-5

The major difference between the divide by 4 frequency divider in Fig. 15.9-1
and the divide by 5 frequency divider in Fig. 15.9-6 is as follows:

(1) In the divide by 4 frequency divider in Fig. 15.9-1, D1  Q3 .

(2) In the divide by 5 frequency divider in Fig. 15.9-6, D1  NAND (Q3 , Q2 ) .

This difference makes the circuit in Fig. 15.9-6 a divide by 5, instead of divide by
6, frequency divider. We will use the following experiment to explain how the
circuit works.

Experiment 15.9-2 An Experiment of the Synchronous Divide by 5 Frequency

Divider

In this experiment, the circuit is in Fig. 15.9-6. We did not use the inverter. We

15-52
connected the output of DFF2 to the input of DFF3 directly. The program is in Table
15.9-3 and the result is in Fig. 15.9-7.

Table 15.9-3 Program for Experiment 15.9-2

Experiment X.1-2
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global VDD GND

.param l_nch = 0.35u

.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u
.param clk_freq = 1e6

.param Mode_volt = 0

*CLK input smooth

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*1.5'
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*0.5'
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*3'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*1'

*DFF
.subckt TSPC_DFF D CLK Qb Q
*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*1.5'
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*1.5'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*0.5'
*Second stage
M2_p1 N3 clk vdd vdd pch L=l_pch W='w_pch*1.5'
M2_n1 N3 N2 tsp2 gnd nch L=l_nch W='w_nch*0.5'
M2_n2 tsp2 clk gnd gnd nch L=l_nch W='w_nch*1.5'
*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*1.5'
M3_n1 Qb clk tsp3 gnd nch L=l_nch W='w_nch*0.5'
M3_n2 tsp3 N3 gnd gnd nch L=l_nch W='w_nch*0.5'
*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*1.5'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.5'
.ic Qb 3.3
.ends TSPC_DFF

*NAND_2in
.subckt NANDN_a N_b N_out
Ma_p1 N_out N_a vdd vdd pch L=l_pch W='w_pch*0.5'

15-53
Mb_p2 N_out N_b vdd vdd pch L=l_pch W='w_pch*0.5'
Ma_n1 N_out N_a nd_1 nd_1 nch L=l_nch W='w_nch*0.5'
Mb_n2 nd_1 N_b gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NAND

*Subckt Circuit
xDFF1 D_1 CLK Qb_1 Q_1 TSPC_DFF
xDFF2 Q_1 CLK Qb_2 Q_2 TSPC_DFF
xDFF3 Q_2 CLK Qb_3 Q_3 TSPC_DFF
xNAND Q_3 Q_2 D_1 NAND

Vsupply VDD GND 3.3V

vclk_in clk_in gnd pulse (0 3.3 '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.4875/clk_freq' '1/clk_freq')

.tran '1/(10000*clk_freq)' '(10/clk_freq)'

.END

CLK

Q1

Q2

Q3

D1

Fig. 15.9-7 The result of Experiment 15.9-2

In Table 15.9-4, we show the behavior of (Q1 ,Q 2 , Q3 ) of Experiment 15.9-2.

Table 15.9-4 The behavior of (Q1 ,Q 2 , Q3 )

of Experiment 15.9-2
D1 Q1 Q2 Q3 D1 計數
1 0 0 0 1 0
1 1 0 0 1 1
1 1 1 0 1 2

15-54
 0 1 1 1 0 3
0 0 1 1 0 4
1 0 0 1 1 5
1 1 0 0 1 1

Consider the state (Q1 ,Q 2 , Q3 )  (0,0,1) .

(1) In the divide by 6 frequency divider circuit, D1  Q3  0 because Q3  1 .

Therefore, we have, in the divide by 6 frequency divider circuit, we have
(0,0,1)  (0,0,0) .
(2) In the divide by 6 frequency divider circuit, D1  NAND (Q2 , Q3 ) . Since Q2  0
and Q3  1 , D1  NAND (Q2 , Q3 )  NAND (0,1)  1 . Thus, in the divide by 5
frequency divider circuit, we have (0,0,1)  (1,0,0) .

Fig. 15.9-8 illustrates the above discussion. From this diagram, we can see that
there are only 5 clock cycles for this circuit. (0,0,0) appears only once at the very
beginning and never appears again. Thus this circuit is a divide by 5 frequency
divider.

Q1 Q2 Q3
000
100

001 110

011 111

Fig. 15.9-8 The changing of (Q1 , Q2 , Q3 ) for Experiment 15.9-2

It is important to point out the difference between asynchronous frequency

dividers and synchronous frequency dividers. Suppose that there are three DFF’s.
For an asynchronous frequency divider, the frequencies of Q1, Q1 and Q0 are different
as can be seen in Fig. 15.6-4. For a synchronous frequency divider, the frequencies
of Q1, Q1 and Q0 are the same as can be seen in Fig. 15.9-7.

15-55
Section 15.10 A dual-modulus prescaler by 4/5 Frequency
Divider
In this section, we shall introduce a special frequency divider, called dual-modulus
prescaler by 4/5.. This circuit will be used in the phase lock loop which will be
introduced in the next chapter. There is a control signal, named MC. When the
MC signal is of low voltage, the circuit is a divide by 4 frequency divider and it is a
divide by 5 frequency divider if the MC signal is of high voltage. The schematic
diagram of the circuit is shown in Fig. 15.10-1, the circuit of the D-Flip Flop is in Fig.
15.10-2 and the NAND gate circuit is in Fig. 15.10-3

Q3
Q2
D1 D Q Q1 D Q D3 D Q
NAND NAND

Qb

DFF_1 DFF_2 DFF_3

CLK

MC
Fig. 15.10-1 A dual modulus prescaler-by 4/5 frequency divider

15-56
 VDD VDD VDD VDD

CLK
M1_p1 M2_p1 M3_p1 M4_p1

t s p1

N3 Qb Q

Qb
CLK N2 M2_n1 CLK M3_n1 M4_n1
M1_p2

t s p2 t s p3

M1_n1 CLK M2_n2 M3_n2

VDD VDD

Mc_p1 Mc_p2

CLK_in CLK_b CLK

Mc_n1 Mc_n2

Fig. 15.10-2 The TSPC D-Flip Flop circuit used in the dual modulus prescaler by
4/5 frequency divider
VDD

A Ma_p1 B Mb_p2

N_out

A Ma_n1

B Mb_n2

Fig. 15.10-3 The NAND gate used in the dual modulus prescaler
by 4/5 frequency divider

If the MC signal is low, D3 will be always high and Q3 will always be high.
Since Q3 is always high, D1 will be simply the inversion of Q2. We may therefore
ignore DFF3 and the circuit becomes a synchronous divide by 4 Johnson counter
frequency divider

Experiment 15.10-1 The Testing of the Dual Modulus Prescaler by 4/5 with MC
Signal Low

15-57
We set MC to be of 0Volt as indicated in Fig. 15.10-4
.param MC_volt = 0
Q3
High
Q2
D1 D Q Q1 D Q D3 D Q
NAND NAND
High

Qb Qb2

DFF_1 DFF_2 DFF_3

CLK

MC (Low)

Fig. 15.10-4 The MC signal is low in Experiment 15.10-1.

The program is in Table 15.10-1.

Table 15.10-1 The Program for Experiment 15.10-1

Experiment X.4-1
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global VDD GND

.param l_nch = 0.35u

.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u
.param clk_freq = 1e6

.param MC_volt = 0

*CLK input smooth

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*1.5'
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*0.5'
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*3'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*1'

*DFF
.subckt TSPC_DFF D CLK Qb Q
*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*1.5'

15-58
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*1.5'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*0.5'
*Second stage
M2_p1 N3 clk vdd vdd pch L=l_pch W='w_pch*1.5'
M2_n1 N3 N2 tsp2 gnd nch L=l_nch W='w_nch*0.5'
M2_n2 tsp2 clk gnd gnd nch L=l_nch W='w_nch*0.5'
*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*1.5'
M3_n1 Qb clk tsp3 gnd nch L=l_nch W='w_nch*0.5'
M3_n2 tsp3 N3 gnd gnd nch L=l_nch W='w_nch*0.5'
*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*1.5'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.5'
.ic Qb 3.3
.ends TSPC_DFF

*NAND_2in
.subckt NANDN_a N_b N_out
Ma_p1 N_out N_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mb_p2 N_out N_b vdd vdd pch L=l_pch W='w_pch*0.5'
Ma_n1 N_out N_a nd_1 nd_1 nch L=l_nch W='w_nch*0.5'
Mb_n2 nd_1 N_b gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NAND

*Subckt Circuit
xDFF1 D_1 CLK Qb_1 Q_1 TSPC_DFF
xDFF2 Q_1 CLK Qb_2 Q_2 TSPC_DFF
xDFF3 D_3 CLK Qb_3 Q_3 TSPC_DFF
xNAND1 Q_2 Q_3 D_1 NAND
xNAND2 Qb_2 MC D_3 NAND

Vmc MC 0 'MC_volt'

Vsupply VDD GND 3.3V

vclk_in clk_in gnd pulse (0 3.3 '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.4875/clk_freq' '1/clk_freq')

.tran '1/(100000*clk_freq)' '(10/clk_freq)'

.END

The result of Experiment 15.10-1 is in Fig. 15.10-5.

15-59
 CLK
Q_1
Q_2
Q_3
MC
D_1
Qb_2
D_3

Fig. 15.10-5 The result of Experiment 15.10-1

From Fig. 15.9-5, we can see that the circuit is a divide by 4 frequency divider.

Experiment 15.10-2 The Testing of the Dual Modulus Prescaler by 4/5 with MC
Signal High

In this experiment, we set MS to be high as depicted in Fig. 15.10-6. All the

circuits are the same as those in Experiment 15.10-1. The result is in Fig. 15.10-7.

We set MC voltage to be 3.3V.

.param MC_volt = 3.3
Q3
Low
Q2
D1 D Q Q1 D Q D3 D Q
NAND NAND
Low

Qb Qb2

DFF_1 DFF_2 DFF_3

CLK

MC (High)

Fig. 15.10-6 MC signal is high in Experiment 15.10-2.

15-60
 CLK
Q_1
Q_2
Q_3
MC
D_1
Qb_2
D_3

Fig. 15.10-7 The result of Experiment 15.10-2 with MC signal high

As one can see, this circuit is a divide by 5 frequency divider. Thus we have
obtained a dual modulus prescaler by 4/5 frequency divider by controlling the
volatage of the MC signal

15-61
Section 15.11 A Dual-modulus Divide by 32/33 Prescaler Frequency
Divider

In this section, we introduce a dual modulus divide by 32/33 prescaler frequency

divider. The control signal is the Mode signal. If the Mode is low, this circuit is a
divide by 32 frequency divider and if it is high, the circuit is a divide by 33 frequency
divider. Fig. 15.11 shows the circuit diagram of this frequency divider.

Divide by 4/5

Q2 Q3
D1 D Q Q1 D Q D3 D Q
NAND NAND

Qb Qb2

DFF1 DFF2 DFF3

CLK
MC Mode
M1
NAND
NOR

Divide by 8

D Qb D Qb D Qb Qb6
Fout
Q Q4 Q Q5 Q

DFF4 DFF5 DFF6

Mode Fout
0 CLK/32
1 CLK/33
Fig. 15.11-1 A dual modulus divide-by 32/33 frequency divider

The following are the important properties of this circuit.

(1) When the Mode signal is low, M1 will be high and MC will be low. If MC is
low, as discussed in Section 15.10, DFF3 can be ignored.
(2) If Mode  1 and Q6  1 , M1 will be low. If, when M 1  Q4 Q 5  0 , MC will

15-62
 be high.
(3) DFF1 and DFF2 constitute a synchronous divide by 4 frequency divider.
(4) If MC is high, DFF3 will not be ignored. In this case, DFF1 to DFF3 constitute a
divide by 5 frequency divider as pointed out in Section 15.9.
(5) DFF4 to DFF6 constitute an asynchronous divide by 8 frequency divider.
(6) If MC is low, DFF3 is ignored. The Q4 signal is divided by 8,the Q5 signal is
divided by 16 and the Q6 signal is divided by 32. Therefore the Fout signal is
divided by 32.
(7) If Mode is low, MC will be low as pointed out in Statement (1). Therefore, if
MC is low, the circuit is a divide 32 frequency divider.
(8) If MC is high, when Q4  Q5  Q6  0 , MC  1 and DFF3 begins to work. As
explained before, DFF1, DFF2 and DFF3 function as a divide by 5 frequency
divider.

As stated in the last of the above statements, it is important to know when

Q4  Q5  Q6  0 . This can be understood by examining Fig. 15.11-2 which shows
the behavior of Q4, Q5 and Q6 when the Mode signal is low. It can be seen that the
only period of time when Q4  Q5  Q6  0 is during the period from t=28 to t=32.
Therefore, if Mode is high, as soon as t=28, FFT3 begins to work and the first three
D-flip flops become a divide by 5 frequency divider. The period of the cycle of this
circuit becomes 28+5=33. This is why the circuit is a divide by 33 frequency divider
when Mode is high.

Q4

Q5

Q6

28 32
Fig. 15.11-2 The behavior of Q4, Q5 and Q6 when Mode is low.

Experiment 15.11-1 The Divide by 32 Frequency Divider

In this experiment, the circuit used is the circuit in Fig. 15.11-1. The NOR gate is in
Fig. 15.11-3. The frequency of the clock was set to be 1MHz. That is, each clock
cycle is 1s . The program is in Table 15.11-1.

15-63
 VDD

A Mn_a_p1

B Mn_b_p1

C Mn_c_p1

NOR_out

A Mn_a_n1 B Mn_b_n1 C Mn_c_n1

Fig. 15.11-3 The NOR gate logic circuit in Experiment 15.11-1

We set Mode = 0. Thus, the circuit should function as a divide by 32 frequency

divider.
.param Mode_volt = 0

Table 15.11-1 Program for Experiment 15.11-1

Experiment X.4-2
.op
.OPTION POST
.PROTECT
.lib "C:\mm0355v.l" TT
.UNPROTECT
.options nomod post
.global VDD GND

.param l_nch = 0.35u

.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u
.param clk_freq = 1e6

.param Mode_volt = 0

*CLK input smooth

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*1.5'
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*0.5'
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*3'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*1'

*DFF
.subckt TSPC_DFF D CLK Qb Q
*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*1.5'
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*1.5'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*0.5'
*Second stage

15-64
M2_p1 N3 clk vdd vdd pch L=l_pch W='w_pch*1.5'
M2_n1 N3 N2 tsp2 gnd nch L=l_nch W='w_nch*0.5'
M2_n2 tsp2 clk gnd gnd nch L=l_nch W='w_nch*0.5'
*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*1.5'
M3_n1 Qb clk tsp3 gnd nch L=l_nch W='w_nch*0.5'
M3_n2 tsp3 N3 gnd gnd nch L=l_nch W='w_nch*0.5'
*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*1.5'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.5'
.ic Qb 3.3
.ends TSPC_DFF

*NAND_2in
.subckt NANDN_a N_b N_out
Ma_p1 N_out N_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mb_p2 N_out N_b vdd vdd pch L=l_pch W='w_pch*0.5'
Ma_n1 N_out N_a nd_1 nd_1 nch L=l_nch W='w_nch*0.5'
Mb_n2 nd_1 N_b gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NAND

*NOR_3in
.subckt NOR nor_a nor_b nor_c NOR_out
Mn_a_p1 nor_1 nor_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mn_b_p1 nor_2 nor_b nor_1 vdd pch L=l_pch W='w_pch*0.5'
Mn_c_p1 NOR_out nor_c nor_2 vdd pch L=l_pch W='w_pch*0.5'
Mn_a_n1 NOR_out nor_a gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_b_n1 NOR_out nor_b gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_c_n1 NOR_out nor_c gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NOR

*Inverter
.subckt INV inv_in inv_out
Minv_p1 inv_out inv_in vdd vdd pch L=l_pch W='w_pch*1.5'
Minv_n1 inv_out inv_in gnd gnd nch L=l_nch W='w_nch*0.5'
.ends INV

*Subckt Circuit
xDFF1 D_1 CLK Qb_1 Q_1 TSPC_DFF
xDFF2 Q_1 CLK Qb_2 Q_2 TSPC_DFF
xDFF3 D_3 CLK Qb_3 Q_3 TSPC_DFF
xNAND1 Q_2 Q_3 D_1 NAND
xNAND2 Qb_2 MC D_3 NAND

xDFF4 Qb_4 Q_1 Qb_4 Q_4 TSPC_DFF

xDFF5 Qb_5 Q_4 Qb_5 Q_5 TSPC_DFF
xDFF6 Qb_6 Q_5 Qb_6 Fout TSPC_DFF

xNAND3 Mode Qb_6 MC_1 NAND

xNOR Q_4 Q_5 MC_1 MC NOR

15-65
Vmc Mode 0 'Mode_volt'

Vsupply VDD GND 3.3V

vclk_in clk_in gnd pulse (0 3.3 '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq'
'0.4875/clk_freq' '1/clk_freq')

.tran '1/(10000*clk_freq)' '(40/clk_freq)'

.END

Fig. 15.11-4 shows the result of this experiment.

Fig. 15.11-4 The result of Experiment 15.11-1 (Mode = 0)

Fig. 15.11-5 shows that the signals all start from 0.5 s .

15-66
 CLK
Q1
Q2
Q3
D1
D3
MC
Q4
Q5
Fout
Qb6
M1
Mode

Fig. 15.11-5 The initial state (time 0~5us)

The ending state is shown in Fig. 15.11-6 We can see that fout ends at 32.5us
which verifies that the circuit is a divide by 32 frequency divider

15-67
 CLK
Q1
Q2
Q3
D1
D3
MC
Q4
Q5
Fout
Qb6
M1
Mode

Fig. 15.11-6 The ending state (t= 30~35us)

Experiment 15.11-2 The Divide by 32 Frequency Divider

In this experiment, we set Mode = 1 The circuit should function as a divide by 33

frequency divider
.param Mode_volt = 3.3

The result is shown in Fig. 15.11-7

15-68
 CLK
Q1
Q2
Q3
D1
D3
MC
Q4
Q5
Fout
Qb6
M1
Mode

Fig. 15.11-7 The result of Experiment 15.11-2

We can see that the circuit does function as a divide by 33 frequency divider
because fout ends at t=33.5us. Besides, this figure shows a very important point,
from t=28us to 33us, Q4  Q5  Q6  0 as we pointed out before. In fact, we can also
see that Q4  Q5  Q6  0 only in this period.

15-69
Section 15.12 The PS-Counter Which Counts to Any
Number
In the above sections, we introduced many frequency dividers with fixed number.
For instance, divide by 2, divide by 3 and divide by 4 frequency dividers have been
introduced. For practical purpose, actually we are interested in counters. For
instance, we need a counter which counts 2, 3 or 4. For a 2-counter, a short pulse will
occur after every 2 clock cycles. For a 3-counter, a short pulse will occur after every
3 clock cycles.

In this section, we shall introduce a counter which is an any number counter.

For instance, we may want to have a 17-counter which gives out a short pulse after
every 17 clock cycles.

Suppose that we have an arbitrary number M . We divide it by N and obtain

the following formula:

M  NP  S (15.12-1)

We may rewrite Equation (15.12-1) as follows:

M  ( N  1)S  N ( P  S ) (15.12-2)

The above equation means that we may do the dividing twice. For the first time,
we divide the frequency by N  1 S times and then for the second time, we divide
it by N P  S times.

Suppose M  17 and N  4 . Then, we have 17  4  4  1 . Thus P  4

and S  1 . Using Equation (15.12-2), we have:

M  5 1  4  (4 1)  5 1  4  3 .

The above discussion shows that we need three program counters:

(1) An (N+1)/N program counter which counts N+1 or N. This kind of program
counter is called a dual modulus-prescaler counter. Its input is the clock signal.
There is a control signal MC which determines whether this counter counts N+1
or N. If the counter counts N+1(N), after N+1(N) clock pulses, this counter will
output a pulse, called nf. This pulse signal is the output of the (N+1)/N program
counter. Note the pulse is a square wave,
(2) An S program counter. The input of this counter is nf. That is, after counting
the nf signal S times, it will send out a control signal MC to change the behavior
of the (N+1)/N counter. The MC signal is a short pulse. If it is counting N+1,
it will start count N and vice versa. Since the S program counter can change the
behavior of the (N+1)/N counter counter, it is called a swallow counter.
(3) A P progam counter whose input signal is the nf pulse from the (N+1)/N program
counter. That is, after counting the nf signal S times, it will send out a
[Link] denoted as pf.

15-70
 A top level diagram of the PS counter is now shown in Fig. 15.12-1.

nf P Program
fin(clock) (N+1)/N Program pf
Counter fout
Counter
(divide by P)

MC=1/0

S Program
Counter
(divide by S)
Reset

Fig. 15.12-1 The Diagram of a PS Counter

The principle of the Pulse Swallow Counter is as follows:

1. The MC signal is first set to be 1. Thus the prescaler divides by N  1 at the

beginning. It sends out a pulse signal nf after every N  1 clock cycles S times.
The nf signal is ent to both S and P counters.

2. In the mean time, both P counter and S counter start counting the bf signals. The
P(S)-counter sends out a pulse signal after every P (S) input nf signals.

3. After the S counter counts to S , the MC signal is changed to be 0. This

happens after ( N  1)S clock cycles

4. Since MC is set to be 0. The prescaler starts to divide by N . That is, it sends

out an upward edge signal after every N clock cycles.

5. From now on, after ( P  S ) upward edge signals have been sent to the P-counter,
the P-counter will send out a pulse. The total time for this set of ( P  S )
signals to be sent corresponds to ( P  S ) N clock cycles.

6. The above discussion indicates that after ( N  1)S  ( P  S ) N  M clock cycles,

a short pulse is sent out from P.

In the following, we shall use the example where M  17, N  4, P  4 , and

S  1 as shown in Table 15.12-1 and Fig. 14.12-

Table 15.12-1 A case for M  17, N  4, P  4 , and S  1

Input Frequency Output Frequency
M Value N Value P Value S Value
(MHz) (MHz)
17 17 4 4 1 1
Table X.1-1

15-71
 S= 1 P-S

M 4+1 4 4 4

P= 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
5 4 4 4
4/5 1 2 3 4

1
S

MC
4
P

Fig. 15.12-2
The circuit of this PS-counter for this example is shown in Fig. 15.12-3.

nF_out P program pF_out

fin 5/4 1MHz
17MHz counter

D Qb

MC Delay and sF_in S program

OR
Latch counter
sF_out
MC DFF

Fig. 15.12-3 The circuit for the PS-Counter

The following explains how the circuit works.

(1) Initially, QB is et to be 1. Thus the MC signal is 1 and the 4/5 counter starts to
5..
(2) After 5 clock cycles, an nf signal is sent to the S counter.

(3) Since S=1, the S Counter will send out a signal to the OR gate, indicating that
the divide by 5 operations are finished. The OR gate sends out a 1 signal to the DFF
which makes the Q terminal to be 1 and Qb to be 0. Since MC is from Qb, MC
becomes 0 which is what we desire.

(4) The 4/5 counter begins to count by 4. After counting 4 clock cycles, it will
send out an nf signal to the P counter. The P counter counts the number of nf signals.
After P=4 nf signals are received, a pf signal will be sent out

15-72
(5) When the pF-out becomes 1, it will cause the DFF to flip again. That is, Qb
will become 1 again. Since MC is from Qb, MC becomes 1 which is what we desire.

(6) When pF-out becomes 1 and MC becomes 1, we need to delay the MC slightly.
If there is no such a delay, the S Counter will send out a 1 signal immediately which is
not desirable. Note that after the S counter counts to S, it should stop functioning.
Therefore, there is a delay and latch circuit which will delay the MC signal and make
sure that the S counter will not function.

The more detailed descriptions of the circuits are given below.

Q3
Q2
D1 D Q Q1 D Q D3 D Q
NAND NAND

Qb

DFF1 DFF2 DFF3

CLK

nF_out MC
Fig. 15.12-4 Divide by 4/5 prescaler

15-73
 Q0 Q1 Q2 Q3 Q4

DFF_0 DFF_1 DFF_2 DFF_3 DFF_4

D Q D Q D Q D Q D Q
CLK Qb Qb
Qb Qb Qb
R R R R R

n0
XOR
Q0
n1
XOR
Q1 R
n2
XOR NOR
Fout
Q2
n3
XOR
Q3
n4
XOR
Q4

Fig. 15.12-5 5-bit Program Counter and 5-bit S Counter

nF_out
Delay

XOR NOT NOT

Delay sF_in
nF_out_delay D Q
sCLK
AND

DFF_sclk_clk DFF
Delay

MC

15-74
 Fig. 15.12-6 The delay and latch circuit

In the following, we shall describe how the delay and latch circuit illustrated in
Fig. 15.12-6 works. We shall present three cases:

Case 1: MC=1. This causes the prescaler to be a divide by N  1 counter

Fig. 15.12-7 illustrates the signals of the delay and latch circuit.

A=nf-out

B=nf-out delayed

DFF-C=XOR(A,B)

DFF-C=XOR(A,B)-delayed
again

MC

MC-delayed

DFF-D=AND(A,MC delayed)

sF-in

Fig. 15.12-7 The signals in the delay and latch circuit for Case 1

Case 2: MC goes down. This happens when the Swallow Counter has already
counted to S . The signals in the delay and latch circuit for this case are now shown
in Fig. 15.12-8. We can see that sF-in will be high after MC is low. This means
that the S-Counter will stop counting which is what we expect.

15-75
 A=nf-out

B=nf-out delayed

DFF-C=XOR(A,B)

DFF-C=XOR(A,B)-delayed
again

MC

MC-delayed

DFF-D=AND(A,MC-delayed)

sF-in

Fig. 15.12-8 The signals in the delay and latch circuit for Case 2

Case 3: MC goes up. This happens immediately after the P-counter counts to P .
Note that this should not cause the sf-in to send out a high signal to the S-counter. If
it does, it will cause the S-counter to count to 1 immediately. As we shall see from
Fig. 15.12-9, sF-in will remain to be low after MC immediately goes down. It will
become high after nF-out sends out its first upward edge signal.

It is important to note that the MC is delayed. This causes the DFF-D arrives at
the DFF after DFF-C. In other words, the DFF-C does not have any effect on the
DFF.

15-76
 A=nf-out

B=nf-out delayed

DFF-C=XOR(A,B)

DFF-C=XOR(A,B)-delayed
again

MC

MC-delayed

DFF-D=AND(A,MC-delayed)

sF-in

Fig. 15.12-9 The signals in the delay and latch circuit for Case 3

The following figures show the details of the circuits of the PS-Counter.

15-77
 VDD VDD VDD VDD

CLK
M1_p1 M2_p1 M3_p1 M4_p1

t s p1

N3 Qb Q

Qb
CLK N2 M2_n1 CLK M3_n1 M4_n1
M1_p2

t s p2 t s p3

M1_n1 CLK M2_n2 M3_n2

VDD VDD

Mc_p1 Mc_p2

CLK_in CLK_b CLK

Mc_n1 Mc_n2

Fig. 15.12-10 TSPC D-Flip Flop circuit

VDD VDD VDD VDD

CLK
M1_p1 M2_p1 M3_p1 M4_p1

t s p1

Qb Q
rst
D M2p_rst
CLK CLK M3_n1 M4_n1
M1_p2 N3

N2 M2_n1 t s p3

t s p2

M1_n1 M3_n2
CLK M2_n2

rst M2n_rst

Fig. 15.12-11 TSPC D-Flip Flop circuit (with reset)

15-78
 VDD

A Ma_p1 B Mb_p2

N_out

A Ma_n1

B Mb_n2

Fig. 15.12-12 2-input NAND gate circuit

VDD

A Mn_a_p1

B Mn_b_p1

C Mn_c_p1

NOR_out

A Mn_a_n1 B Mn_b_n1 C Mn_c_n1

Fig. 15.12-13 3-input NOR gate circuit

VDD
VDD

Mx_A_inv _p1

A_b Mx1 p1 Mx2 p1 A

A A_b
xor _1 xor _2

Mx_A_inv _n1

B Mx1 p2 Mx2 p2 B_b

XOR_out
VDD

A Mx1 n1 Mx2 n1 B_b

Mx_B_inv _p1 xor _3

B B_b
A_b Mx1 n2 Mx2 n2 B
Mx_B_inv _n1

Fig. 15.12-14 XOR gate circuit

Experiment 15.12-1 An Experiment of a PS-Counter Which Counts to 17.

In this section, M  17, N  4, P  4 and S  1 . The top level circuit diagram

is shown in Fig. 15.12-15. The circuits are all shown in the above figures. The

15-79
program is in Table 15.12-2.

Prescaler
fin ÷4 / 5 nF_out 5 bit pF_out
P Counter

D Qb
Delay 5 bit
OR
& Latch S Counter
DFF
sF_out
MC MC

Fig. 15.12-15

Table 15.12-2 Program for Experiment 15.12-1

Experiment X.1-1 with Delay
.op
.OPTION POST
.PROTECT
.lib 'C:\mm0355v.l' TT
.UNPROTECT
.options nomod post
.global VDD GND

*/-----MOS Size-----/*
.param l_nch = 0.35u
.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u

*/-----CLK Frequency-----/*
.param clk_freq = 17e6

*/-----P Counter value-----/*

.param p0_volt = 0
.param p1_volt = 0
.param p2_volt = 3.3
.param p3_volt = 0
.param p4_volt = 0

*/-----S Counter Value-----/*

.param s0_volt = 3.3
.param s1_volt = 0

15-80
.param s2_volt = 0
.param s3_volt = 0
.param s4_volt = 0

*--------CLK input smooth--------*

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*0.4'
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*0.4'
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*0.5'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*0.5'

*--------TSPC DFF without reset--------*

.subckt TSPC_DFF D CLK Qb Q
*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*1.5'
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*1.5'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*0.5'
*Second stage
M2_p1 N3 clk vdd vdd pch L=l_pch W='w_pch*1.5'
M2_n1 N3 N2 tsp2 gnd nch L=l_nch W='w_nch*0.5'
M2_n2 tsp2 clk gnd gnd nch L=l_nch W='w_nch*0.5'
*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*1.5'
M3_n1 Qb clk tsp3 gnd nch L=l_nch W='w_nch*0.5'
M3_n2 tsp3 N3 gnd gnd nch L=l_nch W='w_nch*0.5'
*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*1.5'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.5'
.ic Qb 3.3v
.ends TSPC_DFF

*--------TSPC DFF with reset--------*

.subckt TSPC_rst D CLK Qb Q rst
*Reset Signal
M2n_rst N3 rst gnd gnd nch L=l_nch W='w_nch'
*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*0.4'
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*2'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*2'
*Second stage
M2_p1 tsp2 clk vdd vdd pch L=l_pch W='w_pch*0.4'
M2p_rst N3 rst tsp2 vdd pch L=l_pch W='w_pch*0.4'
M2_n1 N3 N2 tsp3 gnd nch L=l_nch W='w_nch*2'
M2_n2 tsp3 clk gnd gnd nch L=l_nch W='w_nch*2'
*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*0.5'
M3_n1 Qb clk tsp4 gnd nch L=l_nch W='w_nch*0.4'
M3_n2 tsp4 N3 gnd gnd nch L=l_nch W='w_nch*0.4'
*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*0.4'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.4'

15-81
.ic Qb 0v
.ends TSPC_rst

*--------NAND_2_input--------*
.subckt NANDN_a N_b N_out
Ma_p1 N_out N_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mb_p2 N_out N_b vdd vdd pch L=l_pch W='w_pch*0.5'
Ma_n1 N_out N_a nand_1 nand_1 nch L=l_nch W='w_nch*0.5'
Mb_n2 nand_1 N_b gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NAND

*--------NOR_2_input--------*
.subckt NOR2 nor_A nor_B NOR_out
Mn_a_p1 nor_1 nor_A vdd vdd pch L=l_pch W='w_pch*0.5'
Mn_b_p1 NOR_out nor_B nor_1 vdd pch L=l_pch W='w_pch*0.5'
Mn_a_n1 NOR_out nor_A gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_b_n1 NOR_out nor_B gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NOR2

*--------NOR_5_input--------*
.subckt NOR5 nor_A nor_B nor_C nor_D nor_E NOR_out
Mn_a_p1 nor_1 nor_A vdd vdd pch L=l_pch W='w_pch*0.5'
Mn_b_p1 nor_2 nor_B nor_1 vdd pch L=l_pch W='w_pch*0.5'
Mn_c_p1 nor_3 nor_C nor_2 vdd pch L=l_pch W='w_pch*0.5'
Mn_d_p1 nor_4 nor_D nor_3 vdd pch L=l_pch W='w_pch*0.5'
Mn_e_p1 NOR_out nor_E nor_4 vdd pch L=l_pch W='w_pch*0.5'
Mn_a_n1 NOR_out nor_A gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_b_n1 NOR_out nor_B gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_c_n1 NOR_out nor_C gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_d_n1 NOR_out nor_D gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_e_n1 NOR_out nor_E gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NOR5

*--------XOR_2_input--------*
.subckt XOR xor_a xor_b XOR_out
Mx_A_inv_p1 xor_a_b xor_a vdd vdd pch L=l_pch W='w_pch*1.2'
Mx_A_inv_n1 xor_a_b xor_a gnd gnd nch L=l_nch W='w_nch*0.4'
Mx_B_inv_p1 xor_b_b xor_b vdd vdd pch L=l_pch W='w_pch*1.2'
Mx_B_inv_n1 xor_b_b xor_b gnd gnd nch L=l_nch W='w_nch*0.4'
Mx1_p1 xor_1 xor_a_b vdd vdd pch L=l_pch W='w_pch*0.4'
Mx1_p2 XOR_out xor_b xor_1 vdd pch L=l_pch W='w_pch*0.4'
Mx2_p1 xor_2 xor_a vdd vdd pch L=l_pch W='w_pch*0.4'
Mx2_p2 XOR_out xor_b_b xor_2 vdd pch L=l_pch W='w_pch*0.4'
Mx1_n1 XOR_out xor_a xor_3 xor_3 nch L=l_nch W='w_nch*0.4'
Mx1_n2 xor_3 xor_a_b gnd gnd nch L=l_nch W='w_nch*0.4'
Mx2_n1 XOR_out xor_b_b xor_3 xor_3 nch L=l_nch W='w_nch*0.4'
Mx2_n2 xor_3 xor_b gnd gnd nch L=l_nch W='w_nch*0.4'
.ends XOR

*--------Inverter--------*

15-82
.subckt INV inv_in inv_out
Minv_p1 inv_out inv_in vdd vdd pch L=l_pch W='w_pch*0.5'
Minv_n1 inv_out inv_in gnd gnd nch L=l_nch W='w_nch*0.5'
.ends INV

*-------Delay--------*
.subckt Delay delay_in delay_out
Mdelay_p1 delay_out_1 delay_in vdd vdd pch L='l_pch*10' W='w_pch*1.5'
Mdelay_n1 delay_out_1 delay_in gnd gnd nch L='l_nch*10' W='w_nch*0.5'
Mdelay_p2 delay_out delay_out_1 vdd vdd pch L='l_pch*10' W='w_pch*1.5'
Mdelay_n2 delay_out delay_out_1 gnd gnd nch L='l_nch*10' W='w_nch*0.5'
.ends Delay

********** Subckt Circuit **********

*/---------4/5---------/*
xDFF_n1 nD_1 CLK nQb_1 nF_out TSPC_DFF
xDFF_n2 nF_out CLK nQb_2 nF_out_delay TSPC_DFF
xDFF_n3 nD_3 CLK nQb_3 nQ_3 TSPC_DFF
xNAND_n1 nF_out_delay nQ_3 nD_1 NAND
xNAND_n2 nQb_2 MC nD_3 NAND

*/---------5 bit P Counter---------/*

xDFF_p1 pQb_0 nF_out pQb_0 pQ_0 pF_out TSPC_rst
xDFF_p2 pQb_1 pQb_0 pQb_1 pQ_1 pF_out TSPC_rst
xDFF_p3 pQb_2 pQb_1 pQb_2 pQ_2 pF_out TSPC_rst
xDFF_p4 pQb_3 pQb_2 pQb_3 pQ_3 pF_out TSPC_rst
xDFF_p5 pQb_4 pQb_3 pQb_4 pQ_4 pF_out TSPC_rst
xXOR_p1 p_n0 pQ_0 p_ch1 XOR
xXOR_p2 p_n1 pQ_1 p_ch2 XOR
xXOR_p3 p_n2 pQ_2 p_ch3 XOR
xXOR_p4 p_n3 pQ_3 p_ch4 XOR
xXOR_p5 p_n4 pQ_4 p_ch5 XOR
xNOR_p1 p_ch1 p_ch2 p_ch3 p_ch4 p_ch5 pFout NOR5
xINV_p1 pFout pFout_b INV
xINV_p2 pFout_b pF_out INV

*/----------Delay & Latch----------/*

xXOR_DFF_sclk nF_out_delay nF_out nF_out_delay_1 XOR
xINV_DFF_sclk_clk_1 nF_out_delay_1 nF_out_delay_2 INV
xINV_DFF_sclk_clk_2 nF_out_delay_2 DFF_sclk_clk INV
xDelay_MC MC MC_Delay Delay
xNAND_s1 nF_out MC_Delay DFF_sclk_D_b NAND
xINV_s1 DFF_sclk_D_b DFF_sclk_D INV
xDFF_sclk DFF_sclk_D DFF_sclk_clk DFF_sclk_Qb sF_in TSPC_DFF

*/---------5 bit S Counter---------/*

xDFF_s1 sQb_0 sF_in sQb_0 sQ_0 sF_out TSPC_rst
xDFF_s2 sQb_1 sQb_0 sQb_1 sQ_1 sF_out TSPC_rst
xDFF_s3 sQb_2 sQb_1 sQb_2 sQ_2 sF_out TSPC_rst
xDFF_s4 sQb_3 sQb_2 sQb_3 sQ_3 sF_out TSPC_rst

15-83
xDFF_s5 sQb_4 sQb_3 sQb_4 sQ_4 sF_out TSPC_rst
xXOR_s1 s_n0 sQ_0 s_ch1 XOR
xXOR_s2 s_n1 sQ_1 s_ch2 XOR
xXOR_s3 s_n2 sQ_2 s_ch3 XOR
xXOR_s4 s_n3 sQ_3 s_ch4 XOR
xXOR_s5 s_n4 sQ_4 s_ch5 XOR
xNOR_s1 s_ch1 s_ch2 s_ch3 s_ch4 s_ch5 sFout NOR5
xINV_s2 sFout sFout_b INV
xINV_s3 sFout_b sF_out INV
xNOR_s2 pF_out sF_out Mode_1b NOR2
xINV_s4 Mode_1b Mode_1 INV
xDFF_s6 sQb_6 Mode_1 sQb_6 sQ_6 TSPC_DFF
xINV_MC sQ_6 MC INV

*/------P Counter Value (5 bit)------/*

Vp0 p_n0 0 'p0_volt'
Vp1 p_n1 0 'p1_volt'
Vp3 p_n2 0 'p2_volt'
Vp4 p_n3 0 'p3_volt'
Vp5 p_n4 0 'p4_volt'

*/------S Counter Value (5 bit)------/*

Vs0 s_n0 0 's0_volt'
Vs1 s_n1 0 's1_volt'
Vs3 s_n2 0 's2_volt'
Vs4 s_n3 0 's3_volt'
Vs5 s_n4 0 's4_volt'

Vsupply VDD GND 3.3V

vclk_in clk_in gnd pulse (0 3.3 0 '0.025/clk_freq' '0.025/clk_freq' '0.4875/clk_freq'
'1/clk_freq')

.tran '1/(10000*clk_freq)' '(70/clk_freq)'

.END

The result is shown in Fig. 15.12-16. The signal used was 17MHz. This
means that within one second, there will be 17106 clock cycles. Each clock
1
is 106 second. Since we set M  17 , after each 17 clock cycles, there will be
17
a short pulse, which means that after 17us. There will be a pulse. From Fig.
15.12-16, we can see that our circuit works correctly.

15-84
 CLK

nF_out

sF_in

pF_out

sF_out

Mode_1

MC

Fig. 15.12-16 The result of Experiment 15.12-1

Fig. 15.12-17 shows the case when MC goes down. It is what we expected.

15-85
 CLK

nF_out

sF_out_Delay

DFF_sclk_clk

MC

MC_Delay

DFF_sclk_D

sF_in

sF_out

pF_out

Fig. 15.12-17 The case when MC goes down.

Fig. 15.12-18 shows the case when MC goes up. In this case, DFF-sclk-clk
arrives earlier than DFF-sclk-D. Therefore, sF-in has no response as expected.

CLK

nF_out

sF_out_Dela
y
DFF_sclk_clk

MC

MC_Delay

DFF_sclk_D

sF_in

sF_out

pF_out

Fig. 15.12-18 The result when MC goes up.

15-86
Experiment 15.12-2 An Experiment of Generating a 3464 counter.

In this experiment, we wanted to design a 3464 counter. Since this is such a

large number and a large number of subcircuits will be involved, we expect the delay
problem will be a severe one. Thereefore, we will need a synchronous divide by 4
counter. After this frequency divider, we will only need a 3464/ 4  866 counter.
That is, M  866, N  32, P  27 and S  2 .

The circuit disgarm is shown in Fig. 15.12-19

Prescaler
÷4 ÷32/33 nF_out 5 bit pF_out
P Counter

nmode_1
fin Digital Input
D Qb
Delay 5 bit
OR
& Latch S Counter
Modulus
sF_in DFF
Control sF_out
MC Digital Input MC
Fig. 15.12-19 The circuit diagram for Experiment 15.12-2

The circuit for synchronous divide by 4 counter is shown in Fig. 15.12-20

D Q D

Qb

DFF1 DFF2
CLK

F_pre_by4
Fig. 15.12-20 Synchronous Divide by 4 Johnson Counter

The divide by 33/32 prescaler circuit is shown in Fig. 15.12-21.

15-87
 Divide by 4/5

Q2 Q3
D1 D Q Q1 D Q D3 D Q
NAND NAND

Qb Qb2

DFF1 DFF2 DFF3

CLK
MC Mode
M1
NAND
NOR

Divide by 8

D Qb D Qb D Qb Qb6
nF_out
Q Q4 Q Q5 Q

DFF4 DFF5 DFF6

Mode Fout
0 CLK/32
1 CLK/33
Fig. 15.12-21 The divide-by 32/33 prescaler

The P and S counters are the same as those used in Experiment 15.12-1. The
program is in Table 15.12-3.

Table 15.12-3 Program for Experiment 15.12-2

Experiment X.1-2 433MHz with prescaler by 4
.op
.OPTION POST
.PROTECT
.lib 'C:\mm0355v.l' TT
.UNPROTECT
.options nomod post
.global VDD GND

*/-----MOS Size-----/*
.param l_nch = 0.35u

15-88
.param l_pch = 0.35u
.param w_nch = 1u
.param w_pch = 1u

*/-----CLK Frequency-----/*
.param clk_freq = 433e6

*/-----P Counter Value-----/*

.param p0_volt = 3.3
.param p1_volt = 3.3
.param p2_volt = 0
.param p3_volt = 3.3
.param p4_volt = 3.3

*/-----S Counter Value-----/*

.param s0_volt = 0
.param s1_volt = 3.3
.param s2_volt = 0
.param s3_volt = 0
.param s4_volt = 0

*-----CLK input smooth-----*

Mc_p1 clk_b clk_in vdd vdd pch L=l_pch W='w_pch*0.4'
Mc_n1 clk_b clk_in gnd gnd nch L=l_nch W='w_nch*0.4'
Mc_p2 clk clk_b vdd vdd pch L=l_pch W='w_pch*0.5'
Mc_n2 clk clk_b gnd gnd nch L=l_nch W='w_nch*0.5'

*--------TSPC DFF (without reset)--------*

.subckt TSPC_DFF D CLK Qb Q
*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*1.5'
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*1.5'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*0.5'
*Second stage
M2_p1 N3 clk vdd vdd pch L=l_pch W='w_pch*1.5'
M2_n1 N3 N2 tsp2 gnd nch L=l_nch W='w_nch*0.5'
M2_n2 tsp2 clk gnd gnd nch L=l_nch W='w_nch*0.5'
*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*1.5'
M3_n1 Qb clk tsp3 gnd nch L=l_nch W='w_nch*0.5'
M3_n2 tsp3 N3 gnd gnd nch L=l_nch W='w_nch*0.5'
*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*1.5'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.5'
.ic Qb 3.3v
.ends TSPC_DFF

*--------TSPC DFF (with reset)--------*

.subckt TSPC_rst D CLK Qb Q rst
*Reset Signal

15-89
M2n_rst N3 rst gnd gnd nch L=l_nch W='w_nch'
*First stage
M1_p1 tsp1 D vdd vdd pch L=l_pch W='w_pch*0.4'
M1_p2 N2 clk tsp1 vdd pch L=l_pch W='w_pch*2'
M1_n1 N2 D gnd gnd nch L=l_nch W='w_nch*2'
*Second stage
M2_p1 tsp2 clk vdd vdd pch L=l_pch W='w_pch*0.4'
M2p_rst N3 rst tsp2 vdd pch L=l_pch W='w_pch*0.4'
M2_n1 N3 N2 tsp3 gnd nch L=l_nch W='w_nch*2'
M2_n2 tsp3 clk gnd gnd nch L=l_nch W='w_nch*2'
*Third stage
M3_p1 Qb N3 vdd vdd pch L=l_pch W='w_pch*0.5'
M3_n1 Qb clk tsp4 gnd nch L=l_nch W='w_nch*0.4'
M3_n2 tsp4 N3 gnd gnd nch L=l_nch W='w_nch*0.4'
*Forth stage:Inverter
M4_p1 Q Qb vdd vdd pch L=l_pch W='w_pch*0.4'
M4_n1 Q Qb gnd gnd nch L=l_nch W='w_nch*0.4'
.ic Qb 0v
.ends TSPC_rst

*--------NAND_2_input--------*
.subckt NANDN_a N_b N_out
Ma_p1 N_out N_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mb_p2 N_out N_b vdd vdd pch L=l_pch W='w_pch*0.5'
Ma_n1 N_out N_a nd_1 nd_1 nch L=l_nch W='w_nch*0.5'
Mb_n2 nd_1 N_b gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NAND

*--------NOR_2_input--------*
.subckt NOR2 nor_a nor_b NOR_out
Mn_a_p1 nor_1 nor_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mn_b_p1 NOR_out nor_b nor_1 vdd pch L=l_pch W='w_pch*0.5'
Mn_a_n1 NOR_out nor_a gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_b_n1 NOR_out nor_b gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NOR2

*--------NOR_3_input--------*
.subckt NOR3 nor_a nor_b nor_c NOR_out
Mn_a_p1 nor_1 nor_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mn_b_p1 nor_2 nor_b nor_1 vdd pch L=l_pch W='w_pch*0.5'
Mn_c_p1 NOR_out nor_c nor_2 vdd pch L=l_pch W='w_pch*0.5'
Mn_a_n1 NOR_out nor_a gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_b_n1 NOR_out nor_b gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_c_n1 NOR_out nor_c gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NOR3

*--------NOR_5_input--------*
.subckt NOR5 nor_a nor_b nor_c nor_d nor_e NOR_out
Mn_a_p1 nor_1 nor_a vdd vdd pch L=l_pch W='w_pch*0.5'
Mn_b_p1 nor_2 nor_b nor_1 vdd pch L=l_pch W='w_pch*0.5'

15-90
Mn_c_p1 nor_3 nor_c nor_2 vdd pch L=l_pch W='w_pch*0.5'
Mn_d_p1 nor_4 nor_d nor_3 vdd pch L=l_pch W='w_pch*0.5'
Mn_e_p1 NOR_out nor_e nor_4 vdd pch L=l_pch W='w_pch*0.5'
Mn_a_n1 NOR_out nor_a gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_b_n1 NOR_out nor_b gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_c_n1 NOR_out nor_c gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_d_n1 NOR_out nor_d gnd gnd nch L=l_nch W='w_nch*0.5'
Mn_e_n1 NOR_out nor_e gnd gnd nch L=l_nch W='w_nch*0.5'
.ends NOR5

*--------XOR_2_input--------*
.subckt XOR xor_a xor_b XOR_out
Mx_ain_p1 xor_ab xor_a vdd vdd pch L=l_pch W='w_pch*1.2'
Mx_ain_n1 xor_ab xor_a gnd gnd nch L=l_nch W='w_nch*0.4'
Mx_bin_p1 xor_bb xor_b vdd vdd pch L=l_pch W='w_pch*1.2'
Mx_bin_n1 xor_bb xor_b gnd gnd nch L=l_nch W='w_nch*0.4'
Mx1_p1 xor_1 xor_ab vdd vdd pch L=l_pch W='w_pch*0.4'
Mx1_p2 XOR_out xor_b xor_1 vdd pch L=l_pch W='w_pch*0.4'
Mx2_p1 xor_2 xor_a vdd vdd pch L=l_pch W='w_pch*0.4'
Mx2_p2 XOR_out xor_bb xor_2 vdd pch L=l_pch W='w_pch*0.4'
Mx1_n1 XOR_out xor_a xor_3 xor_3 nch L=l_nch W='w_nch*0.4'
Mx2_n1 XOR_out xor_bb xor_3 xor_3 nch L=l_nch W='w_nch*0.4'
Mx1_n2 xor_3 xor_ab gnd gnd nch L=l_nch W='w_nch*0.4'
Mx2_n2 xor_3 xor_b gnd gnd nch L=l_nch W='w_nch*0.4'
.ends XOR

*--------Inverter--------*
.subckt INV inv_in inv_out
Minv_p1 inv_out inv_in vdd vdd pch L=l_pch W='w_pch*0.5'
Minv_n1 inv_out inv_in gnd gnd nch L=l_nch W='w_nch*0.5'
.ends INV

*-------Delay--------*
.subckt Delay delay_in delay_out
Mdelay_p1 delay_out_1 delay_in vdd vdd pch L='l_pch*10' W='w_pch*1.5'
Mdelay_n1 delay_out_1 delay_in gnd gnd nch L='l_nch*10' W='w_nch*0.5'
Mdelay_p2 delay_out delay_out_1 vdd vdd pch L='l_pch*10' W='w_pch*1.5'
Mdelay_n2 delay_out delay_out_1 gnd gnd nch L='l_nch*10' W='w_nch*0.5'
.ends Delay

********** Subckt Circuit **********

*/----------Prescaler by 4----------/*
xDFF_prescaler_1 prescaler_2_Qb CLK prescaler_1_Qb F_pre_by4
TSPC_DFF
xDFF_prescaler_2 F_pre_by4 CLK prescaler_2_Qb prescaler_2_Q
TSPC_DFF

*/----------Prescaler by 32/33----------/*
xDFF_n1 nD_1 F_pre_by4 nQb_1 nF_by4 TSPC_DFF
xDFF_n2 nF_by4 F_pre_by4 nQb_2 nQ_2 TSPC_DFF

15-91
xDFF_n3 nD_3 F_pre_by4 nQb_3 nQ_3 TSPC_DFF
xNAND_n1 nQ_2 nQ_3 nD_1 NAND
xNAND_n2 nQb_2 MC_nand nD_3 NAND
xDFF_n4 nQb_4 nF_by4 nQb_4 nQ_4 TSPC_DFF
xDFF_n5 nQb_5 nQ_4 nQb_5 nQ_5 TSPC_DFF
xDFF_n6 nQb_6 nQ_5 nQb_6 nF_out TSPC_DFF
xOR_n1 nQ_4 nQ_5 MC_1 MC_nand NOR3
xNAND_n3 nQb_6 MC MC_1 NAND

*/----------5 bit P Counter----------/*

xDFF_p1 pQb_0 nF_out pQb_0 pQ_0 pF_out TSPC_rst
xDFF_p2 pQb_1 pQb_0 pQb_1 pQ_1 pF_out TSPC_rst
xDFF_p3 pQb_2 pQb_1 pQb_2 pQ_2 pF_out TSPC_rst
xDFF_p4 pQb_3 pQb_2 pQb_3 pQ_3 pF_out TSPC_rst
xDFF_p5 pQb_4 pQb_3 pQb_4 pQ_4 pF_out TSPC_rst
xXOR_p1 p_n0 pQ_0 p_ch1 XOR
xXOR_p2 p_n1 pQ_1 p_ch2 XOR
xXOR_p3 p_n2 pQ_2 p_ch3 XOR
xXOR_p4 p_n3 pQ_3 p_ch4 XOR
xXOR_p5 p_n4 pQ_4 p_ch5 XOR
xNOR_p1 p_ch1 p_ch2 p_ch3 p_ch4 p_ch5 pFout NOR5
xINV_p1 pFout pFout_b INV
xINV_p2 pFout_b pF_out INV

*/----------Delay & Latch----------/*

xDelay_nF_out nF_out nF_out_delay_1 Delay
xXOR_DFF_sclk nF_out_delay_1 nF_out nF_out_delay_2 XOR
xINV_DFF_sclk_clk_1 nF_out_delay_2 nF_out_delay_3 INV
xINV_DFF_sclk_clk_2 nF_out_delay_3 DFF_sclk_clk INV
xDelay_MC MC MC_Delay Delay
xNAND_s1 nF_out MC_Delay sCLK_b NAND
xINV_s1 sCLK_b sCLK INV
xDFF_sclk sCLK DFF_sclk_clk DFF_sclk_Qb sF_in TSPC_DFF

*/---------5 bit S Counter---------/*

xDFF_s1 sQb_0 sF_in sQb_0 sQ_0 sF_out TSPC_rst
xDFF_s2 sQb_1 sQb_0 sQb_1 sQ_1 sF_out TSPC_rst
xDFF_s3 sQb_2 sQb_1 sQb_2 sQ_2 sF_out TSPC_rst
xDFF_s4 sQb_3 sQb_2 sQb_3 sQ_3 sF_out TSPC_rst
xDFF_s5 sQb_4 sQb_3 sQb_4 sQ_4 sF_out TSPC_rst
xXOR_s1 s_n0 sQ_0 s_ch1 XOR
xXOR_s2 s_n1 sQ_1 s_ch2 XOR
xXOR_s3 s_n2 sQ_2 s_ch3 XOR
xXOR_s4 s_n3 sQ_3 s_ch4 XOR
xXOR_s5 s_n4 sQ_4 s_ch5 XOR
xNOR_s1 s_ch1 s_ch2 s_ch3 s_ch4 s_ch5 sFout NOR5
xINV_s2 sFout sFout_b INV
xINV_s3 sFout_b sF_out INV
xNOR_s2 pF_out sF_out Mode_1b NOR2
xINV_s4 Mode_1b Mode_1 INV

15-92
xDFF_s6 sQb_6 Mode_1 sQb_6 sQ_6 TSPC_DFF
xINV_MC sQ_6 MC INV

*/----------P Counter Value (5 bit)---------/*

Vp0 p_n0 0 'p0_volt'
Vp1 p_n1 0 'p1_volt'
Vp3 p_n2 0 'p2_volt'
Vp4 p_n3 0 'p3_volt'
Vp5 p_n4 0 'p4_volt'

*/----------S Counter Valus (5 bit)----------/*

Vs0 s_n0 0 's0_volt'
Vs1 s_n1 0 's1_volt'
Vs3 s_n2 0 's2_volt'
Vs4 s_n3 0 's3_volt'
Vs5 s_n4 0 's4_volt'

Vsupply VDD GND 3.3V

vclk_in clk_in gnd pulse (0 3.3 0 '0.025/clk_freq' '0.025/clk_freq' '0.4875/clk_freq'
'1/clk_freq')

.tran '1/(100*clk_freq)' '(10500/clk_freq)' *start='(30/clk_freq)'

/*-----f=433.5 MHz-----/*
.alter
.param clk_freq = 433.5e6
.param p0_volt = 3.3
.param p1_volt = 3.3
.param p2_volt = 0
.param p3_volt = 3.3
.param p4_volt = 3.3

.param s0_volt = 3.3

.param s1_volt = 3.3
.param s2_volt = 0
.param s3_volt = 0
.param s4_volt = 0

/*-----f=434 MHz-----/*
.alter
.param clk_freq = 434e6
.param p0_volt = 3.3
.param p1_volt = 3.3
.param p2_volt = 0
.param p3_volt = 3.3
.param p4_volt = 3.3

.param s0_volt = 0
.param s1_volt = 0
.param s2_volt = 3.3

15-93
.param s3_volt = 0
.param s4_volt = 0

/*-----f=434.5 MHz-----/*
.alter
.param clk_freq = 434.5e6
.param p0_volt = 3.3
.param p1_volt = 3.3
.param p2_volt = 0
.param p3_volt = 3.3
.param p4_volt = 3.3

.param s0_volt = 3.3

.param s1_volt = 0
.param s2_volt = 3.3
.param s3_volt = 0
.param s4_volt = 0

/*-----f=435 MHz-----/*
.alter
.param clk_freq = 435e6
.param p0_volt = 3.3
.param p1_volt = 3.3
.param p2_volt = 0
.param p3_volt = 3.3
.param p4_volt = 3.3

.param s0_volt = 0
.param s1_volt = 3.3
.param s2_volt = 3.3
.param s3_volt = 0
.param s4_volt = 0

.END

1
The frequency of our input signal was 433MHz. Each clock cycle is us
433
3464
long. Thus, 3464 clock cycles is  80 us. The result of this experiment is
433
shown in Fig. 15.12-22. As can be seen, PF-out occurs exactly a the expected time.
Thus, our 3464 counter works correctly.

15-94
 CLK

F_pre_by4

nF_out

sF_out

pF_out

MC

Fig. 15.12-22 The result of Experiment 15.12-2

15-95