EC1004E- Digital Circuits and Systems

Monsoon Semester 2024-25

ECED, NIT Calicut

 Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output
code with n  m  2n such that each valid code word produces a unique output code.
Circuits that perform encoding are called encoders.
 An encoder has 2n (or fewer) input lines and n output lines which generate the binary code
corresponding to the input values
 Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code
corresponding to the position in which the 1 appears.
 Eg: A decimal-to-BCD encoder
◦ Inputs: 10 bits corresponding to decimal digits 0 through 9, (D0, …, D9)
◦ Outputs: 4 bits with BCD codes
◦ Function: If input bit Di is a 1, then the output (A3, A2, A1, A0) is the BCD code for i,
 The truth table could be formed, but alternatively, the equations for each of the four outputs
can be obtained directly.

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 Input Di is a term in equation Aj if bit Aj is 1 in the binary value for i.
 Equations:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
Inputs Outputs
A1 = D2 + D3 + D6 + D7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 A3 A2 A1 A0
A0 = D1 + D3 + D5 + D7 + D9 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1

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 If more than one input value is 1, then the encoder just designed does not work.
 One encoder that can accept all possible combinations of input values and produce a
meaningful result is a priority encoder.
 Among the 1s that appear, it selects the most significant input position (or the least
significant input position) containing a 1 and responds with the corresponding binary code
for that position.
 Example:
 Priority encoder with 4 inputs (D3, D2, D1, D0) - highest priority to Inputs Outputs
most significant 1 present - Code outputs A1, A0 and V where V D0 D1 D2 D3 A1 A0 V
indicates at least one 1 present. 0 0 0 0 X X 0
 When all the inputs are zero, output A1A0 is invalid. To make it clear 1 0 0 0 0 0 1
a validity bit output V also can be there. X 1 0 0 0 1 1
X X 1 0 1 0 1
 This kind of validity bit can be designed for the Decimal to BCD
X X X 1 1 1 1
encoder also (which was discussed earlier).

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 D1D0 D1D0
D3D2 00 01 11 10 D3D2 00 01 11 10 Inputs Outputs
X X D0 D1 D2 D3 A1 A0 V
00 00 1 1 0 0 0 0 X X 0
01 1 1 1 1 01 1 0 0 0 0 0 1
D2 X 1 0 0 0 1 1
11 1 1 1 1 11 1 1 1 1 X X 1 0 1 0 1
D3 D3 X X X 1 1 1 1
10 1 1 1 1 10 1 1 1 1

A1=D2+D3 A0=D3+D2’D1 D2’D1

Similarly
V=D3+D2+D1+D0

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 Inputs Outputs
B3 B2 B1 B0 G3 G2 G1 G0 G3=B3
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1 B1B0
0 0 1 1 0 0 1 0 B3B2 00 01 11 10 B1B0
0 1 0 0 0 1 1 0 B3B2 00 01 11 10
0 1 0 1 0 1 1 1 00
00 1 1
0 1 1 0 0 1 0 1 01 1 1 1 1 B3’B2
0 1 1 1 0 1 0 0 01 1 1
1 0 0 0 1 1 0 0 11
1 0 0 1 1 1 0 1 11 1 1
10 1 1 1 1 B3B2’
1 0 1 0 1 1 1 1 10 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0 G2=B3’B2+B3B2’ B2B1’
1 1 0 1 1 0 1 1 =B3B2 B2’B1
1 1 1 0 1 0 0 1 G1=B1’B2+B1B2’
1 1 1 1 1 0 0 0 =B2B1
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 B1B0
Inputs Outputs G3=B3
B3B2 00 01 11 10 B1’B0
B3 B2 B1 B0 G3 G2 G1 G0 G2=B3B2
0 0 0 0 0 0 0 0 00 1 1
G1=B2B1
0 0 0 1 0 0 0 1 1
01 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0 11 1 1
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1 10 1 1 B1B0’
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
G0=B1’B0+B1B0’
1 0 0 0 1 1 0 0
=B1B0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
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 Selecting of data or information is a critical function in digital systems and computers
 Circuits that perform selecting have:
◦ A set of information inputs from which the selection is made
◦ A single output
◦ A set of control lines for making the selection
 Logic circuits that perform selecting are called multiplexers
 A multiplexer selects information from an input line and directs the information to an output
line
 A typical multiplexer has n control inputs (Sn − 1, … S0) called selection inputs, 2n information
inputs (I2n − 1, … I0), and one output Y
 A multiplexer can be designed to have m information inputs with m  2n as well as n
selection inputs

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 A two-to-one-line multiplexer connects one of two 1-bit sources to a common destination.
 The block diagram of a multiplexer is sometimes depicted by a wedge-shaped symbol. It suggests
visually how a selected one of multiple data sources is directed into a single destination.
 The multiplexer is often labeled “MUX” in block diagrams.
 The circuit has two data input lines, one output line, and one
selection line S .
 When S = 0, I0 has a path to the output. When S = 1, I1 has a path
to the output.
 The multiplexer acts like an electronic switch that selects one of
two sources.

Block Diagram 9
 Since 2 = 21, n = 1
 The single selection variable S has two values:
◦ S = 0 selects input I0
◦ S = 1 selects input I1
 The equation:
Y = S’I0 + SI1
 The circuit:

 This is also known as 2:1 MUX or 21 MUX

Block Diagram 10
Function table

Block Diagram

Logic Graph

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 Approach 1:
 Implement function of n variables with:
◦ Sum-of-minterms expressions
◦ An 2n-to-1-line multiplexer
 Design:
◦ Find the truth table for the functions.
◦ In the order they appear in the truth table:
 Apply the function input variables to the multiplexer control inputs Sn - 1, … , S0
 Label the output of the multiplexer with the output variable
◦ Value-fix the information inputs to the multiplexer using the values from the truth table (for
don’t cares, apply either 0 or 1)

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F=(1,2)

X Y F
0 0 0
0 1 1
1 0 1
1 1 0

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F=(1,2,6,7)

X Y Z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

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 Approach 2:
 Implement any function of n variables by using:
◦ An 2n-1-to-1-line multiplexer
◦ A single inverter
 Design:
◦ Find the truth table for the functions.
◦ Based on the values of the first n-1 variables, separate the truth table rows into pairs
◦ For each pair and output, define a rudimentary function of the final variable (0, 1, X0, X0’ )
◦ Using the first n-1 variables as the index, value-fix the information inputs to the multiplexer
with the corresponding rudimentary functions
◦ Use the inverter to generate the rudimentary function X0’

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F=(1,2)

X Y F
0 0 0
F=Y
0 1 1
1 0 1
F=Y’
1 1 0

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F=(1,2,6,7)

X Y Z F
0 0 0 0
F=Z
0 0 1 1
0 1 0 1
0 1 1 0 F=Z’

1 0 0 0
F=0
1 0 1 0
1 1 0 1
F=1
1 1 1 1

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 W X Y Z F
0 0 0 0 0
F=(1,3,4,11,12,13,14,15)
0 0 0 1 1 F=Z
0 0 1 0 0
0 0 1 1 1
F=Z
0 1 0 0 1
F=Z’
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
F=0
1 0 0 0 0
F=0
1 0 0 1 0
1 0 1 0 0
F=Z
1 0 1 1 1
1 1 0 0 1
F=1
1 1 0 1 1
1 1 1 0 1
F=1
1 1 1 1 1 19
 The data distributor, known more commonly as the demultiplexer or “Demux” for short, is the
exact opposite of the Multiplexer.
 The demultiplexer takes one single input data line and then switches it to any one of a
number of individual output lines one at a time.

1:2 Demultiplexer

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 Inputs Outputs Design Equations:
I S1 S0 O3 O 2 O1 O0
0 0 0 0 0 0 0 𝑂0 = 𝑆1 ' 𝑆0 ’I
0 0 1 0 0 0 0 𝑂1 = 𝑆1 ' 𝑆0 I
0 1 0 0 0 0 0 𝑂2 = 𝑆1 𝑆0 ’I
0 1 1 0 0 0 0
1 0 0 0 0 0 1
𝑂3 = 𝑆1 𝑆0 I
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Note that an active high decoder

with enable signal is equivalent to
a demultiplexer.

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 F=(1,2,6,7)
 Each minterm is equivalent each of the output available.
 Hence the required outputs can be combined using OR gate to get the required Boolean
function
X Y Z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
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1. M Morris, M. and Michael, D., Digital Design with an Introduction to the Verilog HDL, 5th
Edn., Pearson, 2013.
2. Roth Jr, C.H., Kinney, L.L. and John, E.B., Fundamentals of logic design, 6th Edn.,
Cengage Learning, 2020.

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Thank You

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