INSTRUCTIONS
•Instruction: Group of bits or words that tells the
computer to perform specific task.
•Instruction Set: Vocabulary(Collection) of commands
understood by a given architecture.
OPERATIONS
⚫ Instruction Set: Different computers have different
instruction sets , But with many aspects in common.
⚫ The MIPS Instruction Set : MIPS (Microprocessor
without Interlocked Pipelined Stages) is a reduced
instruction set computer (RISC) instruction set
architecture (ISA) developed by MIPS Computer
Systems, now MIPS Technologies.
ARITHMETIC OPERATIONS
⚫ Every computer must be able to perform arithmetic.
add a, b a= b +c
⚫ MIPS assembly language notation to add two variables b
and c and,c
to put their sum in a
⚫ Here arithmetic instructions performs only
one operation and have exactly 3 variables.
(two for values and one for storing the result)
To add four variables (a=b+c+d+e)
add a, b ,c b +c placed in a
add a, a b +c +d is now in a
,d
add a, a ,e b +c+ d+ e is now in a
It takes three instructions to sum 4
variables
MIPS REGISTERS
BAC
MIPS ASSEMBLY LANGUAGE
INSTRUCTIONS
Compiling Two C Assignment
Statements into MIPS
⚫ Th is segment of a C program contains the fi ve
variables a, b, c, d, and e.
a=b+c; Two assignment
d=a-e; statements in C
add a , b , c
sub d , a , e
C Statement : f=(g+h) – (i+j);
⚫ MIPS CODE:
temp variable to has g+h
add to , g , h
add t1 , i , j temp variable t1 has i+j
sub f , to , t1 f gets t0-t1
Operands of the computer H/W
⚫ Operands of instructions – A limited number of special
locations built directly in hardware called
REGISTERS
⚫ MIPS [Link] Registers - 32
⚫ For 32 bit processor one word 32 bits : A
natural unit of access in a computer.
⚫ MIPS convention to represent a register – two
character names following a dollar sign ($S0, $S1 ,
$S2 , $t0 , $t1)
Compiling C statements using
registers
C Statement : f=(g+h) – (i+j);
⚫ Variables f , g , h , i and j are assigned to the registers
($S0, $S1 , $S2 , $S3, $S4 respectively .
add $to, $s1, $s2 temp variable to has g+h
add $t1, $s3, $s4 temp variable t1 has i+j
f gets t0-t1 which is in $s0
sub $s0, $t0, $t1
MEMORY OPERANDS
⚫ For accessing and representing complex and large data
structures.
⚫ Processor keeps only small amount of data in registers
and large data(array & structures) are kept in memory.
⚫ Data Transfer Instructions
⚫ Instructions that transfer data between memory and
registers
⚫ To access a word in memory the instruction must
supply the memory address.
MEMORY OPERANDS
•A command that moves
Data transfer instruction data between memory
and registers.
•A value used to
Address delineate the location of
a specific data element
within a memory array.
Memory addresses and contents of
memory at those locations
LOAD /
STORE
•The address of the third data element is 2, and the
value of Memory [2] is 10.
Compiling an Assignment When an
Operand Is in Memory
⚫ Compile this C assignment statement:
C Statement : g = h + A[8];
⚫ Let’s assume that A is an array of 100 words and that
⚫ the compiler has associated the variables g and h with
the registers $s1 and $s2 as before.
⚫ Let’s also assume that the starting address, or base
address, of the array is in $s3.
C Statement : g = h + A[8];
⚫ One of the operands is in memory, so we must first
transfer A[8] to a register.
⚫ The address of this array element is the sum of the base
of the array A, found in register $s3, plus the number
to select element 8.
⚫ The data should be placed in a temporary register for
use in the next instruction.
lw $t0,8($s3) temp reg to gets A[8]
t0 has value in A[8] and
add $s1, $s2, $t0 s2 contains value in h.
Sum is put in g
C Statement : g = h + A[8];
⚫ The constant in a data transfer instruction (8) is called the
offset, and the register added to form the address ($s3) is
called the base register.
⚫ Actual MIPS memory addresses and contents of
memory for those words: Memory byte adresses
•Address of sequential words
differ by 4 .
•MIPS addresses each byte, word
addresses are multiples of 4: there
are 4 bytes in a word.
Using load and store instruction
⚫ Both operands(S and D) are in memory.
C Statement : A[12] = h + A[8];
⚫ h- associated with reg $s2, $s3 – base register of array
A
lw $t0,32($s3) temp reg to gets A[8]
add $t0, $s2, $t0 t0 gets h+A[8}
sw $t0, 48($s3) Sum is written in A[12]
Constant or immediate operands
⚫ For using constants in an operation- eg – incrementing
index.
⚫ Eg: Add the constant 4 to register $s3
Addi $s
⚫ Other way – Using
, $s , $s3=$s3 + 4
3 addi –3add immediate instruction
4
REPRESENTING
INSTRUCTIONS
⚫ In MIPS assembly language the registers used in the
instructions are mapped into numbers..
⚫ Register $s0 to $s7 – Reg number 16-23
⚫ Register $t0 to $t7 – Reg number 8-15
(Refer Register table)
⚫ Machine language Numeric version of
instruction
MIPS INSTRUCTION FORMAT
⚫ All MIPS instructions are encoded in binary.
⚫ All MIPS instructions are 32 bits long. There are
three instruction categories: R-format (most
common), I-format, and J-format.
•R
•Register Format
•I
•Immediate Format
•J
•Jump Format
MIPS INSTRUCTION FORMAT
Translating a MIPS assembly
instruction into a Machine instruction
Assembly language
add $t0, $s1, $s2 instruction
ADD
EXAMPLE
REG TABLE
Conversion
MIPS instruction encoding
⚫ In the table above, “reg” means a register number between 0 and 31,
“address” means a 16-bit address, and “n.a.” (not applicable) means
this field does not appear in this format.
⚫ Note that add and sub instructions have the same value in the op field;
the hardware uses the funct field to decide the variant of the operation:
add (32) or subtract (34).
I FORMAT
⚫ A second type of instruction format is called I-type (for
immediate) or I-format and is used by the immediate
and data transfer instructions. The fields of I-format
are
⚫ The 16-bit address means a load word instruction can
load any word within a region of 215 or 32,768 bytes
⚫ constants no larger than 215.
⚫ rt – destination reg.
⚫ rs-source reg.
I format example
Assembly language
lw $t0, 48($s3) instruction-
Temporary reg $t0 gets
A[8]
35 19 8 48
For lw ($s3) - rs ($t0) -rt address
REG TABLE
MIPS instruction encoding
⚫ In the table above, “reg” means a register number between 0 and 31,
“address” means a 16-bit address, and “n.a.” (not applicable) means
this field does not appear in this format.
⚫ Note that add and sub instructions have the same value in the op field;
the hardware uses the funct field to decide the variant of the operation:
add (32) or subtract (34).
Example encoding
Translating MIPS Assembly Language
into Machine Language
C Statement : A[300]= h + A[300]
⚫ $t1 has the base of the array A and $s2 corresponds to h
⚫ What is the MIPS machine language code for these
three instructions?
Three machine language instructions
lw
add
sw
BINARY
FORMAT
Conversion
LOGICAL OPERATIONS
•Bit wise Operations
•Each word stored as 8 bits
•Shift , AND, OR, NOT, NOR
Logical Operations
⚫ Shift - Moves all bits in a word to the left or right, filling
the emptied bits with 0s
⚫ sll – Shift left logical
⚫ rll- Shift right logical
EXAMPLE for Shift
⚫ Left shift of value contained in register s0
⚫ Assembly lang instruction:
⚫ sll $t2, $s0, 4 # reg $t2 = reg $s0 << 4
bits
⚫ Machine language: op and funct field = 0 for sll
sll – additional benifit
⚫ Shift left logical provides a bonus benefit. Shifting
left by i bits gives the same result as multiplying
by 2i.
⚫ For example, the above sll shift s by 4, which gives
the same result as multiplying by 24 or 16. The first
bit pattern above represents 9, and 9 x 16 =144,
the value of the second bit pattern.
Bitwise - AND
⚫ Example
Bitwise – OR
OR : A logical bit-by bit operation with two operands
that calculates a 1 if there is a 1 in either operand.
Example:
or $t0,$t1,$t2 # reg $t0 = reg $t1 | reg $t2
Answer:
Bitwise – NOT / NOR
A logical bit-by bit operation with one operand that
inverts the bits; that is, it replaces every 1 with a 0, and
every 0 with a 1.
A logical bit-bybit operation with two operands that
calculates the NOT of the OR of the two operands. That
is, it calculates a 1 only if there is a 0 in both operands.
nor $t0, $t1, $t2 # reg $t0 = ~ (reg $t1 | reg $t2)
CONTROL OPERATIONS
•Instructions that controls the flow of
execution
•Instructions for making Decisions
•Eg: If, GoTO
Control Instructions
•Control Instructions
•Conditional Branches
•Unconditional Jumps
Conditional Branches
1. beq register1, register2, L1
Go to the statement labeled
L1 if the value in register 1
and register2 are equal
Conditional Branches
2. bne register1, register2, L1
Go to the statement labeled
L1 if the value in register 1
and register2 are not equal
Compiling if-then-else statements
⚫ C: Statement
if (i==j)
f = g+h;
else
f = g-h;
⚫ If the five variables f through j corresponds to five
registers $s0 to $s4, What is the compiled MIPS code for
this C statement?
MIPS CODE
⚫ Since the above C statement is having else part use bne
instruction
bne •go to Else block
$s3, $s4, Else if i != j
add $s0, •f= g + h
(Skipped if i !=
$s1, $s2 j) to exit ;
•Go
unconditional
j Exit branch
Else : j-jump always
sub $s0,
$s
f= 1g, $s
- h2
(Skipped
if i = j)
Loops - Compiling a while Loop in
C
⚫ Choosing between two alternatives - if
⚫ Iterating a computation – Loops
while (save[i] == k)
i += 1;
⚫ Assume that i and k correspond to registers $s3 and $s5
and the base of the array save is in $s6.
⚫ What is the MIPS assembly code corresponding to
this C segment?
⚫ The first step is to load save[i] into a temporary
register. Before we can load save[i] into a temporary
register, we need to have its address.
⚫ Before we can add i to the base of array save to form
the address, we must multiply the index i by 4 due to
the byte addressing.
⚫ We can use shift left logical, since shifting left by 2
bits multiplies by 22 or 4
MIPS Instructions
Loop : sll $t1, $s3, 2 Temp reg $t1 = i * 4
add $t1, $t1, $s6 $t1 = address of save[i]
lw $t0, 0($t1) Temp reg $t0 = save[i]
bne $t0, $s5, go to Exit if save[i] ≠ k
Exit
addi $s3, $s3, 1 i=i+1
j loop go to Loop
Some other code
Exit :
Machine Lang
Less than instructions – slt , slti
⚫ To check whether a variable is less than another
slt – set less than
⚫ Compares two registers and sets a third register to 1 if the
first is less than the second; otherwise, it is set to 0
slt $t0, $s3, $s4 # $t0 = 1 if $s3 < $s4
slti $t0, $s2, 10 # $t0 = 1 if $s2 < 10
⚫ sltu and sltiu are instructions for unsigned integers
ADDRESSING MODES
•Multiple forms of addressing are generically
called addressing modes.
•How operands are identified for each addressing
mode.
•Different ways of specifying the address of the
operands in an instruction
The MIPS addressing modes are the
following
1 Immediate addressing the operand is a constant within
the instruction itself
2 Register addressing the operand is a register
3 Base or displacement the operand is at the memory
addressing location whose address is the
sum of a register and a
constant in the instruction
4 PC-relative addressing the branch address is the sum of
the PC and a constant in the
instruction
5 Pseudodirect addressing the jump address is the 26 bits of
the instruction concatenated
with the upper bits of the PC
Immediate addressing & Register
addressing
⚫ Example
⚫ 1. addi $s0, $s1, 100
⚫ 2. add $s0, $s1, $s2
[Link] or displacement addressing
⚫ Example
⚫ lw $t0, 8($s1) s1 – base register , 8 - offset
4. PC-relative addressing
⚫ Example
⚫ bne $s0, $s1, 100 -- Control is jumped to PC +
2000
⚫ PC- Address of the next instruction to be
executed
5. Pseudodirect addressing
⚫ Concatenating 26 bits (address) in the instruction with
PC
⚫ Example
⚫ J Exit PC= PC concatenated with Exit