Scribd
Upload
2 views2 pages

Reducing Resistance in Nanowire FETs

The study addresses the issue of uneven current flow in stacked nanowire FETs, where bottom nanowires carry less current due to higher resistance. It finds that Tsilicide adjustment is more effective than Fac scaling for balancing current, as it reduces series resistance without impacting threshold voltage or leakage current. This method enhances performance without compromising power or reliability.

Uploaded by

tanvir02550
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
2 views2 pages

Reducing Resistance in Nanowire FETs

The study addresses the issue of uneven current flow in stacked nanowire FETs, where bottom nanowires carry less current due to higher resistance. It finds that Tsilicide adjustment is more effective than Fac scaling for balancing current, as it reduces series resistance without impacting threshold voltage or leakage current. This method enhances performance without compromising power or reliability.

Uploaded by

tanvir02550
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Series Resistance Reduction in Stacked Nanowire FETs for 7-

nm CMOS Technology

Q1: What problem is addressed in the study regarding stacked nanowire


FETs?
A1: The study looks at a problem in stacked nanowire FETs where the bottom nanowires carry less
current than the top ones. This happens because the bottom nanowires are farther from the
source/drain contacts, so they face higher resistance. This uneven current flow can make the device
slower, less reliable, and harder to design. The paper finds ways to fix this and make the current
more balanced in all nanowires.

Q2: Between Fac scaling and Tsilicide adjustment, which method is more
suitable for balancing current and why?
A2: Tsilicide adjustment is more suitable for balancing current in stacked nanowire FETs. This is
because increasing the silicide thickness (Tsilicide) reduces the series resistance in the lower
nanowires without affecting threshold voltage (Vt), leakage current (Ioff), or parasitic capacitance.

Fig-1 Fig-2

As shown in Fig-1, the current ratio between the top and bottom nanowires approaches unity as
Tsilicide increases, indicating balanced current flow . But Fac scaling which reduces Vt (Fig-2) and
increases leakage.

Thus, Tsilicide adjustment provides better performance enhancement without power or reliability
penalties, making it the more effective and reliable solution.
Q3: Does Tsilicide impact threshold voltage and leakage current?
A3: No, increasing the Tsilicide (silicide depth) does not affect the threshold voltage (Vt) or the
leakage current (Ioff) of the device.
This means the device still turns on at the same voltage and does not leak extra current when it is
off.
It is a safe and effective way to reduce resistance in lower nanowires without causing problems like
increased power loss or unwanted switching.

You might also like