Module 2: Implementation Technology

Mazen A. R. Saghir

Department of Electrical and Computer Engineering

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 1 / 57

 and 1 volt. In this chapter we will mostly use the value VDD = 5 V. Figure 3.1 indicate
range Gnd to V0,max represent logic value 0. The name V0,max means the maximum volt
Representing logic values 0 and 1
circuit must recognize as low. Similarly, the range from V1,min to VDD corresponds to log
is the minimum voltage level that a logic circuit must interpret as high. The exact level

Physically, a digital binary signal is Voltage

represented by a voltage or current VDD

value. Normally, a low voltage value
corresponds to logic value 0 (“low”) Logic value 1
while a high voltage value corresponds
to logic value 1 (“high”). V1,min

Normally, the low voltage value VSS is Undefined

the circuit ground (0 volts), while the
V0,max
high voltage value VDD varies between
1 - 5 volts depending on the circuit
Logic value 0
implementation technology used.
VSS (Gnd)

Figure 3.1 Representation of logic values b

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 2 / 57
Representing logic values 0 and 1 (continued)

Threshold values determine how a voltage value is interpreted.

A voltage value between 60%-100% of VDD will be interpreted as
a logic 1, while a voltage value between 0%-40% of VDD will be
interpreted as a logic 0.

A voltage value between V0,max and V1,min corresponds to an

undefined logic value. Logic signals must never be in this range
unless they are transitioning from 0 → 1, or 1 → 0.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 3 / 57

 x = “low” x = “high”
MOSFETs
x = “high” x = “low”

A transistor is aswitch
(a) A simple three-terminal
controlled by electronic
the input x device that can operate like
a switch. Transistors evolved from discrete components to
(a) A switch with the opposite behavior of Figure 3.2a
high-density devices that can be integrated on a silicon substrate.
Gate
Gate
Integrated circuits are designed using metal oxide semiconductor
field-effect transistors (MOSFETs),
Source Drain
which include three terminals:
source, drain, and gate. The source Drain and the drain functionSource as the
Substrate (Body) V
switch’s terminals, and the gate functions as its control.
Substrate (Body)
DD

There are two (b)

types MOSFETs: nMOS
of transistor
NMOS pMOS. They differ in
and transistor
(b) PMOS
the way they are fabricated.
VG VG

VS VD VS VD

(c) SimplifiednMOS
symbol transistor(c) transistor
for an NMOS Simplified symbol transistor
pMOS for an PMOS transistor

M. Saghir (EECEFigure 3.22023)

320 – Summer
Figure
NMOS transistor as a3.3
Implementation [Link] transistor as a switch.
Technology 4 / 57
 3.8 Practical Aspects 119
n-type MOSFETs 3.8 Practical Aspects 119
VG = 0V

SIO2
VG = 0V

SIO2
VS = 0V
VD
VS = 0 +V+ + + + + + + + + + + + + + + + + + + + + + + +
++++++ ++++++ ++++++ VD
+++++++++++ +++++++++++++++++
+ + ++ ++ ++ ++ ++ ++ ++Substrate + + +p)++ +++++++ ++++++++ + +
+ + + + +( type
++++++ ++++++ ++++++
+++++++++++ +++++++++++++++++
+ +n)+ + + + + + + Substrate ( type p) + + Drain
Source (type + + + +(type
+ + +n)

Source (type n)
(a) When Drain (type n)
VGS = 0 V, the transistor is off

(a) When VGS = 0 V, the transistor is off

VDD

VVGDD= 5V

SIO2
VG = 5V

SIO2
VS = 0V
VD = 0V

VS = 0+
V+ + + + + + + + + +++ ++++++
++++++ ++++++ VD = 0V
+++++++++++ +++++++++++++++++
+ + ++ ++ ++ ++ ++ ++ +++++++++ + + + + + + + +++++++ ++++++++ + +
++++++ ++++++
+++++++++++ +++++++++++++++++
+ + + + + + + + + + + + + + + + + Channel
+ + + + +(n-type)
++++++

M. Saghir (EECE 320 – Summer 2023) (b) When VGS = 5 V, the transistor
Implementation is on (n-type)
Channel
Technology 5 / 57
 VD VD = 0 V VD
OS transistor is turned on when its gate terminal is high, while a PMOS transistor
MOSFETs as switches
on when its gate is low. When the NMOS transistor is turned on, its drain is
own to Gnd, and when the PMOS transistor is turned on, its drain is pulled Vup to
G
cause of the way the transistors operate, an NMOS transistor cannot be used to
rain terminal completely up to VDD . Similarly, a PMOS transistor cannot be used
s drain terminal completely down to Gnd. We discuss the operation of MOSFETs
VS = 0 V
erable detail in section 3.8.
Depending on the type of MOSFET used (nMOS Closed or pMOS)
switch and the
Open switch
when VG = VDD when VG = 0 V
voltage applied to the gate, VG , the state of the switch changes
accordingly: (a) NMOS transistor

VD VD = 0 V VD VS = VDD VDD VDD

VG VG

VS = 0 V VD VD VD = VDD
Closed switch Open switch Open switch Closed switch
when VG = VDD when VG = 0 V when VG = VDD when VG = 0 V

nMOS transistor
(a) NMOS transistor pMOS transistor
(b) PMOS transistor

VG = high ⇒ switch closed FigureV3.4 highand⇒

G =NMOS switch
PMOS transistorsopen
in logic circuits.
VS = VDD VDD VDD
VG = low ⇒ switch open VG = low ⇒ switch closed
VG

M. Saghir (EECE
VD 320 – Summer 2023)
VD Implementation
VD = VDD Technology 6 / 57
ed by an arrow labeled
Typically, V V aboutand
isDD the
0.2 V (see
f section 3.8.3). If V is viewed as a function of V , then the
f x
circuit is an NMOS implementation of a NOT gate. In logic terms this circuit implements
nMOS inverterthe function f = x. Figure 3.5b gives a simplified circuit diagram in which the connection
to the positive terminal on the power supply is indicated by an arrow labeled VDD and the

VDD nMOS circuits need a resistor Vto

DD limit the

current passing through the nMOS transistors

when thereR is a signal path to
R ground. Normally
+
5 V another transistor is used for this purpose.
- V f V f
R
Vx Vx
Vx x nMOSFET Vf f
Vf GND 0 open VDD 1
VDD 1 closed GND 0
(a) Circuit diagram (b) Simplified circuit diagram
Vx

x f x f

(c) Graphical symbols

Simplified circuit diagram

Figure 3.5 A NOT gate built using NMOS technology.
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 7 / 57
arallel connection represents the OR function. Using NMOS transistors,
thenMOS NAND asgate
series connection depicted in Figure 3.6a. If Vx1 = Vx2 = 5 V,
Vf

VDD Vx1
x1 x2 f

Vx1 Vx2V x x1 x2 T1 0 0
T2 1V f ( x1 , x2 )
f
2 0 1 1
GND GND 0 0 open open
1 0
V
1 DD 1
GND VDD 0 1 open closed
1 1 V
0 DD 1
Vf VDD GND 1 0 closed open VDD 1
VDD VDD 1(a) Circuit
1 closed closed GND
(b) Truth table 0
Vx1 T1
x1 x2 f
x1 x1
f f
0 x 20 1 x2
Vx2 T2 0 1 1
1 0 1
1 1 0 (c) Graphical symbols

Figure 3.6 NMOS realization of a NAND gate.

(a) Circuit (b) Truth table
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 8 / 57
er, as depicted in Figure 3.9.
nMOS NOR gate
x1 x2 f
Vf
VDD
0 0 1
V x1 Vx2 0 1 0
1 0 0
1 1 0

(a) Circuit (b) Truth table

x1 x2 f
Vf
0 0 1
V x1 T1 Vx2 T2 x1 0 1 0 x1
x2 1 0 0 f x2 f
1 1 0

(b) Truth table

(c) Graphical symbols
Vx1 (a) V
Circuit
x2 x1 x2 T1 T2 Vf f ( x1 , x2 )
GND GND 0 Figure
0 open
3.7 NMOS realization of a NOR 1gate.
open V DD
GND VDD 0 1 open closed GND 0
VxDD GND 1 0 closed
x1 open GND 0
1
VxDD VDD 1 f 1 closed
x closed GND f 0
2 2

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 9 / 57

 Vf
nMOS AND gate 3.3 CMOS Logic Gates 85
A
VDD VDD V x1
x1 x2 f

V x2 0 0 0
0 1 0
1 0 0
Vf
1 1 1
T3
A (a) Circuit (b) Truth table
V x1 T1
x1 x2 f

V x2 0 x01 0 x1
T2 f f
0 x12 0 x2
1 0 0
1 1 1

(a) Circuit (b) Truth table (c) Graphical symbols

Vx1 Vx2 x1 x2 T1 T2 A T3 Vf f ( x1 , x2 )
GND GND 0 0 openFigure
open
3.8 VDD
NMOS closed of
realization GND 0
an AND gate.
GND VDD 0 1 open closed VDD closed GND 0
x x1
V1DD GND f1 0 closed open f VDD closed GND 0
x x2
V2DD VDD 1 1 closed closed GND open VDD 1

M. Saghir (EECE 320 – Summer 2023)

3.3 CMOS Logic Gates
Implementation Technology 10 / 57
 nMOS OR gate
APTER 3 • Implementation Technology Vf
x1 x2 f
VDD VDD
0 0 0
Vx1 Vx2 0 1 1
1 0 1
1 1 1

Vf
(a) Circuit (b) Truth table
x1 x2 f
T3
A 0 0 0
Vx1 T1 V x2 T2 x1 0 1 1 x1
x2 1 0 1 f x2 f
1 1 1

Vx1 Vx(a)
2
Circuit
x1 x2 T1 T2(b) TruthAtable (c)T3
Graphical symbols
Vf f ( x1 , x2 )
GND GND 0 0 open open VDD closed GND 0
Figure 3.9 NMOS realization of an OR gate.
GND VDD 0 1 open closed GND open VDD 1
VDD
x1 GND 1 0 closedx 1 open GND open VDD 1
VDD
x2 VDD 1 f circuits
1 closed x 2 closed
in Figures GND
3.5 through 3.9f canopen VDD by the
be characterized 1 block diagram in F
3.10. The concept of CMOS circuits is based on replacing the pull-up device with a pu
network (PUN) that is built using PMOS transistors, such that the functions realized b
PDN and PUN networks are complements of each other. Then a logic circuit, such
M. Saghir (EECE 320 – Summer 2023) typical logic
(c) Graphical gate, is implemented
Implementation
symbols Technology as indicated in Figure 3.11. For any given11
valuati
/ 57
 February 27, 2008 10:20 vra_29532_ch03 Sheet number 11 Page numbe
nMOS circuit structure

3.3

VDD
nMOS circuits implement logic
functions by connecting a network
of nMOS transistors to a pull-up
device that functions as a resistor.
Vf
The nMOS transistor network is
Vx1
designed to pull the circuit output to Pull-down network
VSS (GND). That is why it is called a (PDN)
V xn
pull-down network (PDN).

nMOSStructure
Figure 3.10 circuitof an NMOS circu

M. Saghir (EECE 320 – Summer 2023) Implementation Technology VDD 12 / 57

CMOS circuits

Most digital circuits today are built using complementary MOS

(CMOS) technology. In a CMOS circuit the pull-up device is replaced
by a pull-up network (PUN) of pMOS transistors.

A CMOS circuit consists of two parts: A PUN of pMOS transistors that

can pull Vf up to VDD , and a PDN of nMOS transistors that can pull
Vf down to GND. Only one of these networks can affect Vf at a time.

Both the PUN and the PDN use the same number of transistors that
would be organized to implement complementary (dual) functions.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 13 / 57

Generalized CMOS
Figurecircuit
3.10 Structure of an NMOS circuit.

VDD

Pull-up network
(PUN)

Vf

Vx1
Pull-down network
(PDN)
Vxn

Figure 3.11 Structure of a CMOS circuit.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 14 / 57
CMOS inverter
VDD

CHAPTER 3 • Implementation Technology

T1
VDD

Vx Vf
T1 x T1 T2 f
T2
Vx Vf 0 on off 1
x1 T 1 T 2 on f
off 0
T2
0 on off 1
(a) Circuit (b) Truth1 table
off and
on transistor
0 states

Figure(a)
3.12
Circuit CMOS realization of aand
(b) Truth table NOT gate. states
transistor

Figure 3.12 CMOS realization of a NOT gate.

VDD
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 15 / 57
 DD
(a) Circuit (b) Truth table and transistor states
CMOS NAND gate
Figure 3.12 CMOS realization of a NOT gate.

T1 T2
VDD
Vf

T1 T3 T2 x1 x2 T1 T2 T3 T4 f

Vf 0 0 on on off off 1
0 1 on off off on 1
V x1 T3 x1 x2 T1 T2 T3 T4
T4 1 0 off on on
f
off 1
01 01 on off
on off
off offon 1
on 0
0 1 on off off on 1
V x2 T4 off on on off
1 0 1
1 1 off off on on 0
(a) Circuit (b) Truth table and transistor states

(a) Circuit (b) Truth table and transistor states

ure 3.13 CMOS realization of a NAND gate.
Figure 3.13 CMOS realization of a NAND gate.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 16 / 57

 A CMOS AND gate is built by connecting a NAND gate to an inverter, as illustrated
in CMOS
Figure [Link] gate
Similarly, an OR gate is constructed with a NOR gate followed by a NOT
gate.
T1

VDD

T2
V x1 T1
x1 x2 T1 T2 T3 T4 f
Vf
0 0 on on off off 1
Vx2
T3 T4 T2 0 1 on off off on 0
Vf
1x 1 x02 Toff
1 T 2on
T 3 on
T 4 off f 0
10 10 off off on on 1
on on off off
0
T3 T4 0 1 on off off on 0
1 0 off on on off 0
(a) Circuit (b) Truth
1 1 table
off and transistor
off on on 0 states

gure 3.14 CMOS realization of a NOR

(a) Circuit gate.
(b) Truth table and transistor states

Figure 3.14 CMOS realization of a NOR gate.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 17 / 57
CMOS AND gate
CHAPTER 3 • Implementation Technology

VDD VDD

Vf

Vx1

Vx2

Figure 3.15 CMOS realization of an AND gate.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 18 / 57

Designing a complex CMOS logic circuit

Capture the circuit’s functionality as a logic function f(x1 , x2 , ..., xn ).

Design the PUN for f = 1 using pMOS transistors. Because pMOS

transistors switch on when their gate inputs are low, the PUN must
implement f expressed using complemented inputs: f(x1 , x2 , ...xn ).

Design the PDN for f = 0 using nMOS transistors. Because nMOS

transistors switch on when their gate inputs are high, the PDN must
implement f expressed using uncomplemented inputs:
f(x1 , x2 , ...xn ).

In both the PUN and PDN, implement OR operations using parallel

transistor structures, and AND operations using series transistor
structures.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 19 / 57

Example: Design a CMOS circuit to implement
f = x1 + x2 x3 3.4 N

VDD

Step 1: The logic function is already

expressed using complemented inputs,
so we can design the PUN to implement
f = x1 + x2 x3 using three pMOS
transistors.
Vf
Step 2: The complement of f can be
Vx1
derived using DeMorgan’s theorem.
f = x1 · (x2 + x3 ). Because f is already
expressed using uncomplenented inputs, V x2
we can design the PDN using three V x3
nMOS transistors.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology

Figure 3.16 The circuit for Example
20 / 57
3
More CMOS logic circuit design

What if the (optimized) logic function we are

trying to implement includes complemented
and uncomplemented variables?
x1 x2
Example: Considerf the logic function
f(x1 , x2 , x3 ) = (x1 + x2 ) · x3
a
x1To design the PUN we must express f
using complemented input variables only.
But f is expressedausing x1 , x2 , and x3 . f
x2How do we handle x3 ? We define a new
variable a = x3 . It follows that a = x3 , and
we can express f = (x1 + x2 ) · a.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 21 / 57

More CMOS logic circuit design (2)

f
To design the PDN we must express f
using uncomplemented input variables only. x1
But f = x1 x2 + x3 and we must once again
handle x3 . Since a = x3 it follows that a
f = x1 x2 + a. x2

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 22 / 57

CMOS logic circuit implementation of f = (x1 + x2 ) · x3

x1 x2

x3 a f

x1
a
x2

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 23 / 57

Propagation delay
Logic gates are made of networks of transistors that have physical
attributes such as on/off switching times, parasitic capacitance, and
internal resistance. These attributes are related to the physical layout
and dimensions of the transistors, and they result in a signal
propagation delay inside a logic gate.

Propagation delay is the amount of time it takes the output of a logic

gate to change when one or more of its inputs change. More
accurately, it is the time it takes the voltage at the gate output to rise
or fall to 50% of VDD in response to a voltage rise or fall on a gate
input reaching 50% of VDD .

The time it takes a gate output to rise from 10% to 90% of VDD is
called the rise time (tr ), and the time it takes to fall from 90% to 10%
of VDD is called the fall time (tf ). Both tr and tf depend on the
physical characteristics of the gate’s transistors, which are typically
designed so that tr ≈ tf .
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 24 / 57
 Vx to cause a change in VA . This interval is called the propagation delay, often written tp ,
of the inverter. It is the time from when Vx reaches 50 percent of VDD until VA reaches the
Propagation
same level. delay in a CMOS inverter

VDD

Vx 50% 50%
Gnd

Propagation delay Propagation delay

VDD
90% 90%
Vf 50% 50%
Gnd 10% 10%
tr tf

Figure 3.48 Voltage waveforms for logic gates.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 25 / 57
DO NOT COPY
Fan-in3.3.5

Theobtained
Fan-In
The number of inputs that a gate can have in a particular logic family is called
the logic family’s fan-in. CMOS gates with more than two inputs can be
number of inputs
by extending on a logicdesigns
series-parallel gate isoncalled
Figuresits fan-in.
3-13 and 3-15 Although
in the

DO NOT COPY obvious

why,
series
manner. For example,

number of inputs.
in transistors
practice,limits
and 6 for NAND gates.
Figure

In practice,
mostthelogic
fan-ingates
3-16 shows

however,
of CMOShave
a 3-input
a logic gate can be designed with an arbitrary number of inputs,
gate’s
CMOS
In principle, you could design a CMOS NAND or NOR gate with a very
large propagation delay increases as athefunction
additive “on”
a fan-in
gates, typicallybetween
NAND

of itsresistance
to 4 for NOR
gate. the
fan-in. This
1 and
of
gates4.
is

DO NOT COPYA logicAsfunction

the number

the corresponding
thecient
multiple
of inputs is
requiring
as switching
a cascade
logic levels,
or impractical.
a increased,
delay.
thea large
Gates with resulting
CMOS gate
large number
ofHowever,
logic gates
at some
numbercircuit
of inputs
designers
of inputs
with fewer
point
generally
canmay becompen-
sate by increasing the size of the series transistors to reduce their resistance and
implemented [Link]-
this becomes
can be made
Despite
willfaster
be and
faster

DO NOT COPY
smaller
than by cascading gates
an equivalent logicwith
gate fewer
withinputs. For example,
a large fan-in. Figure 3-17 shows
I1
17 I2
I1
m I3
I2
o the I3
I4

DO NOT COPY
cture of I4
OUT OUT
MOS I5
I5
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Copyright © 1999 by John F. Wakerly Copying Prohibited

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 26 / 57
 -out (a) Inverter that drives n other inverters N1
Fan-out
ure 3.48 illustrated timing delays for one NOT gate driving another. In real circuits
ic gate may be required to drive several others. The number of other gates x that a
f To inputs of
n other inverters
gate drives is called its fan-out. An example of fan-out is depicted in Figure 3.55a,
A logic
N1 that gate’s fan-out is inverters.
the numberV f of theofother
other gates that
of can be driven
hows an inverter drives the inputs of n other Each
contributes to the total capacitive loading on node f . In part (b) of the figure, To inputs
by its output. x
erters are represented by one large A gate’s
capacitor propagation
Cn . For simplicity, assumedelay
that eachincreases
n other with its fan-out
inverters
contributes a capacitance C and that Cn = n × C. Equation 3.4 shows that the
due to increased load capacitance. The problem can be overcome
by inserting a buffer between the C
ion delay increases in direct proportion to n.
n (a)gate
logic Inverter that drives n other inverters
and its load.
Vf
To inputs of
N1 x
n other inverters
f To inputs of
x
n other inverters Cn
(b) Equivalent circuit for timing purposes

Vf for n = 1 (b) Equivalent circuit for timing purposes

(a) Inverter that drives n other inverters
VDD
Vf for n = 1
Vf VDD
To inputs of
x
n other inverters
Vf for n = 4
Cn Vf for n = 4
Gnd Gnd
0 Time
0 Time
(b) Equivalent circuit for timing purposes (c) Propagation times for different values of n
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 27 / 57
 ch produces f = x. The simplest implementation of a buffer uses two inverters, as
in Figure 3.56a. Buffers can be created with different amounts of drive capability,
Buffers
ding on the sizes of the transistors (see Figure 3.49). In general, because they are
or driving higher-than-normal capacitive loads, buffers have transistors that are larger
hose in typical logic gates.
A buffer is aThelogic
graphical
gate symbol for a noninverting
designed to drive buffer is given
heavy (high-capacitance)
ure 3.56b.
nother typeloads
of buffer without incurring
is the inverting large the
buffer. It produces propagation
same output as an inverter, It has one input x,
delays.
but is builtone
with relatively
output large transistors.
f, and The graphical
it implements symbol
Vxthe for the
logic inverting f = x.
function
is the same as for the NOT gate; an inverting buffer is just a NOT gate that is capable Vf
ving large capacitive loads. In Figure 3.55 for large values of n an inverting buffer
be used forA thebuffer is implemented
inverter labeled N1 . as a pair of back-to-back inverters. It can
addition todrive high loads by usingperformance
their use for improving the speed transistors with buffers
of circuits, largerareW/L ratios than the
sed when high current flow is needed to drive external devices. Buffers can handle
ones used in regular logic gates. This reduces internal resistance,
which reduces propagation delay and increases drive current.
VDD

(a) Implementation of a buffer

Vx
Vf
x f

(b) Graphical symbol

Figure 3.56 A noninverting buffer.

(a) Implementation of a buffer
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 28 / 57
 control input, called enable, e. The graphical symbol for a tri-state buffer is given in Figure
sconnected from the output f . When e = 1, the buffer drives the value of x onto f ,
3.57a. The enable input is used to determine whether or not the tri-state buffer produces
ausing f =signal,
Tri-state buffers
an output x. This behavior in
as illustrated is described
Figure 3.57b. in truth-table
When e = form part (c)
0, theinbuffer of the figure.
is completely
e For
e two rows of
disconnected fromthethe
table where
output e = 0,e the
f . When = 1,output is denoted
the buffer drives theby value
the logic
of x value
onto f Z,
, which
called fthe
causing = high-impedance
x. This behavior isstate.
describedTheinname tri-state
truth-table in part (c)
formderives from the figure.
of the fact that
Forthere are
wo
thenormal
two rows states
of thefor a logic
table where e = 0,0the
signal, andoutput
1, andis Zdenoted
represents
by thea logic
third value
statex Z,
that produces no
which f
is called
utput the high-impedance
signal. Figure 3.57d state.
showsThe name tri-state
a possible derives fromof
implementation thethe
facttri-state
that there are
buffer.
normalA
twoFigure 3.58 tri-state
states shows buffer
for a logic signal,
several 0isand
types a buffer
of 1, with
and Z represents
tri-state buffers. three
a third
The terminals:
state in
buffer thatpart input
(b)
produces has x,same
nothe output f, and
output signal. Figure 3.57d shows a possible implementation of the tri-state buffer.
ehavior asenable in part e
the buffersignal (a), except that when e =
. When e = 1 the tri-state buffer operates like
1, it produces f = x. Part (c) of a regular
Figure 3.58 shows several types of tri-state buffers. The buffer in part (b) has the same
e figure gives
behavior asbuffer.
a tri-state
the bufferBut
buffer
when
in part
for which
e =that
(a), except
the
0 the enable signal has
e = 1, it becomes
whenoutput
the opposite
produces f = electrically
behavior; that
x. Part (c) of isolated from
, when
the = 0, af tri-state
figuree gives = x, and when
buffer e = 1,thef enable
for which = Z. signal
The term often
has the used behavior;
opposite to describe
(a) that this type buffer
A tri-state
the input, and the tri-state buffer is said to be in a high-impedance
is, when e = 0, f = x, and when e = 1, f = Z. The term often used to describe this type
(Z) state.
e=0
e=0 e x f

e x f
e x f 0 0 Z
0 1 Z
xx f f 1 0 0
e=1 e=1
x x f f 1 1 1

(a) A
(a) A tri-state
tri-statebuffer
buffer (b) Equivalent circuit circuit
(b) Equivalent (c) Truth table

e x f
e Figure 3.57 Tri-state buffe
e x f

0 320 Z
0 – Summer
e
M. Saghir (EECE 2023) Implementation Technology 29 / 57
uit that implements the multiplexer using AND and OR gates is shown in
Tri-state buffers (2)
will present another way of building multiplexer circuits in section 3.9.2
them in detail in Chapter 6.
t of Figure 3.59, the outputs of the tri-state buffers are wired together. This
Tri-state
ssible because buffers
the control are
input s is used so
connected tothat
isolate logic
one of the two circuits
buffers from their loads. For
example, February
be in the high-impedance they can
state. The bex1 used
buffer
27, 2008 10:20 istovra_29532_ch03 s =
connect
active only multiple
when logic 61
0, number
Sheet circuits to 137 black
Page number
r is active only when s = 1. It would 1 be disastrous to allow both buffers
a shared data bus . The tri-state buffers
he same time. Doing so would create a short circuit between VDD and Gnd
would ensure that only one
wo buffers logic
producecircuit
differentwould
values. beFor given
example,access to the
assume that x1 = data
1 and bus at a time.
buffer produces the output VDD , and the x2 buffer produces Gnd. A short
between VTri-state
DD and Gnd, through the transistors in the tri-state buffers. The 3.8 Practical As
buffers can have active-low enable signals and inverted
nt that flows through such a short circuit is usually sufficient to destroy the
outputs. e e

x f x f
x1 f
(a) (b)
s

e e
x2

x f x f

Figure 3.59 An application of tri-state buffers.

(c) (d)

1 Figure 3.58 Four types of tri-state buffers.

A data bus is a group of wires used to transfer multiple binary signals simultaneously.
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 30 / 57
7400-series standard chips

Until the mid-1980’s logic circuits were implemented using standard

integrated circuits (ICs/chips) containing a few logic gates each.

The 7400-series standard chips were the most commonly used. They
were manufactured by several semiconductor companies, but each
chip included the same, standard, set of gates2 .

7400-series standard chips use plastic or ceramic dual-inline

packages (DIPs), which include two rows of connector pins.

2
A list of 7400-series chips and their data sheets is available on Wikipedia.
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 31 / 57
 7400-series chips exist, and they are described in the data books produced by manufacturers
of these chips [3–7]. Diagrams of some of the chips are also included in several textbooks,
7400-series standard chips (2)
such as [8–12].

Different variants of 7400-series chips are built using different

transistor technologies. For example, 74LS00 chips use
transistor-transistor (TTL) technology while 74HC00 chips use CMOS
technology.

Schematic of a 7404 hex(a)inverter

Dual-inlinechip.
package

VDD

Gnd

(b) Structure of 7404 chip

Figure 3.21 A 7400-series chip.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 32 / 57

 can be used to realize other functions.
Implementing f = x1 x2 + x2 x3 using 7400-series chips
VDD

7404

7408 7432

x1
x2
x3
f
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 33 / 57
Standard chip logic densities

7400-series standard chips are classified as small-scale integration

(SSI) devices, with 1-10 logic gates per chip. Devices with 10-100
logic gates are classified as medium-scale integration (MSI)
devices, while devices with more than 100 logic gates are classified
as large-scale integration (LSI) devices.

Most complex digital systems today are implemented using very

large scale integration (VLSI) devices consisting of hundreds of
thousands to tens of millions of logic gates. Examples include
programmable logic devices and application-specific integrated
circuits (ASICs).

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 34 / 57

 chips, comprise only a few logic gates. The technology used to produce these chips is
Standard
referredchip usageintegration (SSI). Chips that include slightly more logic circuitry,
to as small-scale
typically about 10 to 100 gates, represent medium-scale integration (MSI). Until the mid-
1980s chips that were too large to qualify as MSI were classified as large-scale integration
(LSI). In recent years the concept of classifying circuits according to their size has become
of little practical use. Most integrated circuits today contain many thousands or millions
Except for buffers and very simple designs, 7400-series chips are
of transistors. Regardless of their exact size, these large chips are said to be made with
rarely usedscale
very large in contemporary digital systems
integration (VLSI) technology. The trenddue to their
in digital lowproducts
hardware logic is
to integrate
densities andas much
bulkycircuitry as possible onto a single chip. Thus most of the chips used
packages.
today are built with VLSI technology, and the older types of chips are used rarely.

The 74244 octal buffer/line driver chip:

Pin 12

Pin 14

Pin 16

Pin 18

Pin 19
Pin 11

Pin 13

Pin 15

Pin 17
Pin 1
Pin 2

Pin 4

Pin 6

Pin 8

Pin 3

Pin 5

Pin 7

Pin 9
Figure 3.23 The 74244 buffer chip.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 35 / 57

February 27, 2008 10:20 vra_29532_ch03 Sheet number 23 Page number 99 black
Programmable Logic Array (PLA)
The PLA is a programmable logic device (PLD) that contains
hundreds of AND/OR logic gates and3.6programmable connectors.
Programmable Logic Devices 9

PLAs implement arbitrary logic functions expressed as SOP terms.

x1 x2 xn

Input buffers
and
inverters

x1 x1 xn xn

P1

AND plane OR plane

Pk

f1 fm

M. Saghir (EECE 320 – Summer 2023)Figure 3.25 General Technology

Implementation structure of a PLA. 36 / 57
 Anatomy of a PLAImplementation Technology
100 CHAPTER 3 •

x1 x2 x3

Programmable
connections

OR plane
P1

P2

P3

P4

AND plane

f1 f2

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 37 / 57

Common schematic diagram of a3.6PLA
Programmable Logic Devices

x1 x2 x3

OR plane

P1

P2

P3

P4

AND plane

f1 f2
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 38 / 57
Programmable Array Logic (PAL)

Although PLAs offer a high degree of flexibility to implement arbitrary

logic functions, the programmable connectors in their AND/OR planes
make them expensive to manufacture and slow.

A PAL is another kind of programmable logic device where only the

AND plane is programmable, but the OR plane is not. As a result,
PALs are less expensive to manufacture and faster than PLAs, and
they are more commonly used in digital designs.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 39 / 57

Common
C H A P T E schematic
R 3 • diagram
Implementation of a PAL
Technology

x1 x2 x3

P1

f1
P2

P3

f2
P4

AND plane

Figure 3.28 An example of a PAL.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 40 / 57
 PAL OR-gate outputs
February 27, 2008 10:20 vra_29532_ch03 Sheet number 27 Page number 103 black

PALs commonly add extra circuitry to their OR-gate outputs. This

provides added functionality and design flexibility. An output OR gate
and its extra circuitry are typically implemented
3.6
as a single unit called
Programmable Logic Devices
a macro cell.
Select
Enable

f1

Flip-ßop

D Q

Clock

To AND plane

Figure 3.29 Extra circuitry added to OR-gate outputs from Figure 3.28.
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 41 / 57
Programming PLAs and PALs

The programmable connectors inside a PLA or a PAL are

implemented using special transistors whose states can be
configured ON or OFF by applying appropriate electrical pulses to the
transistor gates. This is similar to the technology used to save data to
flash memory devices.

PLAs and PALs are programmed using CAD systems. Once a design
is ready the CAD system generates a device programming file called
a fuse map. This is downloaded to the device using a special
programming unit.

The ability to program and reprogram PLAs/PALs is a major

advantage that enables designers to fix bugs or modify functionality
even after a device has been deployed in the field.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 42 / 57

PLA and PAL Packaging

February 27, 2008 10:20

PLAs and PALs arevra_29532_ch03
available Sheet number 29 Page number 105 black
in DIP and plastic-leaded chip carrier
(PLCC) packaging. The latter use printed circuit board (PCB) sockets
that enable PLA/PAL chips to be easily Programmable removedLogic
3.6
and reprogrammed.
Devices 105

rd
boa
uit
irc
dc
nte
Pri

Figure 3.31 A PLCC package with socket.

3.6.4 2023)
M. Saghir (EECE 320 – Summer Complex Programmable
ImplementationLogic Devices (CPLDs)
Technology 43 / 57
 Complex
0:20
Programmable
vra_29532_ch03
Logic Devices (CPLDs)
Sheet number 30 Page number 106 black

PLAs and PALs are suitable for relatively small designs. CPLDs are
programmable logic devices that include multiple PAL-like blocks and
programmable
C HAPTER 3 • interconnects. They are used to implement relatively
Implementation Technology
large designs.
I/O block

I/O block
PAL-like PAL-like
block block

Interconnection wires
I/O block

I/O block
PAL-like PAL-like
block block

Figure 3.32
M. Saghir (EECE 320 – Summer 2023)
Structure of a complex programmable logic device (CPLD).
Implementation Technology 44 / 57
PAL-like block inside a CPLD 3.6 Programmable Logic Devices 107

PAL-like block (details not shown)

PAL-like block

D Q

D Q

D Q

Figure 3.33
M. Saghir (EECE 320 – Summer 2023) A section of the CPLD in FigureTechnology
Implementation 3.32. 45 / 57
08 10:20 vra_29532_ch03 Sheet number 32 Page number 108 black

CPLD packaging and programming

08 CPLDs E R 3quad
C H A P Tuse • flat pack (QFP)
Implementation packaging, and are commonly
Technology
programmed using in-system programming techniques like JTAG.

A JTAG port can be used to connect a PCB with one or more CPLDs
to a host computer. This enables a device configuration file
(generated by a CAD system) to be downloaded to the CPLDs.

CPLDs use non-volatile, on-chip memory to store the device

(a) CPLD in a Quad Flat Pack (QFP) package
configuration file, which specifies how the on-chip connectors are
programmed.
To computer

Printed
circuit board

(b) JTAG programming

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 46 / 57
 Field Programmable
ebruary 27, 2008 10:20
vra_29532_ch03 Gate
Sheet number 34 Arrays (FPGAs)
Page number 110 black

FPGAs are high-density programmable logic devices that can

110 • Implementation Technology
implementC Hdigital
APTER 3
systems with millions of logic-gate equivalents.
Logic block Interconnection switches

I/O block

I/O block

I/O block
I/O block

(a) General structure of an FPGA

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 47 / 57
Field Programmable Gate Arrays (FPGAs) (2)

FPGAs contain programmable logic blocks, a programmable

interconnection network, and I/O blocks.
– Logic blocks are used to implement simple logic functions, and are
organized in a two-dimensional grid.
– The interconnection network consists of horizontal and vertical wires
(routing channels) and programmable switches. The switches connect
horizontal and vertical wires, and they connect logic blocks and I/O
blocks to routing channels.
– I/O blocks connect the FPGA logic and interconnection fabric to the
package pins.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 48 / 57

 of three multiplexers, which, depending on the valuation of x1 and x2 ,
the structure of a small LUT. It has two inputs, x and
of1the
xstorage
2 , and one output,of thef . LUT. We introduced m
The advantage of BGA packages is that the pins areone very fourhence
small; cellspins
more as the
canoutput
be
of Lookup providedtable
implementing onany (LUT)
logic
a relatively function
small [Link] two variables.
2.8.2 and will Because
discuss storagea two-variable
cells in Chapter 10.
Each LUT
logic block To see how a logicandfunction canAbe realized in the two-input LU
s four rows, this hasinfouran FPGA typically
storage has aOne
cells. small cell
table
number of inputs
corresponds
in Figure 3.36b.
outputs.
to the
The function
output
f1 from this table can be stored in the
variety of FPGA products are on the market, featuring different types of logic blocks. The
row of themost
truth [Link]
commonly The input
logic blockvariables x1 and
is a lookup table (LUT),x2whichare contains
used asstorage the select
cells thatinputs
iplexers, An
which,
are FPGA’s
used todepending
implement logic on
a smallblocks
logic are Each
the function.
valuation commonly
of and ximplemented
cellxis1 capable 2 , holding
of selecta the using
singlecontent
logic ofmemory
value, either 0called
or 1. Thelookup
stored value tables
is produced(LUTs).
as the output of x 1 the storage cell. LUTs
devices
ur storageofcells assizes
themayoutput of the LUT. Weis introduced multiplexers in section
various be created, where the size defined by the number of inputs. Figure
l discuss 3.36a
storageshowscells in Chapter
the structure 10.
of a small LUT. It has two inputs, x1 and x2 , and0/1one output, f .
It is capable of implementing any logic function of n
An
ow a logic n-inputcan
function LUT be consists
realized inofthe 2 two-bit
a two-input variables. Because0/1
memory
LUT, consider a two-variable
followed
truth table has four rows, this LUT has four storage cells. One cell corresponds to the output
theby a 2n -to-1 1 2
truth f
x x

e 3.36b. The
value function
multiplexer.
in each row of f1A from
the this table
sequence
truth table. can
of
The input 2nbebits
stored
variables x1 andcanxin the
2 arebe usedLUT theas
as 0/1
stored illustrated
a LUTinto
ininputs
select 0 0
0 1
of three multiplexers, which, depending on the valuation of x and x , select
1 2 0/1the content of
implement
one of the four storage nas-input
anycells logic
the output function.
of the LUT. We introduced multiplexers in section 1 0
2 x 1 1
2.8.2 and will discuss storage cells in Chapter 10.
x1 To see how a logic function can be realized in the two-input LUT, consider the truth
Example: 2-input
table in Figure 3.36b. LUT
The function implementing
f1 from this table can be stored1in the(a)LUTf =x x +x x
Circuit 2 : LUT
for a two-input
1 as2illustrated
1 in (b) f
1 = x1 x

0/1
x1 x
1
0/1 x
1 x
2 f
1
0/1 f 1
0/1 0/1 0 x01 x
2 11 f 0
f f
1
0/1 0 01 0 01 0
0/1
1 00 1 00
0/1 1
1 0 0
x2 1 11
x2 11 1 x
2

(a) Circuit for a two-input LUT (b) f = x1 x2 +x

+ x112x 2(c) Storage cell contents in the LUT
x
(a) Circuit for a two-input LUT (b) f
1 =1 x1 x2

Figure 3.36 A two-input lookup table (LUT).

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 49 / 57
 that PALs usually have extra circuitry included with their AND-OR gates. The same is true
for FPGAs, which xusually
1 have extra circuitry, besides a LUT, in each logic block. Figure
Lookup table (LUT) (2) 3.38 shows how a xflip-flop
2 may be included in an FPGA logic block. As discussed for

0/1
x1
0/1
x
2
0/1
0/1
0/1
0/1 f
3-input LUTs can 0/1
0/1
implement arbitrary 0/1
0/1
f

3-input logic functions. 0/1

0/1

Commercial FPGAs use 0/1

0/1
x 0/1
4-6-input LUTs. 3
0/1
Figure
x
3 3.37 A three-input LUT.
Additional logic circuits
Figure 3.37 A three-input LUT.
like flip-flops and Select
multiplexers are also
Select
used with LUTs to Out
Flip-flop
provide added flexibility In 1 Out
In 2 In Flip-flop
D Q
and functionality. In 3 In
1
LUT
2 LUT D Q
In 3 Clock
Clock

Figure 3.38 Inclusion of a flip-flop in an FPGA logic block.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 50 / 57
Programmable interconnect
N B
!

N


N 0 N 0
0 B
1 B

0 0
N N N!
1 0

B
 0
1 B
1
B
1

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 51 / 57

FPGA packaging and programming

I/O block
FPGAs use pin grid array (PGA) or ball grid array (BGA)
(a) General structure of an FPGA
packaging, and are also programmed using in-system programming
techniques like JTAG.

(b) Pin grid array (PGA) package (bottom view)

FPGAs use volatile on-chip configuration memories. They must be
Figure 3.35 A field-programmable gate array (FPGA).
programmed (configured) as soon as they are powered up.
PLCC and QFP packages described earlier. Figure 3.35b depicts another type of package,
called a pin grid array (PGA). A PGA package may have up to a few hundred pins in
FPGAs use configuration bit streams to program their LUTs and
total, which extend straight outward from the bottom of the package, in a grid pattern. Yet
another packaging technology that has emerged is known as the ball grid array (BGA).
interconnection switches. Bit streams can be downloaded from a host
The BGA is similar to the PGA except that the pins are small round balls, instead of posts.

computer through a JTAG port, or they can be loaded from an

on-board programmable read-only memory (PROM) on power up.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 52 / 57

Custom integrated circuits

Contemporary programmable logic devices offer high levels of logic

density and design flexibility, which often come at the expense of area
overhead (for programmable switches), lower speeds, and high power
consumption.

An alternative to PLDs is full-custom integrated circuits where

designers can decide on the number transistors to use, the logic gates
to build, and how they should be connected. This always results in the
best overall area-efficiency, circuit speed, and power consumption.

Full-custom chips are very expensive to design and manufacture, and

only make sense if there is a large enough market to recoup their
design and manufacturing costs. This is why only high-volume
devices like microprocessors or memory chips are designed as
full-custom chips.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 53 / 57

 often called application-specific integrated circuits (ASICs). This technology is illustrated
in Figure 3.40, which depicts a small portion of a chip. The rows of logic gates may be
Standard cells
connected by wires that are created in the routing channels between the rows of gates. In
general, many types of logic gates may be used in such a chip. The available gates are
prebuilt and are stored in a library that can be accessed by the designer. In Figure 3.40 the
A technology
wires are drawnfor implementing
in two colors. This schemeapplication-specific
is used because metal wires can integrated
be created
on integrated circuits in multiple layers, which makes it possible for two wires to cross
circuits (ASICs). The technology relies on libraries of standard
one another without creating a short circuit. The blue wires represent one layer of metal logic
wires, and the black wires are a different layer. Each
gates that have been pre-designed using a specific transistor blue square represents a hard-wired
connection (called a via) between a wire on one layer and a wire on the other layer. In
fabrication process
current technology technology
it is possible (e.g.
to have eight 10layers
or more nmofCMOS).
metal wiring. Some of the

Designers use the standard cell libraries and CAD tools to organize
the logic gates in rows separated by interconnection wires.

x f
1 2

x
2

x
3
f
1

Figure 3.40 A section of two rows in a standard-cell chip.

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 54 / 57

Gate arrays

Another technology
February 27, 2008 10:20
for implementing
vra_29532_ch03
ASICs where only part of a chip
Sheet number 41 Page number 117 black

is prefabricated with logic gates (typically 2- or 3-input NAND), and a

designer can customize a circuit by specifying how to connect its
Custom Chips, Standard Cells, and Gate Arrays
3.7 117
logic
gates.

Figure 3.41 A sea-of-gates gate array.

f
1

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 55 / 57

Using gateFigure
arrays
3.41 toA implement f1 = x2 x3 + x1 x3
sea-of-gates gate array.

f
1

x
1

x
2

x
3

Figure 3.42 The logic function f1 = x2 x3 + x1 x3 in the gate array of Figure 3.41.
M. Saghir (EECE 320 – Summer 2023) Implementation Technology 56 / 57
Summary of chip packaging technologies

Technology Devices Pin Count

Dual inline package (DIP) standard chips < 64
Plastic-leaded chip carrier (PLCC) PLAs, PALs < 100
Quad flat pack (QFP) CPLDs 100-256
Pin grid array (PGA) FPGAs 200+
Ball grid array (BGA) FPGAs 200+

M. Saghir (EECE 320 – Summer 2023) Implementation Technology 57 / 57