1. Subtract 11001 from 11011.
2. Determine the output waveform X for the circuit shown in figure, with input waveforms
shown.
3. Compare Decoder and Demultiplexer.
4. Draw the timing diagram for the circuit shown in figure showing the outputs of G1, G2 and
G3 with the input waveforms A and B as indicated.
5. Convert T Flip Flop to D Flip Flop
6. Give the guidelines for State Assignment.
7. Compare pulsed mode and fundamental mode asynchronous circuit.
8. State the difference between PROM, PLA, PAL.
9. Write the behavioral model for D Flip Flop.
10. State the advantages of Package declaration and Component declaration.
11 (a) (i)Design a TTL logic circuit for a 2-input NAND gate. (6)
(ii)Draw the CMOS logic circuit for 2 input NOR gate. (7)
11(b) (i)Explain error correction and detection using Hamming Code with an example.
(ii)Give the circuit for parity generator and parity checker (3)
12 (a) An optical encoder placed in a shaft of a DC Motor sends error signal while measuring speed.
Suggest a solution and explain. (13)
12(b) (i)State and prove Simplification theorems in Boolean Algebra. (7)
(ii)State and prove basic theorems and laws of Boolean Algebra. (6)
13(a) Design a Synchronous Up/Down Counter using JK Flip Flop.
13(b) Suppose a parking area in a shop whose capacity is 10. The gate is closed as soon as the
capacity is reached. Design a circuit to count the number of cars using D flip flop. What
should be done to increase the capacity to 50.
14(a) Design an Asynchronous Sequential Circuit that has two inputs, X1 and X2 and one output
Z. When X1 = 0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will
cause output Z to be 1. The output Z will remain 1 until X1 returns to 0.
14(b) Implement 4 bit Binary to Gray code converter using PROM, PLA and PAL.
15(a) (i)Write a VHDL code for a 3-8 Decoder. (8)
(ii)Write the test bench for the above question.
15(b) Discuss the various data types, operators and attributes in VHDL.
16(a) Simplification of Boolean Expression results in optimized area, delay and power for any
digital circuit – Justify.
16(b) A 7-segment display displays A, b, C, d, E and F. Derive a SOP expression for segment ‘a’
using four inputs, A, B, C, D and then minimize the expression using Karnaugh Map