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ES9290 High-Performance Audio CODEC

The SABRE® ES9290 is a high-performance 32-bit stereo A/D and D/A CODEC designed for professional audio applications, featuring advanced audio quality specifications such as a DNR of +116dB and THD+N of -110dB/-108dB. It includes integrated programmable gain amplifiers, customizable filters, low latency direct monitoring, and supports multiple I/O formats including I2S and TDM. The ES9290 is packaged in a compact 40 pin QFN format, making it a cost-effective solution for high-quality audio interfaces.

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0% found this document useful (0 votes)

17 views138 pages

ES9290 High-Performance Audio CODEC

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hugosaldano

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Available Formats

Download as PDF, TXT or read online on Scribd

ES9290

32-bit Stereo Channel High Performance CODEC

Analog Reinvented Product Datasheet

The SABRE® ES9290 is a synchronous stereo analog-to-digital (A/D) and digital-to-analog (D/A) CODEC targeted for
professional audio interfaces such as Professional Audio Interfaces, Live stream media, High-quality microphones,
professional DAW (Digital Audio Workstation) Audio Recording, and Active speakers.
The ES9290 is a cost-effective solution that has 2 integrated ADCs & DACs which use ESS’ patented Hyperstream ® IV
Architecture, which delivers unprecedented audio sound quality and specifications, including a DNR of +116dB and a THD+N
of -110dB/-108dB (DAC/ADC) per channel. A direct monitoring path is also provided with very low latency.
The SABRE CODEC supports synchronous I2S master/slave, and TDM input and outputs.
The ES9290 has built-in programmable gain amplifiers (PGAs) with a gain of up to +30dB, 2V rms line driver buffers for
simplification of BOM requirements, custom pre-programmed filters as well as high pass filters that are complementary to
both ADC & DAC, and a Digital Full Biquad (DBQ) filter with many presets and for custom biquad filters.
The ES9290 ADCs have an Ultra-Low noise floor bandwidth of 200kHz. This bandwidth is up to 10 times wider than the
competition.
Low latency Direct Monitoring and stereo ADC/DAC mixing are new advanced features.

FEATURE DESCRIPTION
+116dB DNR per Ch, DAC & ADC
-110dB/-108dB THD+N per Ch. (DAC/ADC) High performance dynamic range and very low distortion for both
+122dB/+119dB DNR mono DAC/ADC differential ADCs & DACs
-116dB THD+N mono DAC differential
High Sample Rates Up to 768kHz (in 64FS mode)
Presets of digital optimal filters for ADC & DAC, and a DBQ for
Customizable Filter Characteristics
High Pass Filters and RIAA filters that are customizable
I2S & TDM inputs/outputs are available, TDM daisy chain is
Multiple I/O Formats Available
supported
Configured by microcontroller or other I2C/SPI source, or pins
I2C, SPI, and Hardware interface control
through Hardware Mode for simplification of control
Direct Monitoring Low Latency direct monitoring
PGA frontend with gain of +0 to +30dB in +3dB steps with 5kΩ
Programmable Input Amplifies (PGA)
input impedance
Digital Volume Control (I2C/SPI) -127 to +6dB in increments of +0.5dB
Digital Gain Control (I2C/SPI) +0 to +42dB in increments of +6dB for creating maximum gain
Integrated DAC Line Driver Simplifying BOM requirements for the DAC output stage
Programmable MICBIAS Programmable Microphone BIAS for Analog microphone support
Integrated Analog PLL Reduces need for additional clocks
200kHz bandwidth enabling higher resolution at higher sample
Ultra-Low Noise Floor Bandwidth on ADC
rates
Integrated low noise reference regulators Reduced BOM cost, PCB area and improved DNR
Low Power Consumption Simplifies power supply design
Low Pin Count Packaging 5mm x 5mm 40 pin QFN
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 1
VERSION 0.3.2

ES9290 Product Datasheet

ES9290 Product Datasheet

List of Tables
Table 1 - 40 QFN Pin List ...................................................................................................................................................... 12
Table 2 - Mode Pin Configuration Options ............................................................................................................................. 13
Table 3 - I2C Addresses ......................................................................................................................................................... 14
Table 4 - I2C Slave Interface Timing Definitions .................................................................................................................... 15
Table 5 - SPI Commands ...................................................................................................................................................... 16
Table 6 - SPI Slave Interface Timing ..................................................................................................................................... 17
Table 7 - Input Mode Selection with HW3 in Hardware Mode................................................................................................ 18
Table 8 - Mute Control in Hardware Mode ............................................................................................................................. 18
Table 9 - Analog ADC GPIO Functions in Hardware Mode ................................................................................................... 19
Table 10 - Digital PDM GPIO Functions in Hardware Mode .................................................................................................. 19
Table 11 - PGA Gain and Mic Bias in Hardware Mode .......................................................................................................... 19
Table 12 - ADC DC Block in Hardware Mode ........................................................................................................................ 19
Table 13 - Hardware Mode Pin Configurations ...................................................................................................................... 20
Table 14 - PDM Decoder Pins ............................................................................................................................................... 22
Table 15 - Pre-Programmed Digital Filter Descriptions .......................................................................................................... 31
Table 16 - ADC PCM Filter Latency....................................................................................................................................... 32
Table 17 - ADC PCM Filter Properties ................................................................................................................................... 34
Table 18 - ADC PCM Filter Frequency Response ................................................................................................................. 38
Table 19 - ADC PCM Filter Impulse Response...................................................................................................................... 42
Table 20 - ADC Minimum Phase 64FS Latency .................................................................................................................... 43
Table 21 - ADC Minimum Phase 64FS Properties................................................................................................................. 43
Table 22 - DAC PCM Filter Latency....................................................................................................................................... 45
Table 23 - DAC PCM Filter Properties ................................................................................................................................... 47
Table 24 - DAC PCM Filter Frequency Response ................................................................................................................. 51
Table 25 - DAC PCM Filter Impulse Response...................................................................................................................... 55
Table 26 - DAC Minimum Phase 64FS Latency .................................................................................................................... 56
Table 27 - DAC Minimum Phase 64FS Properties................................................................................................................. 56
Table 28 - Pre-Programmed DBQ Digital Filter Descriptions ................................................................................................. 58
Table 29 - DBQ Filter Properties............................................................................................................................................ 59
Table 30 - DBQ Filter Frequency Response .......................................................................................................................... 62
Table 31 - DBQ Filter Impulse Response .............................................................................................................................. 65
Table 32 - Daisy Chain Pins .................................................................................................................................................. 66
Table 33 - PCM Pin Connections........................................................................................................................................... 68
Table 34 - TDM Pin Connections ........................................................................................................................................... 69
Table 35 - GPIO Configuration .............................................................................................................................................. 70
Table 36 - APLL Divider Values for 44.1kHz Base Rates ...................................................................................................... 74
Table 37 - APLL Divider Values for 48kHz Base Rates ......................................................................................................... 74
Table 38 - Absolute Maximum Ratings .................................................................................................................................. 76
Table 39 - ESD Ratings ......................................................................................................................................................... 76
Table 40 - I/O Electrical Characteristics................................................................................................................................. 76
Table 41 - Recommended Operating Conditions ................................................................................................................... 77
Table 42 - Power Consumption ............................................................................................................................................. 78
Table 43 – ES9290 ADC Performance .................................................................................................................................. 79
Table 44 – ES9290 DAC Performance .................................................................................................................................. 80
7 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Table 45 - Register Map ........................................................................................................................................................ 84

Table 46 - Internal Pad Circuitry .......................................................................................................................................... 132
Table 47 - RPC-1 Classification Reflow Profile .................................................................................................................... 136
Table 48 - RPC-2 Pb Free Classification Temperature ........................................................................................................ 137
Table 49 - Ordering Information ........................................................................................................................................... 138

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 8
VERSION 0.3.2

ES9290 Product Datasheet

Applications
• Professional Digital Audio Workstation (DAW) Audio Recording
• Very High-Quality Microphones
• Live Stream Media
• Professional Audio Interfaces
• Powered (Active) Speakers

Functional Block Diagram

DVDD AVDD AVCC_LD

POWER
ACLK CLOCK DVDD SS/ADDR1/HW2
NETWORK MANAGEMENT
LDO MISO/ADDR0/
& CONTROL
PLL_REG APLL
MUTE_MCLK_CTRL
SCLK/SCL/HW1

CHIP_EN CLK DETECT / POR MOSI/SDA/HW0

I2C/SPI/HW Programmable
MIC BIAS MIC BIAS
Interface
GPIO1 MODE
Controller
GPIO2 BANDGAP VREF
GPIO3 Direct Monitoring
HW3/GPIO4 w/MIX Mode
DATA3 Low Noise Reg
DATA2
DIGITAL CORE
DATA1
VREF_BUF
DIGITAL FILTERS, VOLUME CONTROL

DATA_CLK DIGITAL AVCC_ADC

RT1 AUDIO
PORT
IN_P1 Hyperstream® IV Hyperstream® IV Line
PGA ADC
OUT_1
DAC Driver
IN_M1
SERIAL
INPUT/ GND_SNS
OUTPUT
IN_P2 Hyperstream® IV Hyperstream® IV Line
PGA ADC DAC Driver
OUT_2
IN_M2 TDM
I2S

Charge Pump AVCC_CP

DGND AGND_ADC AGND_DAC AGND_LD AGND_CP C1 C2 PNEG

Figure 1 - ES9290 Block Diagram

9 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

ES9290 Package
40 QFN Pinout
(Pin 41 is QFN package pad, see package dimensions)

Figure 2 - 40 QFN Pinout

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 10
VERSION 0.3.2

ES9290 Product Datasheet

40 QFN Pin List

Pin Name Pin Type Reset State Pin Description
1 AVCC_CP Power Power 3.3V Supply for Charge Pump
2 AVCC_LD Power Power 3.3V Supply for Line Driver
3 AGND_LD Ground Ground Analog Ground for Line Driver
4 OUT_1 AO Ground Line Driver Output 1
5 GND_SNS A I/O - Line Driver Ground Sense
6 OUT_2 AO Ground Line Driver Output 2
7 AGND_DAC Ground Ground Analog Ground for DAC
8 VREF_BUF A I/O P/D Low Noise Supply for DAC/ADC, internally generated
9 VREF A I/O P/D Low Noise Voltage Reference, internally generated
10 MICBIAS A I/O P/D Low Noise Supply for Microphone Bias, internally generated
11 AVCC_ADC Power Power 3.3V Supply for ADC
12 IN_P1 AI HiZ ADC Channel 1 Differential Positive (+) Input
13 IN_M1 AI HiZ ADC Channel 1 Differential Negative (-) Input
14 IN_M2 AI HiZ ADC Channel 2 Differential Negative (-) Input
15 IN_P2 AI HiZ ADC Channel 2 Differential Positive (+) Input
16 AGND_ADC Ground Ground Analog Ground for ADC
17 PLL_REG A I/O P/D Low Noise Supply for PLL, internally generated
18 MODE D I/O HiZ I2C/SPI Control Selection or HW Mode
19 ACLK Clock I HiZ Clock Input
20 CHIP_EN D I/O D I/O Active-High Chip Enable (Defines Reset State)
21 AVDD Power Power 3.3V Supply for Digital I/O
22 DGND Ground Ground Digital Ground for Digital Core
23 DVDD A I/O P/D 1.2V Supply for Digital Core, internally generated
24 DATA_CLK D I/O HiZ Serial Data Clock Pin
25 DATA1 D I/O HiZ Serial DATA1
26 DATA2 D I/O HiZ Serial DATA2
27 DATA3 D I/O HiZ Serial DATA3
28 GPIO1 D I/O HiZ General I/O 1
29 GPIO2 D I/O HiZ General I/O 2
30 GPIO3 D I/O HiZ General I/O 3
GPIO4 D I/O HiZ General I/O 4
31
HW3 D I/O HiZ Hardware 3 interface pin, controlled by MODE
MISO SPI Main In Sub Out pin, controlled by MODE
32 ADDR0 D I/O HiZ I2C Address 0 pin, controlled by MODE
MUTE_MCLK_CTRL Hardware Mute Control pin, controlled by MODE
SS SPI Slave Select pin, controlled by MODE
33 D I/O HiZ
ADDR1 I2C Address 1 pin, controlled by MODE
11 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

HW2 Hardware 2 interface pin, controlled by MODE

SCLK SPI Serial Clock pin, controlled by MODE
34 SCL D I/O HiZ I2C Serial Clock pin, controlled by MODE
HW1 Hardware 1 interface pin, controlled by MODE
MOSI SPI Main Out Sub In pin, controlled by MODE
35 SDA D I/O HiZ I2C Serial Data pin, controlled by MODE
HW0 Hardware 0 interface pin, controlled by MODE
36 RT1 D I/O HiZ Reserved. Must be connected to GND for normal operation.
37 AGND_CP Ground Ground Analog Ground for Charge Pump
38 PNEG A I/O Ground -3.3V Supply for Line Driver, internally generated.
39 C2 A I/O Neg Ground Charge Pump negative flying capacitor pin
40 C1 A I/O Ground Charge Pump positive flying capacitor pin
Not electrically connected, used for heat dissipation.
41 Package Pad1 - -
Connect to DGND.
Table 1 - 40 QFN Pin List
*Note: A = Analog, D = Digital, I/O = Digital Input/Output, P/D = Power Down

1 Pin 41 is the package pad. See 40 QFN package dimensions for sizing. Connect to DGND.
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 12
VERSION 0.3.2

ES9290 Product Datasheet

Feature List

Configuration Modes
The ES9290 has 4 control programming modes which are controlled by the state of the MODE pin (Pin 18).

MODE PIN Configuration

0 I²C Interface
Pull 0 HW control mode (see Hardware Mode Table)
Pull 1 HW control mode (see Hardware Mode Table)
1 SPI Interface
Table 2 - Mode Pin Configuration Options

Design Information
Hardware pins can be configured in 4 different ways. Each pin can be tied-high (1), pulled-high (Pull 1), pulled-low (Pull 0),
or tied-low (0). HW0 and HW1 pins are always tied-high or tied-low. These 4 options also apply to MUTE_CTRL.

1 Pull 1 Pull 0 0
AVDD or GPIO AVDD or GPIO

HW0/ HW0/
47Ω HW1/ 47k HW2/ HW2/ HW1/
HW2/ HW3/ HW3/ HW2/
HW3/ MODE 47k MODE 47Ω HW3/
MODE MODE
GND or GPIO GND or GPIO

Figure 3 - Example Hardware Mode Pin Configurations

13 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Software Mode
The ES9290 supports I²C or SPI serial communication in software mode. There are two types of registers, read/write
registers and read-only registers. Software modes are set when the MODE pin is a 0 (0V) for I2C or a 1 (AVDD) for SPI.
A system clock is not required to read and write registers.
I2C Slave Interface Commands
• MODE (Pin 18) – 0 V I2C Address ADDR1 ADDR0
• Connect per I²C standard 0x30 GND GND
o SDA (Pin 35)
0x32 GND AVDD
o SCL (Pin 34)
o ADDR0 (Pin 32) 0x34 AVDD GND
o ADDR1 (Pin 33) 0x36 AVDD AVDD
Table 3 - I2C Addresses

Figure 4 - I2C Write Example

Figure 5 - I2C Read Example

Note: CHIP_ID is 0xAA in Register 225 (0xE1)

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 14
VERSION 0.3.2

ES9290 Product Datasheet

I2C Slave Interface Timing

Figure 6 - I2C Slave Control Interface Timing

CLK Standard-Mode Fast-Mode

Parameter Symbol Unit
Constraint MIN MAX MIN MAX
SCL Clock Frequency fSCL < CLK/20 0 100 0 400 kHz
START condition hold time tHD;STA 4.0 - 0.6 - s
LOW period of SCL tLOW >10/CLK 4.7 - 1.3 - s
HIGH period of SCL (>10/CLK) tHIGH >10/CLK 4.0 - 0.6 - s
START condition setup time (repeat) tSU;STA 4.7 - 0.6 - s
SDA hold time from SCL falling
- All except NACK read tHD;DAT 0 - 0 - s
2/CLK 2/CLK s
- NACK read only
SDA setup time from SCL rising tSU;DAT 250 - 100 - ns
Rise time of SDA and SCL tr - 1000 - 300 ns
Fall time of SDA and SCL tf - 300 - 300 ns
STOP condition setup time tSU;STO 4 - 0.6 - s
Bus free time between transmissions tBUF 4.7 - 1.3 - s
Capacitive load for each bus line Cb - 400 - 400 pF
Table 4 - I C Slave Interface Timing Definitions
2

15 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

SPI Slave Interface Commands

• MODE (Pin 18) - AVDD
• Connect per SPI standard
o MOSI (Pin 35) SPI Command First Byte
o SCLK (Pin 34) Write 0x03
o SS (Pin 33)
Read 0x01
o MISO (Pin 32)
Table 5 - SPI Commands

Figure 7 - SPI Single Byte Write

Figure 8 - SPI Single Byte Read

Note: CHIP_ID is 0xAA in Register 225 (0xE1)

Figure 9 - SPI Multi Byte Read

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 16
VERSION 0.3.2

ES9290 Product Datasheet

SPI Slave Interface Timing

Figure 10 - SPI Slave Interface Timing

Min Max
Parameter Symbol
[ns] [ns]
CS Lead Time (SCLK rising edge) tLEAD 4 -
CS Trail Time (SCLK falling edge) tTRAIL 4 -
MOSI Data Setup Time tSETUP_MOSI -36 -
MOSI Data Hold Time tHOLD_MOSI 60 -
SCLK-MISO Delay Time tDELAY_MISO - 74
SCLK Period tP_SCLK 122 -
SCLK High Pulse Duration tH_SCLK 94 -
SCLK Low Pulse Duration tL_SCLK 60 -
Sequential Transfer Delay tDSEQ 38 -
Table 6 - SPI Slave Interface Timing

17 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Hardware Mode
The ES9290 has pre-configured modes that can be set with external pin configuration. These modes configure the CODEC
for different input/output serial data rates and set the muting. Hardware modes also support stereo digital PDM microphones
as inputs. Each hardware mode pin has 4 states that can be found in Design Information.
These modes are set with pins:
• MODE (Pin 18)
• HW0 (Pin 35)
• HW1 (Pin 34)
• HW2 (Pin 33)
• HW3 (Pin 31)
Input Select
The ES9290 supports an analog input signal and a digital input from a PDM microphone. In all Hardware Modes, HW3 (Pin
31) sets the input mode between the analog PGA or digital PDM Decoder.

Pin State Input Conditions

0 Daisy Chain
Analog - ADC
Pull 0 Parallel
HW3/GPIO4
Pull 1 -
Digital - PDM
1 -
Table 7 - Input Mode Selection with HW3 in Hardware Mode
Mute Control
Set MUTE_MCLK_CTRL (Pin 32) to mute the output while in Hardware Mode:

MUTE_MCLK_CTRL (Pin 32) Mute Condition MCLK

0 Mute 24.576MHz
1 Unmute 24.576MHz
Pull 0 Mute 49.152MHz
Pull 1 Unmute 49.152MHz
Table 8 - Mute Control in Hardware Mode
Note: If MUTE_MCLK_CTRL (Pin 32) is set incorrectly, it may seem that the ADC or DAC has higher noise than specified.
Note: If using the APLL as the MCLK source, MUTE_MCLK_CTRL must be set to 0 or 1.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 18
VERSION 0.3.2

ES9290 Product Datasheet

GPIO Functions in Hardware Mode

The ES9290 supports specific functions through the GPIO pins in hardware modes. The tables below show the available
controls in hardware modes. These include PGA gain, Mic Bias enable, and choosing between PDM or analog input for the
ADC. These functions are supported in hardware modes.

HW3 State Supported HW Modes GPIO # Input/Output HW Mode Function

GPIO1 - High Z
0 0 - 15
GPIO2 - High Z
GPIO1 Output DAC_TSD
0 16 - 31
GPIO2 Input ADC_RSD
GPIO1
Pull 0 All Input PGA Gain & Mic Bias
GPIO2
Table 9 - Analog ADC GPIO Functions in Hardware Mode

HW3 State Supported HW Modes GPIO # Input/Output HW Mode Function

GPIO1 Input PDM_DATA
Pull 1 / 1 All
GPIO2 Output PDM_CLK
Table 10 - Digital PDM GPIO Functions in Hardware Mode

[GPIO2, GPIO1] PGA Gain Mic Bias GPIO3 ADC DC Block

2’b00 +0dB Disabled 1’b0 Disabled
1’b1 Enabled
2’b01 +18dB Enabled (2.85V)
Table 12 - ADC DC Block in Hardware Mode
2’b10 +24dB Enabled (2.85V)
2’b11 +30dB Enabled (2.85V)
Table 11 - PGA Gain and Mic Bias in Hardware Mode

19 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Hardware Mode Pin Configuration

HW
Description FS [kHz] BCK [MHz] MODE HW2 HW1 HW0
Mode
32-bit PCM Master Modes (Ext MCLK)
0 I2S with Ext MCLK MCLK/128 MCLK/2 (64*FS) Pull 0 0 0 0
1 I2S with Ext MCLK MCLK/256 MCLK/4 (64*FS) Pull 0 0 0 1
2 I2S with Ext MCLK MCLK/512 MCLK/8 (64*FS) Pull 0 0 1 0
3 I2S with Ext MCLK MCLK/1024 MCLK/16 (64*FS) Pull 0 0 1 1
4 LJ with Ext MCLK MCLK/128 MCLK/2 (64*FS) Pull 0 Pull 0 0 0
5 LJ with Ext MCLK MCLK/256 MCLK/4 (64*FS) Pull 0 Pull 0 0 1
6 LJ with Ext MCLK MCLK/512 MCLK/8 (64*FS) Pull 0 Pull 0 1 0
7 LJ with Ext MCLK MCLK/1024 MCLK/16 (64*FS) Pull 0 Pull 0 1 1
32-bit PCM Slave Modes (PLL or Ext MCLK)
8 I S with Ext MCLK, Auto FS
2 8 ≤ FS ≤ 384 64*FS Pull 0 Pull 1 0 0
9 I2S with PLL from BCK 48 3.072 Pull 0 Pull 1 0 1
10 I S with PLL from BCK
2 96 6.144 Pull 0 Pull 1 1 0
11 I2S with PLL from BCK 192 12.288 Pull 0 Pull 1 1 1
12 LJ with Ext MCLK 8 ≤ FS ≤ 384 64*FS Pull 0 1 0 0
13 LJ with PLL from BCK 48 3.072 Pull 0 1 0 1
14 LJ with PLL from BCK 96 6.144 Pull 0 1 1 0
15 LJ with PLL from BCK 192 12.288 Pull 0 1 1 1
32-bit TDM LJ Slave Modes, Autodetect FS & CH Num
Auto (64FS, 128FS, 256FS,
16 TDM LJ Channel Slots = 1,2 8 ≤ FS ≤ 384 Pull 1 0 0 0
512FS, 1024FS)
Auto (128FS, 256FS, 512FS,
17 TDM LJ Channel Slots = 3,4 8 ≤ FS ≤ 384 Pull 1 0 0 1
1024FS)
18 TDM LJ Channel Slots = 5,6 8 ≤ FS ≤ 192 Auto (256FS, 512FS, 1024FS) Pull 1 0 1 0
19 TDM LJ Channel Slots = 7,8 8 ≤ FS ≤ 192 Auto (256FS, 512FS, 1024FS) Pull 1 0 1 1
20 TDM LJ Channel Slots = 9,10 8 ≤ FS ≤ 96 Auto (512FS, 1024FS) Pull 1 Pull 0 0 0
21 TDM LJ Channel Slots = 11,12 8 ≤ FS ≤ 96 Auto (512FS, 1024FS) Pull 1 Pull 0 0 1
22 TDM LJ Channel Slots = 13,14 8 ≤ FS ≤ 96 Auto (512FS, 1024FS) Pull 1 Pull 0 1 0
23 TDM LJ Channel Slots = 15,16 8 ≤ FS ≤ 96 Auto (512FS, 1024FS) Pull 1 Pull 0 1 1
16-bit TDM LJ Slave Modes, Autodetect FS & CH Num
Auto (32FS, 64FS, 128FS,
24 TDM LJ Channel Slots = 1,2 8 ≤ FS ≤ 384 Pull 1 Pull 1 0 0
256FS, 512FS)
Auto (64FS, 128FS, 256FS,
25 TDM LJ Channel Slots = 3,4 8 ≤ FS ≤ 384 Pull 1 Pull 1 0 1
512FS)
26 TDM LJ Channel Slots = 5,6 8 ≤ FS ≤ 192 Auto (128FS, 256FS, 512FS) Pull 1 Pull 1 1 0
27 TDM LJ Channel Slots = 7,8 8 ≤ FS ≤ 192 Auto (128FS, 256FS, 512FS) Pull 1 Pull 1 1 1
28 TDM LJ Channel Slots = 9,10 8 ≤ FS ≤ 96 Auto (256FS, 512FS) Pull 1 1 0 0
29 TDM LJ Channel Slots = 11,12 8 ≤ FS ≤ 96 Auto (256FS, 512FS) Pull 1 1 0 1
30 TDM LJ Channel Slots = 13,14 8 ≤ FS ≤ 96 Auto (256FS, 512FS) Pull 1 1 1 0
31 TDM LJ Channel Slots = 15,16 8 ≤ FS ≤ 96 Auto (256FS, 512FS) Pull 1 1 1 1
Table 13 - Hardware Mode Pin Configurations

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 20
VERSION 0.3.2

ES9290 Product Datasheet

Recommended Hardware Mode Setup Sequence

The Hardware Mode setup sequence is shown below with all hardware pins being defined after CHIP_EN is asserted.
Note: It is recommended that MUTE_MCLK_CTRL is set low until the HW mode is finalized and after CHIP_EN is asserted,
then asserted last.

CHIP_EN
HW0
HW1
HW2
HW3
MUTE_MCLK_CTRL
1m s

OUT

Figure 11 - Hardware Mode Startup Sequence

21 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Digital Features
The ES9290 CODEC features an ADC Digital Signal Path and a DAC Digital Signal Path that can pass audio through both
paths alongside monitoring the signal with Direct Monitoring.

Direct Monitoring w/ Mixing

DSP

Analog Monitor Out

Analog IN ADC + DAC (Direct Path)
Low Latency Path

Figure 12 - Direct Monitoring Path

ADC Digital Signal Path

Peak
Analog Audio Input Detector
8x FIR
PGA &
PCM/
ADC ADC ADC ADC Digital
4x FIR 2x FIR DBQ TDM
DC Mixing Volume Gain Audio Out
Encoder
Blocking
PDM Bypass Bypass
Decoder
Monitor Monitor Audio to DAC
PDM_DATA Volume Gain Digital Signal Path
PDM_CLK Programmable ADC Filter Coefficients

Selectable ROM Filter Coefficients

Figure 13 - ADC Digital Signal Path

PDM Decoder
The ES9290 can receive input audio from a PDM microphone using the integrated PDM decoder. To use the PDM signal in
software mode, PDM_INPUT_SEL must be set. PDM is also supported in hardware modes. The PDM_DATA in input into
GPIO1 and PDM_CLK is output through GPIO2.
Note: If Daisy Chain mode is enabled, PDM_DATA and PDM_CLK use GPIO3/4.
PDM Decoder Registers
• Register 66[4] PDM_PHASE
• Register 66[5] PDM_SAMPLE_EDGE
• Register 66[7] PDM_INPUT_SEL
• Register 67[6:0] MCLK_PDM_DIV
Daisy Chain Mode PDM_DATA PDM_CLK
Off GPIO1 GPIO2
On GPIO3 GPIO4
Table 14 - PDM Decoder Pins

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 22
VERSION 0.3.2

ES9290 Product Datasheet

DC Blocking
The integrated DC Blocking filter exhibits a high cutoff frequency (-3dB @ 0.25Hz).
DC Blocking Registers
• Register 65[6] CH1_DC_BLOCK_EN
• Register 65[6] CH2_DC_BLOCK_EN
Peak Detector
If the peak level of the ES9290 input rises above the programmed PEAK_THRESH_CHx value, the corresponding peak flag
will be set. The level will decay at a rate based off the value of PEAK_DECAY_RATE. The peak detection can be toggled on
or off using the PEAK_DETECT_CHx_EN registers. The peak can be read from the PEAK CHx READ registers and a flag
will be set on the PEAK_FLAG_CHx registers. Normal flag registers will unset the flag once it is no longer asserted except
the PEAK_FLAG_LAT_CHx registers which will stay set until it is cleared with INT_CLEAR_CHx_PEAK_LATCH.
GPIO pins can be configured to output the state of any peak flags or latched peak flags if
STATUS_MASK_CHx_PEAK_DET or STATUS_MASK_CHx_PEAK_LATCH is set for the corresponding channel.
Peak Enable Registers
• Register 88[1:0] PEAK_DETECT_CHx_EN
Peak Flag GPIO Registers
• Register 18[1:0] STATUS_MASK_CHx_PEAK_LATCH
• Register 18[3:2] STATUS_MASK_CHx_PEAK_DET
Peak Flag and Read Registers
• Register 238-239 PEAK CH1 READ
• Register 240-241 PEAK CH2 READ
• Register 233[5:4] PEAK_FLAG_CHx
• Register 233[7:6] PEAK_FLAG_LAT_CHx
• Register 19[1:0] INT_CLEAR_CHx_PEAK_LATCH
Peak Decay Rate and Threshold Registers
• Register 89[4:0] PEAK_DECAY_RATE
• Register 90-91[7:0] PEAK_THRESH_CH1
• Register 90-91[15:8] PEAK_THRESH_CH2
−𝑀𝐶𝐿𝐾_24𝑀 ∗ 𝑡
𝑁(𝑡) = 𝑁0 𝑒𝑥𝑝 ( 𝑑𝑒𝑐𝑎𝑦_𝑟𝑎𝑡𝑒+9 )
2
20 ∗ 𝑀𝐶𝐿𝐾_24𝑀 ∗ 𝑡
𝑁(𝑡) = 𝑁0 − [𝑑𝐵]
𝑙𝑛(10) ∗ 2𝑑𝑒𝑐𝑎𝑦_𝑟𝑎𝑡𝑒+9
𝑑𝑁 𝑁 ∗ 𝑀𝐶𝐿𝐾_24𝑀
= − 𝑑𝑒𝑐𝑎𝑦_𝑟𝑎𝑡𝑒+9 [1/𝑠]
𝑑𝑡 2

23 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

ADC 8x FIR Filter

Selection of the 8x interpolation filter is chosen from 8 pre-programmed filter shapes. For more information on filters see the
ADC: PCM Filter Latency section.
FIR Registers
• Register 64[7:5] ADC_FILTER_SHAPE
ADC Digital Biquad Filter
The ES9290 features a Digital Full Biquad (DBQ) filter for the ADC datapath. The filter comes with 23 preset filters and the
ability to make a custom filter via user input coefficients.
The custom filter uses 5 coefficients to shape the filter: -A2, -A1, B2, B1, and B0.
The coefficients are signed 24-bit numbers.
ADC DBQ Filter Registers
• Register 48[4:0] ADC_DBQ_COEFF_SEL (preset filter selection)
• Register 48[7] ADC_DBQ_CLK_FAMILY_SEL
• Register 48[6] ADC_DBQ_80HZ_HPF_EN
• Register 48[5] ADC_DBQ_120HZ_HPF_EN
• Register 49-51 ADC PROG DBQ A2 COEFF
o Note: Assigns -A2 to the register
• Register 52-54 ADC PROG DBQ A1 COEFF
o Note: Assigns -A1 to the register
• Register 55-57 ADC PROG DBQ B2 COEFF
• Register 58-60 ADC PROG DBQ B1 COEFF
• Register 61-63 ADC PROG DBQ B0 COEFF
The DBQ is arranged in a transposed direct form 2 format.

X(z) b0 Y(z)

z-1

b1 -a1

z-1

b2 -a2

Figure 14 - ADC DBQ format

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VERSION 0.3.2

ES9290 Product Datasheet

ADC Mixing
The ES9290 has the ability to mix the incoming ADC_CH1 data into ADC_CH2 and vice versa. The range of mixing is -∞dB
(8’hFF) to 0dB (8’h00).

CH1 IN CH1 MIX

CH1 Into CH2
CH2 Into CH1

CH2 IN CH2 MIX

Figure 15 - ADC Mixing

ADC Mixing Registers
• Register 70 ADC MIX VOLUME CH1
• Register 71 ADC MIX VOLUME CH2
ADC Volume
The ADC Volume Control is intended for use during audio playback. Each channel can be digitally attenuated from +1dB to
-126dB in 0.5dB steps. When a new volume level is set, the attenuation circuit will ramp softly to the new level at a rate
specified in the VOLUME UP RAMP RATE and VOLUME DOWN RAMP RATE registers.
ADC Volume Registers
• Register 68 ADC VOLUME CH1
• Register 69 ADC VOLUME CH2
• Register 14 VOLUME UP RAMP RATE
• Register 15 VOLUME DOWN RAMP RATE
ADC Gain
The ES9290 has an additional digital gain that can be added through registers. Settings for +0dB to +42dB in +6dB steps
are available.
ADC Gain Registers
• Register 72[6:4] ADC_DIGITAL_GAIN_CH2
• Register 72[2:0] ADC_DIGITAL_GAIN_CH1
Direct Monitor Volume
The signal from the ADC digital path can be passed into the DAC digital path using the Direct Monitor. The Direct Monitor
Volume Control is intended for use during audio playback. Each channel can be digitally attenuated from +1dB to
-126dB in 0.5dB steps. When a new volume level is set, the attenuation circuit will ramp softly to the new level at a rate
specified in the VOLUME UP RAMP RATE and VOLUME DOWN RAMP RATE registers.
Monitor Volume Registers
• Register 127 DIRECT MONITOR VOLUME CH1
• Register 128 DIRECT MONITOR VOLUME CH2
Note: This is the same Monitor Volume block as seen in the DAC Digital Signal Path.
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VERSION 0.3.2

ES9290 Product Datasheet

Direct Monitor Gain

The Direct Monitor uses the same gain settings as the ADC Gain does.
Monitor Gain Registers
• Register 72[6:4] ADC_DIGITAL_GAIN_CH2
• Register 72[2:0] ADC_DIGITAL_GAIN_CH1
Note: This is the same Monitor Gain block as seen in the DAC Digital Signal Path.
PCM/TDM Encoder
The ES9290 integrates a PCM/TDM Encoder that can be mixed with the monitor’s output. The PCM/TDM Encoder input has
a maximum word width of 32-bits (default) and a maximum bit depth of 32-bit (default). The encoder allows for I2S, LJ, and
TDM output streams.
The PCM/TDM Encoder can support up to 32 different slots and each channel of the DAC can be mapped to any of the 32
slots.
Note: The PCM/TDM Encoder and PCM/TDM Decoder use all the same registers settings and will run with the exact same
formatting.
PCM/TDM Encoder Registers
• Register 5[7] TDM_RESYNC
• Register 5[6] AUTO_CH_DETECT
• Register 5[4:0] TDM_CH_NUM
• Register 6[7] ENABLE_WS_MONITOR
• Register 6[6] ENABLE_BCK_MONITOR
• Register 6[5:4] TDM_WORD_WIDTH
• Register 6[3:2] TDM_BIT_DEPTH
• Register 6[1] TDM_VALID_EDGE
• Register 6[0] TDM_LJ
TDM Mapping Registers
• Register 7[4:0] ADC_TDM_SLOT_SEL_CH1
• Register 8[4:0] ADC_TDM_SLOT_SEL_CH2
Daisy Chain Registers
• Register 11[5] ADC_TDM_DAISY_CHAIN
• Register 11[4:0] ADC_TDM_DATA_LATCH_ADJ

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VERSION 0.3.2

ES9290 Product Datasheet

DAC Digital Signal Path

Audio from ADC Monitor Monitor

Digital Signal Path Volume Gain

8x FIR
Digital Audio In PCM/
DAC DAC DAC 2x FIR 4x FIR Hyperstream® To Data
TDM DBQ IIR
Mixing Volume Gain IV Arch. Conversion
Decoder
Programmable DAC Bypass Bypass Bypass
Filter Coefficients Automute

Selectable ROM
Filter Coefficients

PCM/TDM Decoder
The ES9290 integrates a PCM/TDM Decoder that can be mixed with the monitor’s output. The PCM/TDM decoder input has
a maximum word width of 32-bits (default) and a maximum bit depth of 32-bit (default). The decoder allows for I2S, LJ, RJ
and TDM input streams.
The PCM/TDM decoder can support up to 32 different slots and each channel of the DAC can be mapped to any of the 32
slots.
Note: The PCM/TDM Encoder and PCM/TDM Decoder use all the same registers settings and will run in the exact same
format.
PCM/TDM Decoder Registers
• Register 5[7] TDM_RESYNC
• Register 5[6] AUTO_CH_DETECT
• Register 5[4:0] TDM_CH_NUM
• Register 6[7] ENABLE_WS_MONITOR
• Register 6[6] ENABLE_BCK_MONITOR
• Register 6[5:4] TDM_WORD_WIDTH
• Register 6[3:2] TDM_BIT_DEPTH
• Register 6[1] TDM_VALID_EDGE
• Register 6[0] TDM_LJ
TDM Mapping Registers
• Register 9[4:0] DAC_TDM_SLOT_SEL_CH1
• Register 10[4:0] DAC_TDM_SLOT_SEL_CH2
Daisy Chain Registers
• Register 12[5] DAC_TDM_DAISY_CHAIN
• Register 12[4:0] DAC_TDM_DATA_LATCH_ADJ

27 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

DAC Digital Biquad Filter

The ES9290 features a Digital Full Biquad (DBQ) filter for the DAC datapath. The filter comes with 23 preset filters and the
ability to make a custom filter via user input coefficients.
The custom filter uses 5 coefficients to shape the filter: -A2, -A1, B2, B1, and B0.
The coefficients are signed 24-bit numbers.
DAC DBQ Filter Registers
• Register 102[4:0] DAC_DBQ_COEFF_SEL (preset filter selection)
• Register 103-105 DAC PROG DBQ A2 COEFF
o Note: Assigns -A2 to the register
• Register 106-108 DAC PROG DBQ A1 COEFF
o Note: Assigns -A1 to the register
• Register 109-111 DAC PROG DBQ B2 COEFF
• Register 112-114 DAC PROG DBQ B1 COEFF
• Register 115-117 DAC PROG DBQ B0 COEFF
The DBQ is arranged in a transposed direct form 2 format.

X(z) b0 Y(z)

z-1

b1 -a1

z-1

b2 -a2

Figure 16 - DAC DBQ format

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VERSION 0.3.2

ES9290 Product Datasheet

DAC Mixing
The ES9290 has the ability to mix the incoming TDM Decoder audio data DAC_CH1 data into DAC_CH2 and vice versa.
The range of mixing is -∞dB (8’hFF) to 0dB (8’h00).

CH1 IN CH1 MIX

CH1 Into CH2
CH2 Into CH1

CH2 IN CH2 MIX

Figure 17 - DAC Mixing

DAC Mixing Registers
• Register 125 DAC MIX VOLUME CH1
• Register 126 DAC MIX VOLUME CH2
DAC Automute
The DAC in the ES9290 features an automute that triggers when the signal is below the specified level for longer than the
specified time. The automute will disengage when the signal is above the specified off value for the same amount of time.
Note: Automute will not engage if the ADC monitor is running.
225
𝑇𝑖𝑚𝑒[𝑠] =
𝐴𝑈𝑇𝑂𝑀𝑈𝑇𝐸_𝑇𝐼𝑀𝐸 ∗ 𝑀𝐶𝐿𝐾_128𝐹𝑆 ∗ 264𝐹𝑆_𝑀𝑂𝐷𝐸
20 ∗ 𝑙𝑜𝑔10 (𝐴𝑈𝑇𝑂𝑀𝑈𝑇𝐸_𝐿𝐸𝑉𝐸𝐿)
𝐿𝑒𝑣𝑒𝑙[𝑑𝐵] =
(216 − 1) ∗ 27
DAC Automute Registers
• Register 139[1:0] AUTOMUTE_EN_CHx
• Register 140-141[10:0] AUTOMUTE_TIME
• Register 142-143 AUTOMUTE_LEVEL
• Register 144-145 AUTOMUTE_OFF_LEVEL
DAC Volume
The DAC Volume Control is intended for use during audio playback. Each channel can be digitally attenuated from -126dB
to +1dB in +0.5dB steps. When a new volume level is set, the attenuation circuit will ramp softly to the new level at a rate
specified in the VOLUME UP RAMP RATE and VOLUME DOWN RAMP RATE registers.
DAC Volume Registers
• Register 123 DAC VOLUME CH1
• Register 124 DAC VOLUME CH2
• Register 14 VOLUME UP RAMP RATE
• Register 15 VOLUME DOWN RAMP RATE

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VERSION 0.3.2

ES9290 Product Datasheet

DAC Gain
The ES9290 has an additional digital gain that can be added through registers. Settings for +0dB to +42dB in 6dB steps are
available.
DAC Gain Registers
• Register 135[6:4] DAC_DIGITAL_GAIN_CH2
• Register 135[2:0] DAC_DIGITAL_GAIN_CH1
Direct Monitor Volume
The signal from the ADC digital path can be passed into the DAC digital path using the Direct Monitor. The Direct Monitor
Volume Control is intended for use during audio playback. Each channel can be digitally attenuated from +1dB to
-126dB in 0.5dB steps. When a new volume level is set, the attenuation circuit will ramp softly to the new level at a rate
specified in the VOLUME UP RAMP RATE and VOLUME DOWN RAMP RATE registers.
Monitor Volume Registers
• Register 127 DIRECT MONITOR VOLUME CH1
• Register 128 DIRECT MONITOR VOLUME CH2
Note: This is the same Monitor Volume block as seen in the ADC Digital Signal Path.
Direct Monitor Gain
The Direct Monitor uses the same gain settings as the ADC Gain does.
Monitor Gain Registers
• Register 72[6:4] ADC_DIGITAL_GAIN_CH2
• Register 72[2:0] ADC_DIGITAL_GAIN_CH1
Note: This is the same Monitor Gain block as seen in the ADC Digital Signal Path.
DAC 8x FIR Filter
Selection of the 8x interpolation filter is chosen from 8 pre-programmed filters. The 2x and 4x filter can be bypassed
individually or together. For more information on filters see the DAC: PCM Filter Latency section.
DAC FIR Registers
• Register 118[2:0] DAC_FILTER_SHAPE
• Register 118[3] BYPASS_FIR2X
• Register 118[4] BYPASS_FIR4X
DAC IIR Filter
The IIR filter can be bypassed using Register 118[5] BYPASS_IIR

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VERSION 0.3.2

ES9290 Product Datasheet

Pre-Programmed FIR Filters

The ES9290 has 8 pre-programmed digital filters. The latency for each filter reduces (scales) with increasing sample rates.
(See Register 64[7:5] ADC_FILTER_SHAPE and Register 118[2:0] DAC_FILTER_SHAPE for configuration)

# Filter Description
Version 2 of minimum phase fast roll-off (#5) with less ripple and more image
0 Minimum Phase (default)
rejection
Linear Phase Apodizing Fast Full image rejection by FS/2 to avoid any aliasing, with smooth roll-off
1
Roll-Off starting before 20k.
2 Linear Phase Fast Roll-Off Sabre legacy filter, optimized for image rejection @ 0.55FS
Linear Phase Fast Roll-Off
3 Sabre legacy filter, optimized for in-band ripple
Low-Ripple
Sabre legacy filter, optimized for lower latency, but symmetric impulse
4 Linear Phase Slow Roll-Off
response
Low latency, minimal pre ringing and low passband ripple, image rejection @
5 Minimum Phase Fast Roll-Off
0.55FS
6 Minimum Phase Slow Roll-Off Lowest latency at the cost of image rejection
Provides a nice balance of the low latency of minimum phase filters and the
Minimum Phase Fast Roll-Off
7 low dispersion of linear phase filters. Minimal pre-ringing is added to
Low Dispersion
achieve the low dispersion in the audio band.
Table 15 - Pre-Programmed Digital Filter Descriptions
Note: Minimum Phase filters are asymmetric filters that work to minimize the pre-echo of the filter, while still maintaining an
excellent frequency response and they peak earlier than linear phase filters, resulting in a lower group delay. Minimum
phase filters usually feature zero cycles of pre-echo, which can result in improved audio quality.

31 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

ADC: PCM Filter Latency

The following table shows the simulated latency of each filter at 44.1kHz sampling rate. Measurements were taken from the
external impulse response prior to being down sampled to 1FS. The extra sample delay to get the data encoded accounts
for external processing time to serialize the data stream. Latency delay will reduce (scale) with sampling rate.

Digital Filter Delay

Minimum Phase (default) 7.25 / FS

Linear Phase Apodizing Fast Roll-Off 37.13 / FS

Linear Phase Fast Roll-Off 37.25 / FS

Linear Phase Fast Roll-Off Low-Ripple 36.88 / FS

Linear Phase Slow Roll-Off 9.88 / FS

Minimum Phase Fast Roll-Off 7.38 / FS

Minimum Phase Slow Roll-Off 6.25 / FS

Minimum Phase Fast Roll-Off Low Dispersion 16.13 / FS

Table 16 - ADC PCM Filter Latency

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VERSION 0.3.2

ES9290 Product Datasheet

ADC: PCM Filter Properties

Minimum Phase
Parameter Conditions MIN TYP MAX UNIT
Pass band 0.46 FS Hz
Stop band -88 dB 0.54 FS Hz
Group Delay 2.90/FS 9.23/FS s
Flatness (ripple) 0.0042 dB

Linear Phase Apodizing

Parameter Conditions MIN TYP MAX UNIT
Pass band 0.41 FS Hz
Stop band -81.91 dB 0.50 FS Hz
Group Delay 33.25/FS s
Flatness (ripple) 0.0043 dB

Linear Phase Fast Roll-Off

Parameter Conditions MIN TYP MAX UNIT
Pass band 0.46 FS Hz
Stop band -77.88 dB 0.54 FS Hz
Group Delay 33.38/FS s
Flatness (ripple) 0.0043 dB

Linear Phase Fast Roll-Off Low Ripple

Parameter Conditions MIN TYP MAX UNIT
Pass band 0.46 FS Hz
Stop band -77.46 dB 0.55 FS Hz
Group Delay 33.00/FS s
Flatness (ripple) 0.0040 dB

Linear Phase Slow Roll-Off

Parameter Conditions MIN TYP MAX UNIT
Pass band -3 dB 0.46 FS Hz
Stop band -84.63 dB 0.75 FS Hz
Group Delay 6.05/FS s
Flatness (ripple) dB

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VERSION 0.3.2

ES9290 Product Datasheet

Minimum Phase Fast Roll-Off

Parameter Conditions MIN TYP MAX UNIT
Pass band 0.46 FS Hz
Stop band -88.26 dB 0.54 FS Hz
Group Delay 2.95/FS 9.42/FS s
Flatness (ripple) 0.0054 dB

Minimum Phase Slow Roll-Off

Parameter Conditions MIN TYP MAX UNIT
Pass band -3 dB 0.43 FS Hz
Stop band -90.02 dB 0.80 FS Hz
Group Delay 2.03/FS 3.51/FS s
Flatness (ripple) dB

Minimum Phase Slow Roll-Off Low Dispersion

Parameter Conditions MIN TYP MAX UNIT
Pass band -3 dB 0.43 FS Hz
Stop band -90.02 dB 0.80 FS Hz
Group Delay 12.16/FS 12.43/FS s
Flatness (ripple) dB
Table 17 - ADC PCM Filter Properties

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VERSION 0.3.2

ES9290 Product Datasheet

ADC: PCM Filter Frequency Response

The following frequency responses were obtained from software simulations of these filters. Simulation sample rate is
44.1kHz.
Filter Frequency Response

Minimum Phase

Linear Phase Apodizing

Minimum Phase Slow Roll-

Off Low Dispersion

Table 18 - ADC PCM Filter Frequency Response

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VERSION 0.3.2

ES9290 Product Datasheet

ADC: PCM Filter Impulse Response

The following impulse responses were obtained from software simulations of these filters. They show the decimation path
prior to down-sampling to 1FS and are scaled accordingly. The extra sample delay to get the data encoded accounts for
external processing time to serialize data stream.
Filter Impulse Response

Minimum Phase

Linear Phase Apodizing

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VERSION 0.3.2

ES9290 Product Datasheet

Linear Phase Fast Roll-Off

Low Ripple

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VERSION 0.3.2

ES9290 Product Datasheet

Linear Phase Slow Roll-Off

Minimum Phase Fast Roll-

Off

41 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Minimum Phase Slow Roll-

Off

Minimum Phase Slow Roll-

Off Low Dispersion

Table 19 - ADC PCM Filter Impulse Response

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VERSION 0.3.2

ES9290 Product Datasheet

ADC: 64FS Mode

ADC: Minimum Phase 64FS Mode Latency
The following table shows the simulated latency at 705.6kHz sampling rate and is very similar at 768kHz. Measurements
were taken from the external impulse response prior to being down sampled to 1FS. The extra sample delay to get the data
encoded accounts for external processing time to serialize the data stream. Latency delay will reduce (scale) with sampling
rate.

Digital Filter Delay

Minimum Phase Double Rate 6 / FS

Table 20 - ADC Minimum Phase 64FS Latency

ADC: Minimum Phase 64FS Properties
Minimum Phase 64FS Mode
Parameter Conditions MIN TYP MAX UNIT
Pass band -3 dB 0.44 FS Hz
Stop band -68.37 dB 0.68 FS Hz
Group Delay 1.43/FS 3.45/FS s
Flatness (ripple) dB
Table 21 - ADC Minimum Phase 64FS Properties
Note: The ADC Minimum Phase 64FS filter has an additional +0.020dB of gain.

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VERSION 0.3.2

ES9290 Product Datasheet

ADC: Minimum Phase 64FS Frequency Response

This filter gets selected automatically when MCLK/FS = 64. The following frequency response was obtained from software
simulations with a sample rate of 705.6kHz

Figure 18 - ADC Minimum Phase 64FS Frequency Response

ADC: Minimum Phase 64FS Impulse Response
The following impulse responses were obtained from software simulations of these filters. They show the decimation path
prior to down-sampling to 1FS and are scaled accordingly. The extra sample delay to get the data encoded accounts for
external processing time to serialize data stream.

Figure 19 - ADC Minimum Phase 64FS Impulse Response

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VERSION 0.3.2

ES9290 Product Datasheet

DAC: PCM Filter Latency

The following table shows the simulated latency of each filter at 44.1kHz sampling rate. Measurements were taken from the
external impulse response. The extra sample delay to get the data encoded accounts for external processing time to
serialize the data stream. Latency will reduce (scale) with sampling rate.

Digital Filter Delay

Minimum Phase (default) 5.39 / FS

Linear Phase Apodizing Fast Roll-Off 34.76 / FS

Linear Phase Fast Roll-Off 35.38 / FS

Linear Phase Fast Roll-Off Low-Ripple 33.32 / FS

Linear Phase Slow Roll-Off 7.82 / FS

Minimum Phase Fast Roll-Off 5.39 / FS

Minimum Phase Slow Roll-Off 4.42 / FS

Minimum Phase Fast Roll-Off Low Dispersion 11.35 / FS

Table 22 - DAC PCM Filter Latency

45 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

DAC: PCM Filter Properties

Minimum Phase
Parameter Conditions MIN TYP MAX UNIT
Pass band 0.46 x fs Hz
Stop band -95 dB 0.55 x fs Hz
Group Delay 2.91/fs 9.01/fs s
Flatness (ripple) 0.0012 dB

Linear Phase Apodizing

Parameter Conditions MIN TYP MAX UNIT
Pass band 0.41 x fs Hz
Stop band -108 dB 0.50 x fs Hz
Group Delay 32.81/fs s
Flatness (ripple) 0.0024 dB

Linear Phase Fast Roll-Off

Parameter Conditions MIN TYP MAX UNIT
Pass band 0.45 x fs Hz
Stop band -117 dB 0.55 x fs Hz
Group Delay 33.43/fs s
Flatness (ripple) 0.0030 dB

Linear Phase Fast Roll-Off Low Ripple

Parameter Conditions MIN TYP MAX UNIT
Pass band 0.46 x fs Hz
Stop band -88 dB 0.55 x fs Hz
Group Delay 31.37/fs s
Flatness (ripple) 0.0012 dB

Linear Phase Slow Roll-Off

Parameter Conditions MIN TYP MAX UNIT
Pass band -3 dB 0.44 x fs Hz
Stop band -90 dB 0.75 x fs Hz
Group Delay 5.87/fs s
Flatness (ripple) dB

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VERSION 0.3.2

ES9290 Product Datasheet

Minimum Phase Fast Roll-Off

Parameter Conditions MIN TYP MAX UNIT
Pass band 0.46 x fs Hz
Stop band -98 dB 0.55 x fs Hz
Group Delay 2.91/fs 9.14/fs s
Flatness (ripple) 0.0023 dB

Minimum Phase Slow Roll-Off

Parameter Conditions MIN TYP MAX UNIT
Pass band -3 dB 0.43 x fs Hz
Stop band -91 dB 0.80 x fs Hz
Group Delay 2.08/fs 3.56/fs s
Flatness (ripple) dB

Minimum Phase Slow Roll-Off Low Dispersion

Parameter Conditions MIN TYP MAX UNIT
Pass band -3 dB 0.43 x fs Hz
Stop band -91 dB 0.80 x fs Hz
Group Delay 9.23/fs 9.75/fs s
Flatness (ripple) dB
Table 23 - DAC PCM Filter Properties

47 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

DAC: PCM Filter Frequency Response

The following frequency responses were obtained from software simulations of these filters. Simulation sample rate is
44.1kHz.
Filter Frequency Response

Minimum Phase

Linear Phase Apodizing

Minimum Phase Slow Roll-

Off Low Dispersion

Table 24 - DAC PCM Filter Frequency Response

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VERSION 0.3.2

ES9290 Product Datasheet

DAC: PCM Filter Impulse Response

The following impulse responses were obtained from software simulations of these filters. They were measured from the
external impulse response. The extra sample delay to get the data encoded accounts for external processing time to
serialize data stream.
Filter Impulse Response

Minimum Phase

Linear Phase Apodizing

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VERSION 0.3.2

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Linear Phase Fast Roll-Off

Low Ripple

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Linear Phase Slow Roll-Off

Minimum Phase Fast Roll-

Off

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VERSION 0.3.2

ES9290 Product Datasheet

Minimum Phase Slow Roll-

Off

Minimum Phase Slow Roll-

Off Low Dispersion

Table 25 - DAC PCM Filter Impulse Response

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VERSION 0.3.2

ES9290 Product Datasheet

DAC: 64FS Mode

DAC: Minimum Phase 64FS Mode Latency
The following table shows the simulated latency at 705.6kHz sampling rate and is very similar at 768kHz. Measurements
were taken from the external impulse response. The extra sample delay to get the data encoded accounts for external
processing time to serialize the data stream. Latency delay will reduce (scale) with sampling rate.

Digital Filter Delay

Minimum Phase Double Rate 3.83 / FS

Table 26 - DAC Minimum Phase 64FS Latency
DAC: Minimum Phase 64FS Properties
Minimum Phase 64FS Mode
Parameter Conditions MIN TYP MAX UNIT
Pass band -3 dB 0.45 FS Hz
Stop band -61 dB 0.68 FS Hz
Group Delay 1.54 / FS 2.35 / FS s
Flatness (ripple) dB
Table 27 - DAC Minimum Phase 64FS Properties

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VERSION 0.3.2

ES9290 Product Datasheet

DAC: Minimum Phase 64FS Frequency Response

This filter gets selected automatically when MCLK/FS = 64. The following frequency response was obtained from software
simulations with a sample rate of 705.6kHz

Figure 20 - DAC Minimum Phase 64FS Frequency Response

DAC: Minimum Phase 64FS Impulse Response

Figure 21 - DAC Minimum Phase 64FS Impulse Response

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VERSION 0.3.2

ES9290 Product Datasheet

Pre-Programmed DBQ Filters

The ES9290 has 24 pre-programmed DBQ digital filters, which are second order Butterworth filters with no delay. The cutoff
frequency for each filter increases (scales) with increasing sample rates. To manually configure the filters see Register
48[4:0] ADC_DBQ_COEFF_SEL and Register 102[4:0] DAC_DBQ_COEFF_SEL.
The High-pass filters can be automatically set based on the sample rate and clock family. See Register 48[5, 6, 7]
ADC_DBQ_120HZ_HPG_EN, ADC_DBQ_80HZ_HPF_EN, ADC_DBQ_CLK_FAMILY_SEL and Register 102[5, 6, 7]
DAC_DBQ_120HZ_HPG_EN, DAC_DBQ_80HZ_HPF_EN, DAC_DBQ_CLK_FAMILY_SEL.
The DBQ programmable coefficients are arranged in a Transposed Direct Form II format. See ADC Digital Biquad Filter for
more information.

# Filter Description
1 Programmable Program desired filters into the ES9290.
2 Bypass DBQ filter is bypassed.
3 DC Blocking High-pass filter with FC = (0.001/48) * FS
4 Low-pass filter with FC = 3.512kHz, FS = 48kHz
5 De-emphasis Low-pass filter with FC = 3.522kHz, FS = 44.1kHz
6 Low-pass filter with FC = 3.519kHz, FS = 32kHZ
7 RIAA De-emphasis Standard RIAA De-emphasis filter for FS= 48kHz
8 RIAA Pre-emphasis Standard RIAA Pre-emphasis filter for FS= 48kHz
9 High-pass filter for FS = 48kHz
10 High-pass filter for FS = 96kHz
80Hz High-pass
11 High-pass filter for FS = 192kHz
12 High-pass filter for FS = 384kHz
13 High-pass filter for FS = 48kHz
14 High-pass filter for FS = 96kHz
120Hz High-pass
15 High-pass filter for FS = 192kHz
16 High-pass filter for FS = 384kHz
17 High-pass filter for FS = 44.1kHz
18 High-pass filter for FS = 88.2kHz
80Hz High-pass
19 High-pass filter for FS = 176.4kHz
20 High-pass filter for FS = 352.8kHz
21 High-pass filter for FS = 44.1kHz
22 High-pass filter for FS = 88.2kHz
120Hz High-pass
23 High-pass filter for FS = 176.4kHz
24 High-pass filter for FS = 352.8kHz
Table 28 - Pre-Programmed DBQ Digital Filter Descriptions
Note: Pre-emphasis filters attenuate lower frequency and boost higher frequencies to improve overall signal to noise ratio.
De-emphasis filters redo this process by boosting the lower frequencies and attenuating the higher frequencies. RIAA Pre/De-
emphasis filters are specific types of filters used in vinyl record playback systems. It's part of the standard established by the
Recording Industry Association of America (RIAA) for phonograph records.

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DBQ Filter Properties

DC Blocking
Parameter Conditions MIN TYP MAX UNIT
Pass band 2.1e-5 FS Hz
Stop band -32 dB 0 FS Hz

De-emphasis
Parameter Conditions MIN TYP MAX UNIT
Pass band 0.073 FS Hz
Stop band -9.625 dB 0.50 FS Hz

RIAA De-emphasis
Parameter Conditions MIN TYP MAX UNIT
Pass band 0.001 FS Hz
Stop band -40 dB 0.50 FS Hz

RIAA Pre-emphasis
Parameter Conditions MIN TYP MAX UNIT
Pass band 0.031 FS Hz
Stop band -40 dB 0 FS Hz

80 Hz High-pass filter (9-12) (17-20)

Parameter Conditions MIN TYP MAX UNIT
Pass band 80 Hz
Stop band -140 dB 0 FS Hz

120 Hz High-pass filters (13-16) (21-24)

120Hz High-pass filter

(13-16)(21-24)

Table 30 - DBQ Filter Frequency Response

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VERSION 0.3.2

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DBQ Filter Impulse Response

DC Blocking

De-emphasis

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RIAA De-emphasis

RIAA Pre-emphasis

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VERSION 0.3.2

ES9290 Product Datasheet

80Hz High-pass filter

(9-12) (17-20)

120Hz High-pass filter

(13-16)(21-24)

Table 31 - DBQ Filter Impulse Response

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VERSION 0.3.2

ES9290 Product Datasheet

Daisy Chain
The ES9290 supports connecting multiple devices together in a daisy chain configuration. Up to 16 devices can be daisy
chained together to output data onto any of the 32 channels in a TDM data line. The digital input to Chip#1 through DATA3
is output through GPIO1 for the Chip#2 down the chain. At the same time, the digital output from Chip #2’s DATA2 is
inputted through GPIO2 of Chip #1 to append to its DATA2 digital output. See Application Note for more information.
Note: GPIO2 on the last ES9290 of the Daisy Chain must be set to zero by pulling to ground through a 47Ω resistor.
Note: While operating in 32 or 24bit word widths, TDM must be configured into I2S mode.

Data Path Output Pin Input Pin

DAC GPIO1 DATA3
ADC DATA2 GPIO2
Table 32 - Daisy Chain Pins

Figure 22 - Daisy Chain Configuration

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VERSION 0.3.2

ES9290 Product Datasheet

Sample Rate Calculation

Acquiring the real time sample rate from the ES9290 can be accomplished using Register 230 AUTO FS READ.
Auto fs detect (Register 0[3] AUTO_FS_DETECT = 1’b1) must be set.
The below equation calculates the current auto detected sample rate by using a combination of register readback states.
𝑌 ∗ 𝑀𝐶𝐿𝐾
𝐹𝑆 [𝐻𝑧] =
128
(𝑋 + 1) ∗ ( 𝑍 )
2
Variables
• {X}: Register 230[5:0] MCLK_128FS_DIV_AUTO
• {Y}: Register 230[6] MCLK_128FS_HALF_DIV_AUTO
o 1’b0: Y=1
o 1’b1: Y=2
• {Z}: Register 230[7] EN_64FS_MODE_AUTO
• MCLK: Master Clock rate
Example
For this example, let the variables be as follows:
X = 7, Y = 1, Z = 0, MCLK = 49.152 [MHz]
1 ∗ 49.152𝑀𝐻𝑧 49.152𝑀𝐻𝑧
𝐹𝑆 [𝐻𝑧] = = = 48𝑘𝐻𝑧
128 8 ∗ 128
(7 + 1) ∗ ( 0 )
2

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VERSION 0.3.2

ES9290 Product Datasheet

Audio Input and Output Formats

The ES9290 supports PCM or TDM serial input/output data formats along with PDM inputs.
Note: See PDM Decoder for more information on using PDM as an input source.
PCM (I2S, LJ)
PCM includes I2S and LJ with 2 channels/slots per data line. The ADC outputs can be mapped to any slot/channel of the
PCM encoder output data (DATA2) using ADC_TDM_SLOT_SEL_CHx. The PCM decoder routes any slot/channel of the
PCM input data (DATA3) to the DACs using DAC_TDM_SLOT_SEL_CHx.
Data is latched on the positive edge of BCLK.

Pin Name Function Description

DATA_CLK PCM BCLK PCM Clock (Bit Clock), Master or Slave
DATA1 PCM WS PCM WS (Word Select/Frame Select), Master or Slave
DATA2 PCM Output Data PCM Data Output from ADC
DATA3 PCM Input Data PCM Data Input for DAC
Table 33 - PCM Pin Connections
Note: The PCM Decoder supports Right Justified (RJ) format in software mode for a single device.

Figure 23 - LJ (top) & I2S (bottom) for 32, 24, and 16-bit Word Widths

DAC Minimum Volume Flag

Outputs HIGH when the DAC is muted. This can occur from manually muting, automuting, and setting volume to 0xFF.
Relevant Registers
• Register 44[0] GPIO_AND_VOL_MIN sets the output to be the logical AND of both channels’ mute flags.
• Register 44[3] GPIO_OR_VOL_MIN sets the output to be the logical OR of both channels’ mute flags.
• Register 44[6] FLAG_CH_SEL selects which of the individual DAC channel flags to output.
DAC Automute Status
Outputs HIGH when the DACs automute condition is met.
Relevant Registers
• Register 44[1] GPIO_AND_AUTOMUTE sets the output to be the logical AND of both channels’ automute flags.
• Register 44[4] GPIO_OR_AUTOMUTE sets the output to be the logical OR of both channels’ automute flags.
• Register 44[6] FLAG_CH_SEL selects which of the DAC channel flags to output.
DAC Soft Ramp Done Flag
Outputs HIGH when the DAC is neither ramping up nor down.
Relevant Registers
• Register 44[2] GPIO_AND_SS_RAMP sets the output to be the logical AND of both channels’ automute flags.
• Register 44[5] GPIO_OR_SS_RAMP sets the output to be the logical OR of both channels’ automute flags.
• Register 44[6] FLAG_CH_SEL selects which of the DAC channel flags to output.
ADC CHx Peak Flag
Outputs the latched peak detector flags. Flags will become HIGH when then channels peak has gone above the peak
threshold and will stay high until cleared.
Relevant Registers
• Register 90-91 PEAK_THRESH_CHx sets the peak threshold.
• Register 88[1:0] PEAK_DETECT_CHx_EN is required to be set for the peak detector logic to function.
• Register 18[1:0] STATUS_MASK_CHx_PEAK_LATCH is required to be set for the GPIO output to be active.
• Register 19[1:0] STATUS_CLEAR_CHx_PEAK_LATCH must be toggled HIGH-LOW for the latched flag to clear.

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VERSION 0.3.2

ES9290 Product Datasheet

PWM Signal
Outputs a configurable PWM signal. The frequency and duty cycle of the PWM signal can be calculated with the following
equations:
𝑀𝐶𝐿𝐾
𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 [𝐻𝑧] =
𝑃𝑊𝑀_𝐹𝑅𝐸𝑄 + 1
𝑃𝑊𝑀_𝐶𝑂𝑈𝑁𝑇
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 [%] = ( ) × 100
𝑃𝑊𝑀_𝐹𝑅𝐸𝑄 + 1
Relevant Registers
• Register 45 PWM_COUNT
• Register 46-47 PWM_FREQ
OR of all Status Bits
Outputs the logical OR of all the status flags. This includes the PLL Locked Flag, ADC CHx Peak Flag, and ADC CHx Peak
Latch Flag.
BCK/WS Monitor
Outputs the status of the BCK and WS monitors. HIGH if either monitor detects an invalid signal.
BCK is considered invalid if the ratio MCLK/BCK > 1024.
WS is considered invalid if the ratio BCK/WS > 1024.
Relevant Registers
• Register 6[7] ENABLE_WS_MONITOR
• Register 6[6] ENABLE_BCK_MONITOR
MCLK_24M
Outputs the MCLK_24M clock. Requires the ADC to be on.
MCLK_128FS
Outputs the MCLK_128FS clock. Requires the ADC or DAC to be on.
Output 1’b0
Outputs a constant 1’b0.
Output 1’b1
Outputs a constant 1’b1.

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VERSION 0.3.2

ES9290 Product Datasheet

Analog Features
PGA
The ES9290 features an integrated analog programmable gain amplifier (PGA) that can implement a gain from +0dB to
+30dB in configurable steps of +3dB.
PGA Registers
• Register 82[3:0] PGA_GAIN_CTRL_CH1
• Register 82[7:4] PGA_GAIN_CTRL_CH2

APLL
Register 164[5:4]
SEL_PLL_CLK_IN ES9290
DATA_CLK
Fref Fvco Fout
1 1
Ni
Ф No
ACLK
1
Nfb

MCLK

Digital Core

Register 164[2:1] ADCs + Digital Core + DACs

SEL_MCLK_IN

Figure 28 - Functional Block Diagram of ES9290 APLL

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VERSION 0.3.2

ES9290 Product Datasheet

The ES9290 has a built in Analog PLL (APLL) for generating frequencies that are unavailable externally. For the application
note on the APLL, please ask your FAE or distributor.
For calculation of the PLL frequency output, use the following formulas:
𝐹 𝐹 225 𝐹 𝑁𝑓𝑏
𝐹𝑟𝑒𝑓 = ( 𝑖𝑛 ) 𝐹𝑣𝑐𝑜 = ( 𝑖𝑛 )∗𝑁𝑓𝑏 𝑁𝑓𝑏 = 𝐹𝑜𝑢𝑡 = ( 𝑖𝑛 )∗
𝑁𝑖 𝑁𝑖 𝐹𝐵𝐷𝐼𝑉 𝑁𝑖 𝑁𝑜
Where:
a. FBDIV is a 24-bit number
b. PLL frequency range requirements:
a. Fref requirement: 2.5MHz < Fref < 12 MHz
b. Fvco requirement: 90MHz < Fvco < 110MHz
c. Fout requirement: 22.5792/24.576MHz
c. Ni = input divider
• Accessible from Reg 172-170[8:0], PLL_CLK_IN_DIV
d. No = output divider
• Accessible from Reg 172-170[15:12], PLL_CLK_OUT_DIV
e. Nfb = feedback divider
• Accessible from Reg 167-169[23:0], PLL_CLK_FB_DIV
44.1kHz Base Rates (SYNC Slave Mode)
FS (kHz) DATA_CLK (MHz) Ni Fref (MHz) FBDIV Fvco (MHz) No Fout (MHz)
32-Bit Frame
352.8 22.5792 2 11.2896 4194304 90.3168 4 22.5792
176.4 11.2896 1 11.2896 4194304 90.3168 4 22.5792
88.2 5.6448 1 5.6448 2097152 90.3168 4 22.5792
44.1 2.8224 1 2.8224 1048576 90.3168 4 22.5792
16-Bit Frame
352.8 11.2896 1 11.2896 4194304 90.3168 4 22.5792
176.4 5.6448 1 5.6448 2097152 90.3168 4 22.5792
88.2 2.8224 1 2.8224 1048576 90.3168 4 22.5792
44.1 1.4112 1 1.4112 524288 90.3168 4 22.5792
Table 36 - APLL Divider Values for 44.1kHz Base Rates

48kHz Base Rates (SYNC Slave Mode)

FS (kHz) DATA_CLK (MHz) Ni Fref (MHz) FBDIV Fvco (MHz) No Fout (MHz)
32-Bit Frame
384 24.576 2 12.288 4194304 98.304 4 24.576
192 12.288 1 12.288 4194304 98.304 4 24.576
96 6.144 1 6.144 2097152 98.304 4 24.576
48 3.072 1 3.072 1048576 98.304 4 24.576
16-Bit Frame
384 12.288 1 12.288 4194304 98.304 4 24.576
192 6.144 1 6.144 2097152 98.304 4 24.576
96 3.072 1 3.072 1048576 98.304 4 24.576
48 1.536 1 1.536 524288 98.304 4 24.576
Table 37 - APLL Divider Values for 48kHz Base Rates

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VERSION 0.3.2

Recommended Operating Conditions

PARAMETER SYMBOL CONDITIONS
Operating Temperature TA -20C to +85C
AVCC_ADC +3.3V
AVCC_LD +3.3V
AVCC_CP +3.3V
AVDD +3.3V
DVDD Internal
VREF_BUF Internal
VREF Internal
MICBIAS Internal
PLL_REG Internal
PNEG Internal
IN_M / IN_P DC Offset 1.4V
IN_M / IN_P Input Voltage 1Vrms (2.8Vpp)
Table 41 - Recommended Operating Conditions

Recommended Power Up/Down Sequence

It is recommended for powering up that AVDD turns on ~200us before AVCC_LD, AVCC_CP and AVCC_ADC turn on.

Figure 29 - Recommended Power Up Sequence

For powering down, first make CHIP_EN low, then AVCC_LD, AVCC_CP and AVCC_ADC turn off, then AVDD turns off.

Figure 30 - Recommended Power Down Sequence

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ES9290 Product Datasheet

Power Consumption
Test Conditions (unless otherwise noted)
TA = 25ºC, AVCC_ADC = AVCC_LD = AVCC_CP = AVDD = +3.3V, 1.8Vrms differential input, 0dBFS digital input.
AVDD supply includes DVDD current.

Parameter Min Typ. Max Unit

Standby (CHIP_EN=0)
AVCC_ADC 0.1 µA
AVCC_LD 0.1 µA
AVCC_CP 0.1 µA
AVDD 0.4 µA

HW Mode 0-2, 4-6 (I2S /LJ Master, 32bit), MCLK = 24.576MHz

AVCC_ADC 19 mA
AVCC_LD 6.5 mA
AVCC_CP 8 mA
AVDD for HW2/HW6, Fs=48kHz 14 mA
AVDD for HW1/HW5, Fs=96kHz 19 mA
AVDD for HW0/HW4, Fs=192kHz 29 mA

HW Mode 8, 12 (I2S /LJ Slave, 32bit), MCLK = 24.576MHz

AVCC_ADC 18.5 mA
AVCC_LD 6.5 mA
AVCC_CP 8 mA
AVDD for HW8/HW12, Fs=48kHz 10 mA
AVDD for HW8/HW12, Fs=96kHz 13 mA
AVDD for HW8/HW12, Fs=192kHz 18 mA
AVDD for HW8/HW12, Fs=384kHz 19 mA

Table 42 - Power Consumption

Note: Current consumption can be reduced by externally supplying DVDD with 1.2V to decrease AVDD current.

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VERSION 0.3.2

ES9290 Product Datasheet

Performance
Test Conditions 1 (unless otherwise noted)
TA = 25ºC, AVCC_ADC = AVCC_LD = AVCC_CP = AVDD = +3.3V, fs = 48kHz, HW mode (I2S Master Mode)
Note: Performance numbers were measured using the ESS ES9290 1v0 evaluation board.

Parameter Min Typ. Max Unit

ADC Analog Input Characteristics:
Resolution 32 Bit
Input Voltage 0dBFS 2 Vrms
Input DC Common Mode 1.67 Vdc
Input Impedance 5 kΩ
fs=48kHz
-1dBFS -108 dB
BW=20Hz-20kHz
fs=96kHz
-1dBFS -106 dB
Stereo THD+N Ratio BW=20Hz-40kHz
(1.8Vrms differential input) fs=192kHz
-1dBFS -104 dB
BW=20Hz-80kHz
fs=384kHz
-1dBFS -103 dB
BW=20Hz-100kHz
Stereo Dynamic Range
A-weighted -60dBFS 116 dB
(2mVrms differential input)
Mono Dynamic Range
A-weighted -60dBFS 119 dB
(2mVrms differential input)

Table 43 – ES9290 ADC Performance

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ES9290 Product Datasheet

Parameter Min Typ. Max Unit

DAC Analog Output Characteristics:
Resolution 32 Bit
Output Voltage 0dBFS 2 Vrms
Output DC Voltage 0 V
fs=48kHz
2Vrms -110 dB
BW=20Hz-20kHz
fs=96kHz
2Vrms -108 dB
Stereo THD+N Ratio BW=20Hz-40kHz
(0dBFS input, single ended output) fs=192kHz
2Vrms -106 dB
BW=20Hz-80kHz
fs=384kHz
2Vrms -104 dB
BW=20Hz-100kHz
Mono THD+N Ratio fs=48kHz
4Vrms -116 dB
(0dBFS input, differential output) BW=20Hz-20kHz
Stereo Dynamic Range
A-weighted 2mVrms 116 dB
(-60dBFS input, single ended output)
Mono Dynamic Range
A-weighted 2mVrms 119 dB
(-60dBFS input, mono single ended output)
Mono Dynamic Range
A-weighted 4mVrms 122 dB
(-60dBFS input, differential output)
Table 44 – ES9290 DAC Performance

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VERSION 0.3.2

ES9290 Product Datasheet

Read/Write Register Addresses

Registers 0-178 (0x00 - 0xB2) are read and write registers.

Read-Only Register Addresses

Multi-Byte Registers
Multi-Byte registers must be written from LSB to MSB. Data is latched when MSB is written.
Multi-Byte registers must be read from LSB to MSB. Data is latched when LSB is read.
MSB is always stored in the highest register address.

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VERSION 0.3.2

ES9290 Product Datasheet

Register Map
Addr Addr
Register 7 6 5 4 3 2 1 0
(Hex) (Dec)
AUTO_FS_
FORCE_PLL_ AUTO_FS_ ENABLE_64FS_
0x00 0 SYS CONFIG SOFT_RESET RESERVED DETECT_ ENABLE_DAC ENABLE_ADC
LOCK DETECT MODE
BLOCK_64FS
ENABLE_TDM_ ENABLE_TDM_
0x01 1 CODEC CONFIG RESERVED
DECODE ENCODE
MCLK_128FS_
0x02 2 FRONT-END CLOCK CONTROL EN_CLK_DET MCLK_128FS_DIV
HALF_DIV
MCLK_24M_
0x03 3 BACK-END CLOCK CONTROL DAC_CLK_INV RESERVED RESERVED
DIV2
0x04 4 PCM MASTER CLK CONFIG MASTER_BCK_DIV
AUTO_CH_
0x05 5 TDM CONFIG 1 TDM_RESYNC RESERVED TDM_CH_NUM
DETECT
ENABLE_WS_ ENABLE_BCK_ TDM_VALID_
0x06 6 TDM CONFIG 2 TDM_WORD_WIDTH TDM_BIT_DEPTH TDM_LJ
MONITOR MONITOR EDGE
ADC_16BIT_
0x07 7 ADC TDM CH1 SLOT CONFIG RESERVED ADC_TDM_SLOT_SEL_CH1
DITHER_SHAPE
0x08 8 ADC TDM CH2 SLOT CONFIG RESERVED ADC_TDM_SLOT_SEL_CH2
0x09 9 DAC TDM CH1 SLOT CONFIG RESERVED DAC_TDM_SLOT_SEL_CH1
0x0A 10 DAC TDM CH2 SLOT CONFIG RESERVED DAC_TDM_SLOT_SEL_CH2
ADC_TDM_
0x0B 11 ADC DAISY CHAIN RESERVED ADC_TDM_DATA_LATCH_ADJ
DAISY_CHAIN
DAC_TDM_
0x0C 12 DAC DAISY CHAIN RESERVED DAC_TDM_DATA_LATCH_ADJ
DAISY_CHAIN
SLAVE_BCK_ MASTER_WS_ MASTER_WS_ MASTER_WS_ MASTER_BCK_ MASTER_MODE
0x0D 13 PCM MASTER MODE CONFIG RESERVED
INVERT CLK_PHASE PULSE_MODE INVERT INVERT _EN
0x0E 14 VOLUME UP RAMP RATE VOL_RAMP_RATE_UP
0x0F 15 VOLUME DOWN RAMP RATE VOL_RAMP_RATE_DOWN
0x10 16 SYNC CONFIG RESERVED
AUTO_MCLK_
AUTO_WS_ AUTO_ICG_ AUTO_FS_CLK_
0x11 17 AUTO SYNC CONFIG RESERVED 24M_PHASE_
PHASE_SYNC SYNC GEN_SYNC
SYNC
STATUS_MASK STATUS_MASK STATUS_MASK STATUS_MASK
STATUS_MASK
0x12 18 STATUS BITS MASK RESERVED _CH2_PEAK_ _CH1_PEAK_ _CH2_PEAK_ _CH1_PEAK_
_PLL_LOCKED
DET DET LATCH LATCH
STATUS_ STATUS_
0x13 19 STATUS BITS CLEAR RESERVED CLEAR_CH2_ CLEAR_CH1_
PEAK_LATCH PEAK_LATCH
0x14 20 RESERVED RESERVED
0x15 21 CHARGE PUMP CONFIG RESERVED CP_PDB_MUTE
0x16 22 RESERVED RESERVED
0x17 23 CHARGE PUMP CLOCK DIV CP_CLK_DIV
0x18-
24-38 RESERVED RESERVED
0x26
0x27 39 GPIO1/2 CONFIG GPIO2_CFG GPIO1_CFG
0x28 40 GPIO3/4 CONFIG GPIO4_CFG GPIO3_CFG
0x29 41 GPIO4_SDB GPIO3_SDB GPIO2_SDB GPIO1_SDB GPIO4_OE GPIO3_OE GPIO2_OE GPIO1_OE
GPIO CONTROLS
0x2A 42 INVERT_GPIO4 INVERT_GPIO3 INVERT_GPIO2 INVERT_GPIO1 GPIO4_WK_EN GPIO3_WK_EN GPIO2_WK_EN GPIO1_WK_EN
0x2B 43 GPIO READ RESERVED GPIO4_READ GPIO3_READ GPIO2_READ GPIO1_READ
GPIO_OR_SS_ GPIO_OR_ GPIO_OR_VOL_ GPIO_AND_SS_ GPIO_AND_ GPIO_AND_VOL
0x2C 44 GPIO OUTPUT LOGIC RESERVED FLAG_CH_SEL
RAMP AUTOMUTE MIN RAMP AUTOMUTE _MIN
0x2D 45 PWM COUNT PWM_COUNT
0x2E 46 PWM_FREQ
PWM FREQUENCY
0x2F 47 PWM_FREQ
ADC_DBQ_CLK ADC_DBQ_ ADC_DBQ_
0x30 48 ADC DBQ COEFF SEL ADC_DBQ_COEFF_SEL
_FAMILY_SEL 80HZ_HPF_EN 120HZ_HPF_EN
0x31 49 ADC_DBQ_A2
0x32 50 ADC PROG DBQ A2 COEFF ADC_DBQ_A2
0x33 51 ADC_DBQ_A2
0x34 52 ADC_DBQ_A1
0x35 53 ADC PROG DBQ A1 COEFF ADC_DBQ_A1
0x36 54 ADC_DBQ_A1
0x37 55 ADC_DBQ_B2
0x38 56 ADC PROG DBQ B2 COEFF ADC_DBQ_B2
0x39 57 ADC_DBQ_B2
0x3A 58 ADC_DBQ_B1
0x3B 59 ADC PROG DBQ B1 COEFF ADC_DBQ_B1
0x3C 60 ADC_DBQ_B1
0x3D 61 ADC_DBQ_B0
0x3E 62 ADC PROG DBQ B0 COEFF ADC_DBQ_B0
0x3F 63 ADC_DBQ_B0
0x40 64 ADC FIR FILTER ADC_FILTER_SHAPE RESERVED
CH2_DC_ CH1_DC_
0x41 65 ADC DC BLOCKING RESERVED
BLOCK_EN BLOCK_EN
PDM_INPUT_ PDM_SAMPLE_
0x42 66 PDM CONFIG RESERVED PDM_PHASE RESERVED
SEL EDGE
0x43 67 PDM CLK SELECT RESERVED MCLK_PDM_DIV
0x44 68 ADC VOLUME CH1 ADC_VOLUME_CH1

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VERSION 0.3.2

ES9290 Product Datasheet

0x45 69 ADC VOLUME CH2 ADC_VOLUME_CH2
0x46 70 ADC MIX VOLUME CH1 ADC_MIX_VOL_CH1
0x47 71 ADC MIX VOLUME CH2 ADC_MIX_VOL_CH2
0x48 72 ADC DIGITAL GAIN RESERVED ADC_DIGITAL_GAIN_CH2 RESERVED ADC_DIGITAL_GAIN_CH1
ADC_MIX_VOL_ ADC_MIX_VOL_ ADC_VOL_ ADC_VOL_
0x49 73 ADC PHASE INVERSION RESERVED PHASE_INV_ PHASE_INV_ PHASE_INV_ PHASE_INV_
CH2 CH1 CH2 CH1
0x4A-
74-81 RESERVED RESERVED
0x51
0x52 82 PGA GAIN CONTROL PGA_GAIN_CTRL_CH2 PGA_GAIN_CTRL_CH1
0x53-
83-87 RESERVED RESERVED
0x57
PEAK_DETECT PEAK_DETECT
0x58 88 PEAK DETECT ENABLE RESERVED
_CH2_EN _CH1_EN
LOCK_PEAK_
0x59 89 PEAK DETECT CONFIG RESERVED RESERVED PEAK_DECAY_RATE
VALUE
0x5A 90 PEAK_THRESH_CH1
PEAK THRESHOLDS
0x5B 91 PEAK_THRESH_CH2
0x5C-
92-93 RESERVED RESERVED
0x5D
0x5E 94 MIC BIAS RESERVED MB_VR_BYPB RESERVED MB_PDB MB_VR_SET
0x5F-
95-99 RESERVED RESERVED
0X63
NSMOD_CH2_
0x64 100 DAC NSMOD SEL RESERVED
SEL
0x65 101 RESERVED RESERVED
0x66 102 DAC DBQ COEFF SEL RESERVED DAC_DBQ_COEFF_SEL
0x67 103 DAC_DBQ_A2
0x68 104 DAC PROG DBQ A2 COEFF DAC_DBQ_A2
0x69 105 DAC_DBQ_A2
0x6A 106 DAC_DBQ_A1
0x6B 107 DAC PROG DBQ A1 COEFF DAC_DBQ_A1
0x6C 108 DAC_DBQ_A1
0x6D 109 DAC_DBQ_B2
0x6E 110 DAC PROG DBQ B2 COEFF DAC_DBQ_B2
0x6F 111 DAC_DBQ_B2
0x70 112 DAC_DBQ_B1
0x71 113 DAC PROG DBQ B1 COEFF DAC_DBQ_B1
0x72 114 DAC_DBQ_B1
0x73 115 DAC_DBQ_B0
0x74 116 DAC PROG DBQ B0 COEFF DAC_DBQ_B0
0x75 117 DAC_DBQ_B0
0x76 118 DAC FILTER CONFIG RESERVED BYPASS_IIR BYPASS_FIR4X BYPASS_FIR2X DAC_FILTER_SHAPE
0x77- 119-
RESERVED RESERVED
0x7A 122
0x7B 123 DAC VOLUME CH1 DAC_VOLUME_CH1
0x7C 124 DAC VOLUME CH2 DAC_VOLUME_CH2
0x7D 125 DAC MIX VOLUME CH1 DAC_MIX_VOL_CH1
0x7E 126 DAC MIX VOLUME CH2 DAC_MIX_VOL_CH2
0x7F 127 DIRECT MONITOR VOLUME CH1 DIR_MON_VOL_CH1
0x80 128 DIRECT MONITOR VOLUME CH2 DIR_MON_VOL_CH2
0x81- 129-
RESERVED RESERVED
0x86 134
DIR_MON_ DIR_MON_
0x87 135 DAC DIGITAL GAIN DAC_DIGITAL_GAIN_CH2 DAC_DIGITAL_GAIN_CH1
MUTE_CH2 MUTE_CH1
DIR_MON_VOL_ DIR_MON_VOL_ DAC_MIX_VOL_ DAC_MIX_VOL_ DAC_VOL_ DAC_VOL_
DIR_MON_ DIR_MON_
0x88 136 DAC PHASE INVERSION PHASE_INV_ PHASE_INV_ PHASE_INV_ PHASE_INV_ PHASE_INV_ PHASE_INV_
MONO_CH2 MONO_CH1
CH2 CH1 CH2 CH1 CH2 CH1
DAC_MUTE_CH DAC_MUTE_CH
0x89 137 DAC MUTE RESERVED
2 1
MUTE_RAMP_
0x8A 138 SOFT RAMP CONFIG RESERVED SOFT_RAMP_TIME
TO_GROUND
AUTOMUTE_EN AUTOMUTE_EN
0x8B 139 AUTOMUTE ENABLE RESERVED
_CH2 _CH1
0x8C 140 AUTOMUTE_TIME
AUTOMUTE TIME
0x8D 141 RESERVED AUTOMUTE_TIME
0x8E 142 AUTOMUTE_LEVEL
AUTOMUTE LEVEL
0x8F 143 AUTOMUTE_LEVEL
0x90 144 AUTOMUTE_OFF_LEVEL
AUTOMUTE OFF LEVEL
0x91 145 AUTOMUTE_OFF_LEVEL
0x92- 146-
RESERVED RESERVED
0xA3 164
PLL_CLK_ EN_PLL_CLK_
0xA4 164 PLL CLOCK SELECT RESERVED SEL_PLL_CLK_IN SEL_MCLK_IN EN_MCLK_IN
PHASE_INV IN
PLL_CLKSMP_
0xA5 165 PLL VCO & CP RESERVED PLL_CP_PDB PLL_VCO_PDB PLL_DIG_RSTB
PDB
0xA6 166 PLL REGULATOR RESERVED PLL_REG_PDB RESERVED
0xA7 167 PLL_CLK_FB_DIV
0xA8 168 PLL FEEDBACK DIV PLL_CLK_FB_DIV
0xA9 169 PLL_CLK_FB_DIV
0xAA 170 PLL IN & OUT DIV PLL_CLK_IN_DIV

83 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

ES9290 Product Datasheet

Register 5: TDM CONFIG 1

Bits [7] [6] [5] [4:0]
Default 1'b0 1'b0 1'b0 5'd1

Bits Mnemonic Description

[7] TDM_RESYNC Force TDM encoder & decoder to resync.
• 1'b0: Enable TDM codec synchronization (default)
• 1'b1: Force TDM codec to desynchronize.
[6] AUTO_CH_DETECT Automatically determine the number of TDM channels in a
sample, based on the BCK/WS ratio.
• 1'b0: Disabled, use TDM_CH_NUM to set channels
(default)
• 1'b1: Enabled, overrides TDM_CH_NUM
Note: Only active in TDM slave mode.
[5] RESERVED N/A
[4:0] TDM_CH_NUM Sets number of channels in each frame.
• 5'd0: 1 channel
• 5'd1: 2 channels (default)
• 5'd31: 32 channels

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VERSION 0.3.2

ES9290 Product Datasheet

Register 6: TDM CONFIG 2

Bits [7] [6] [5:4] [3:2] [1] [0]
Default 1'b1 1'b1 2'b00 2'b00 1'b0 1'b0

Bits Mnemonic Description

[7] ENABLE_WS_MONITOR Enable WS monitor, used to detect the validity of the WS signal.
WS is considered invalid if BCK/WS > 1024.
• 1'b0: Disabled
• 1'b1: Enabled (default)
[6] ENABLE_BCK_MONITOR Enable BCK monitor, used to detect the validity of the BCK
signal.
BCK is considered invalid if MCLK/BCK > 256.
• 1'b0: Disabled
• 1'b1: Enabled (default)
[5:4] TDM_WORD_WIDTH Sets the width, in bits, of one data word / subframe.
A subframe is a frame divided by the number of channels.
• 2'b00: 32-bits (default)
• 2'b01: 24-bits
• 2'b10: 16-bits
[3:2] TDM_BIT_DEPTH Sets the bit depth, number of data bits, in one data word /
subframe.
• 2'b00: 32-bit (default)
• 2'b01: 24-bit
• 2'b10: 16-bit
[1] TDM_VALID_EDGE Sets which WS edge the frame starts on.
• 1'b0: Frame starts on negedge of WS (default)
• 1'b1: Frame starts on posedge of WS
[0] TDM_LJ Sets left-justified mode.
• 1'b0: One BCK period delay (default)
• 1'b1: Left-justified
Register 7: ADC TDM CH1 SLOT CONFIG
Bits [7:6] [5] [4:0]
Default 2'd0 1'b0 5'd0

Bits Mnemonic Description

[7:6] RESERVED N/A
[5] ADC_16BIT_DITHER_SHAPE Sets the shape of the 16-bit data output dither.
• 1'b0: 1st order noise shaped (default)
• 1'b1: Flat noise shaped
[4:0] ADC_TDM_SLOT_SEL_CH1 Selects which TDM channel slot is filled by ADC CH1 data.
• 5'd0: Slot 1 (default)
• 5'd31: Slot 32

89 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Register 8: ADC TDM CH2 SLOT CONFIG

ES9290 Product Datasheet

Register 20: RESERVED

Bits Mnemonic Description

[7:1] RESERVED N/A
[0] CP_PDB_MUTE Charge pump state control when the DAC mutes.
• 1'b0: Keep charge pump on when DAC mutes
• 1'b1: Turn off charge pump when DAC mutes (default)
Register 22: RESERVED
Register 23: CHARGE PUMP CLOCK DIV
Bits [7:0]
Default 8'd31

Bits Mnemonic Description

Bits Mnemonic Description

[15:0] PWM_FREQ 16-bit value for the frequency of the PWM signal.
• 16'h0000: Disabled (default)
• 16'h0001: Minimum
• 16'hFFFF: Maximum
MCLK
frequency [Hz] =
PWM_FREQ + 1
PWM_COUNT
Duty Cycle [%] = ( ) · 100
PWM_FREQ + 1

101 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

ADC Registers
Register 48: ADC DBQ COEFF SEL
Bits [7] [6] [5] [4:0]
Default 1'b0 1'b0 1'b0 5'd1

Bits Mnemonic Description

[7] ADC_DBQ_CLK_FAMILY_SEL Selects the clock family for the automatic DBQ selection.
• 1'b0: 48kHz clock family (default)
• 1'b1: 44.1kHz clock family
[6] ADC_DBQ_80HZ_HPF_EN Sets the DBQ to one of the 80Hz HPFs, based on sample rate.
• 1'b0: Disabled (default)
• 1'b1: Enabled
[5] ADC_DBQ_120HZ_HPF_EN Sets the DBQ to one of the 120Hz HPFs, based on sample rate.
• 1'b0: Disabled (default)
• 1'b1: Enabled
[4:0] ADC_DBQ_COEFF_SEL Select the filter coefficients used by the ADC DBQ filter.
• 5'd0: Use programmable coeffs
• 5'd1: Bypass DBQ Filter (default)
• 5'd2: 1st order DC blocking filter
• 5'd3: 48kHz de-emphasis filter
• 5'd4: 44.1kHz de-emphasis filter
• 5'd5: 32kHz de-emphasis filter
• 5'd6: RIAA de-emphasis filter
• 5'd7: RIAA pre-emphasis filter
• 5'd8: 80Hz high-pass filter, FS = 48kHz
• 5'd9: 80Hz high-pass filter, FS = 96kHz
• 5'd10: 80Hz high-pass filter, FS = 192kHz
• 5'd11: 80Hz high-pass filter, FS = 384kHz
• 5'd12: 120Hz high-pass filter, FS = 48kHz
• 5'd13: 120Hz high-pass filter, FS = 96kHz
• 5'd14: 120Hz high-pass filter, FS = 192kHz
• 5'd15: 120Hz high-pass filter, FS = 384kHz
• 5'd16: 80Hz high-pass filter, FS = 44.1kHz
• 5'd17: 80Hz high-pass filter, FS = 88.2kHz
• 5'd18: 80Hz high-pass filter, FS = 176.4kHz
• 5'd19: 80Hz high-pass filter, FS = 352.8kHz
• 5'd20: 120Hz high-pass filter, FS = 44.1kHz
• 5'd21: 120Hz high-pass filter, FS = 88.2kHz
• 5'd22: 120Hz high-pass filter, FS = 176.4kHz
• 5'd23: 120Hz high-pass filter, FS = 352.8kHz
• Others: Reserved

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VERSION 0.3.2

ES9290 Product Datasheet

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VERSION 0.3.2

ES9290 Product Datasheet

Register 64: ADC FIR FILTER

Bits [7:5] [4:0]
Default 3'd0 5'd0

Bits Mnemonic Description

[7:5] ADC_FILTER_SHAPE Selects the 8x decimation FIR filter shape.
• 3'd0: Minimum phase (default)
• 3'd1: Linear phase fast roll-off apodizing
• 3'd2: Linear phase fast roll-off
• 3'd3: Linear phase fast roll-off low ripple
• 3'd4: Linear phase slow roll-off
• 3'd5: Minimum phase fast roll-off
• 3'd6: Minimum phase slow roll-off
• 3'd7: Minimum phase slow roll-off low dispersion
[4:0] RESERVED N/A
Register 65: ADC DC BLOCKING
Bits [7] [6] [5:0]
Default 1'b1 1'b1 6'b111111

Bits Mnemonic Description

[7] CH2_DC_BLOCK_EN Enable the CH2 DC blocking filter on audio datapath.
• 1'b0: Bypass DC blocking filter
• 1'b1: Use DC blocking filter (default)
[6] CH1_DC_BLOCK_EN Enable the CH1 DC blocking filter on audio datapath.
• 1'b0: Bypass DC blocking filter
• 1'b1: Use DC blocking filter (default)
[5:0] RESERVED N/A

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VERSION 0.3.2

ES9290 Product Datasheet

Register 66: PDM CONFIG

[7:0] ADC_MIX_VOL_CH2 Volume of ADC_CH1 mixed into ADC_CH2.
-0dB to -127dB, 0.5dB steps.
• 8'h00: 0dB
• 8'hFE: -127dB
• 8'hFF: -inf dB (default)

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VERSION 0.3.2

ES9290 Product Datasheet

Register 72: ADC DIGITAL GAIN

Bits [7] [6:4] [3] [2:0]
Default 1'b0 3'd0 1'b0 3'd0

Bits Mnemonic Description

[7] RESERVED N/A
[6:4] ADC_DIGITAL_GAIN_CH2 ADC CH2 gain boost. +0dB to +42dB, +6dB steps.
• 3'd0: +0dB (default)
• 3'd1: +6dB
• 3'd2: +12dB
• 3'd3: +18dB
• 3'd4: +24dB
• 3'd5: +30dB
• 3'd6: +36dB
• 3'd7: +42dB
[3] RESERVED N/A
[2:0] ADC_DIGITAL_GAIN_CH1 ADC CH1 gain boost. +0dB to +42dB, +6dB steps.
• 3'd0: +0dB (default)
• 3'd1: +6dB
• 3'd2: +12dB
• 3'd3: +18dB
• 3'd4: +24dB
• 3'd5: +30dB
• 3'd6: +36dB
• 3'd7: +42dB

107 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Register 73: ADC PHASE INVERSION

Bits [7:4] [3] [2] [1] [0]
Default 4'd0 1'b0 1'b0 1'b0 1'b0

Bits Mnemonic Description

[7:4] RESERVED N/A
[3] ADC_MIX_VOL_PHASE_INV_CH2 Inverts the phase of ADC_MIX_VOL_CH2.
• 1'b0: Non-inverted, ADC_CH1 added into ADC_CH2
(default)
• 1'b1: Inverted, ADC_CH1 subtracted from ADC_CH2
[2] ADC_MIX_VOL_PHASE_INV_CH1 Inverts the phase of ADC_MIX_VOL_CH1.
• 1'b0: Non-inverted, ADC_CH2 added into ADC_CH1
(default)
• 1'b1: Inverted, ADC_CH2 subtracted from ADC_CH1
[1] ADC_VOL_PHASE_INV_CH2 Inverts the phase of ADC_VOLUME_CH2.
• 1'b0: Non-inverted (default)
• 1'b1: Inverted
[0] ADC_VOL_PHASE_INV_CH1 Inverts the phase of ADC_VOLUME_CH1.
• 1'b0: Non-inverted (default)
• 1'b1: Inverted
Register 81-74: RESERVED
Register 82: PGA GAIN CONTROL
Bits [7:4] [3:0]
Default 4'd0 4'd0

Bits Mnemonic Description

[7:4] PGA_GAIN_CTRL_CH2 Sets the gain applied to the PGA (+0dB to +30dB, 3dB steps).
Valid from 4'd0 to 4'd10.
[3:0] PGA_GAIN_CTRL_CH1 Sets the gain applied to the PGA (+0dB to +30dB, 3dB steps).
Valid from 4'd0 to 4'd10.

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VERSION 0.3.2

ES9290 Product Datasheet

Register 87-83: RESERVED

Bits Mnemonic Description

[7:2] RESERVED N/A
[1] PEAK_DETECT_CH2_EN Enables the ADC CH2 peak detector.
• 1'b0: Disabled (default)
• 1'b1: Enabled
[0] PEAK_DETECT_CH1_EN Enables the ADC CH1 peak detector.
• 1'b0: Disabled (default)
• 1'b1: Enabled
Register 89: PEAK DETECT CONFIG
Bits [7] [6] [5] [4:0]
Default 1'd0 1'b0 1'b0 5'd10

Bits Mnemonic Description

[7] RESERVED N/A
[6] LOCK_PEAK_VALUE Locks the current peak detector values, for reading back.
• 1'b0: Peak detector value can update (default)
• 1'b1: Peak detector value locked
[5] RESERVED N/A
[4:0] PEAK_DECAY_RATE Sets the speed at which the peak detector value will decay
when greater than the input signal.
• 5'd0: Instant decay
• 5'd1: Fastest decay
• 5'd10: Default value
• 5'd22: Slowest decay
• Others: Reserved

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VERSION 0.3.2

ES9290 Product Datasheet

Register 91-90: PEAK THRESHOLDS

Bits [15:8] [7:0]
Default 8'hFF 8'hFF

Bits Mnemonic Description

[15:8] PEAK_THRESH_CH2 Threshold value to trigger the PEAK_FLAG in the CH2 peak
detector.
Triggers if the input signal > PEAK_THRESH_CH2.
• 8'h01: -48dB
• 8'hFF: 0dB (default)
PEAK_THRESH_CH2
threshold [dB] = 20 · log10( )
28 − 1
[7:0] PEAK_THRESH_CH1 Threshold value to trigger the PEAK_FLAG in the CH1 peak
detector.
Triggers if the input signal > PEAK_THRESH_CH1.
• 8'h01: -48dB
• 8'hFF: 0dB (default)
PEAK_THRESH_CH1
threshold [dB] = 20 · log10( )
28 − 1
Register 93-92: RESERVED
Register 94: MIC BIAS
Bits [7] [6] [5:4] [3] [2:0]
Default 1'b0 1'b0 2'b00 1'b0 3'b010

Bits Mnemonic Description

[7] RESERVED N/A
[6] MB_VR_BYPB Bypass the MICBIAS reference voltage select.
• 1'b0: 2.85V (default)
• 1'b1: Determined by MB_VR_SET
[5:4] RESERVED N/A
[3] MB_PDB Enables the MICBIAS.
• 1'b0: Disabled (default)
• 1'b1: Enabled
[2:0] MB_VR_SET Set mic bias voltage.
• 3'b000: 1.45V
• 3'b001: 2.55V
• 3'b010: 2.65V (default)
• 3'b011: 2.75V
• 3'b100: 1.65V
• 3'b101: 1.75V
• 3'b110: 1.85V
• 3'b111: 1.95V
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VERSION 0.3.2

ES9290 Product Datasheet

Register 99-95: RESERVED

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VERSION 0.3.2

ES9290 Product Datasheet

DAC Registers
Register 100: DAC NSMOD SEL
Bits [7:1] [0]
Default 6'd0 1'b0

Bits Mnemonic Description

[7:1] RESERVED N/A
[0] NSMOD_CH2_SEL Selects CH2 nsmod input.
1'b0: Input from CH2 interpolation path (default)
1'b1: Input from CH1 interpolation path
Register 101: RESERVED
Register 102: DAC DBQ COEFF SEL
Bits [7:5] [4:0]
Default 3'd0 5'd1

Bits Mnemonic Description

[7:5] RESERVED N/A
[4:0] DAC_DBQ_COEFF_SEL Select the filter coefficients used by the DAC DBQ filter.
5'd0: Use programmable coeffs
5'd1: Bypass DBQ Filter (default)
5'd2: 1st order DC blocking filter
5'd3: 48kHz de-emphasis filter
5'd4: 44.1kHz de-emphasis filter
5'd5: 32kHz de-emphasis filter
5'd6: RIAA de-emphasis filter
5'd7: RIAA pre-emphasis filter
5'd8: 80Hz high-pass filter, FS = 48kHz
5'd9: 80Hz high-pass filter, FS = 96kHz
5'd10: 80Hz high-pass filter, FS = 192kHz
5'd11: 80Hz high-pass filter, FS = 384kHz
5'd12: 120Hz high-pass filter, FS = 48kHz
5'd13: 120Hz high-pass filter, FS = 96kHz
5'd14: 120Hz high-pass filter, FS = 192kHz
5'd15: 120Hz high-pass filter, FS = 384kHz
5'd16: 80Hz high-pass filter, FS = 44.1kHz
5'd17: 80Hz high-pass filter, FS = 88.2kHz
5'd18: 80Hz high-pass filter, FS = 176.4kHz
5'd19: 80Hz high-pass filter, FS = 352.8kHz
5'd20: 120Hz high-pass filter, FS = 44.1kHz
5'd21: 120Hz high-pass filter, FS = 88.2kHz
5'd22: 120Hz high-pass filter, FS = 176.4kHz
5'd23: 120Hz high-pass filter, FS = 352.8kHz
Others: Reserved
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VERSION 0.3.2

ES9290 Product Datasheet

113 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Register 118: DAC FILTER CONFIG

Bits [7:6] [5] [4] [3] [2:0]
Default 2'd0 1'b0 1'b0 1'b0 3'd0

Bits Mnemonic Description

[7:6] RESERVED N/A
[5] BYPASS_IIR Bypass the IIR filter.
1'b0: Non-bypassed (default)
1'b1: Bypassed
[4] BYPASS_FIR4X Bypass the 4X FIR filter.
1'b0: Non-bypassed (default)
1'b1: Bypassed
[3] BYPASS_FIR2X Bypass the 2X FIR filter.
1'b0: Non-bypassed (default)
1'b1: Bypassed
[2:0] DAC_FILTER_SHAPE Selects the 8x interpolation FIR filter shape.
3'd0: Minimum phase (default)
3'd1: Linear phase fast roll-off apodizing
3'd2: Linear phase fast roll-off
3'd3: Linear phase fast roll-off low ripple
3'd4: Linear phase slow roll-off
3'd5: Minimum phase fast roll-off
3'd6: Minimum phase slow roll-off
3'd7: Minimum phase slow roll-off low dispersion
Register 122-119: RESERVED
Register 123: DAC VOLUME CH1
Bits [7:0]
Default 8'h02

Bits Mnemonic Description

[7:0] DAC_VOLUME_CH1 DAC CH1 volume.
+1dB to -126dB, 0.5dB steps.
8'h00: +1dB
8'h02: 0dB (default)
8'hFE: -126dB
8'hFF: Mute

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 114
VERSION 0.3.2

ES9290 Product Datasheet

Register 124: DAC VOLUME CH2

ES9290 Product Datasheet

Register 134-129: RESERVED

Bits Mnemonic Description

[7] DIR_MON_MUTE_CH2 Mutes the CH2 ADC direct monitor signal.
1'b0: Normal operation (default)
1'b1: Direct monitor signal muted
[6:4] DAC_DIGITAL_GAIN_CH2 DAC CH2 gain boost. +0dB to +42dB, +6dB steps.
3'd0: +0dB (default)
3'd1: +6dB
3'd2: +12dB
3'd3: +18dB
3'd4: +24dB
3'd5: +30dB
3'd6: +36dB
3'd7: +42dB
[3] DIR_MON_MUTE_CH1 Mutes the CH1 ADC direct monitor signal.
1'b0: Normal operation (default)
1'b1: Direct monitor signal muted
[2:0] DAC_DIGITAL_GAIN_CH1 DAC CH1 gain boost. +0dB to +42dB, +6dB steps.
3'd0: +0dB (default)
3'd1: +6dB
3'd2: +12dB
3'd3: +18dB
3'd4: +24dB
3'd5: +30dB
3'd6: +36dB
3'd7: +42dB

117 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Register 136: DAC PHASE INVERSION

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0

Bits Mnemonic Description

[7] DIR_MON_MONO_CH2 Adds both ADC direct monitor signals onto the CH2 DAC
datapath.
Both signals are controlled by the CH2 volume and mute
controls.
1'b0: Disabled, CH2 ADC monitored on CH2 DAC (default)
1'b1: Enabled, CH1 ADC & CH2 ADC monitored on CH2 DAC
[6] DIR_MON_MONO_CH1 Adds both ADC direct monitor signals onto the CH1 DAC
datapath.
Both signals are controlled by the CH1 volume and mute
controls.
1'b0: Disabled, CH1 ADC monitored on CH1 DAC (default)
1'b1: Enabled, CH1 ADC & CH2 ADC monitored on CH1 DAC
[5] DIR_MON_VOL_PHASE_INV_CH2 Inverts the phase of DIR_MON_VOL_CH2.
1'b0: Non-inverted (default)
1'b1: Inverted
[4] DIR_MON_VOL_PHASE_INV_CH1 Inverts the phase of DIR_MON_VOL_CH1.
1'b0: Non-inverted (default)
1'b1: Inverted
[3] DAC_MIX_VOL_PHASE_INV_CH2 Inverts the phase of DAC_MIX_VOL_CH2.
1'b0: Non-inverted, DAC_CH1 added into DAC_CH2 (default)
1'b1: Inverted, DAC_CH1 subtracted from DAC_CH2
[2] DAC_MIX_VOL_PHASE_INV_CH1 Inverts the phase of DAC_MIX_VOL_CH1.
1'b0: Non-inverted, DAC_CH2 added into DAC_CH1 (default)
1'b1: Inverted, DAC_CH2 subtracted from DAC_CH1
[1] DAC_VOL_PHASE_INV_CH2 Inverts the phase of DAC_VOLUME_CH2.
1'b0: Non-inverted (default)
1'b1: Inverted
[0] DAC_VOL_PHASE_INV_CH1 Inverts the phase of DAC_VOLUME_CH1.
1'b0: Non-inverted (default)
1'b1: Inverted

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 118
VERSION 0.3.2

ES9290 Product Datasheet

Register 137: DAC MUTE

Bits [7:2] [1] [0]
Default 6'd0 1'b0 1'b0

Bits Mnemonic Description

[7:2] RESERVED N/A
[1] DAC_MUTE_CH2 Mutes the CH2 DAC datapath, will not mute the monitor signal.
1'b0: Normal CH2 operation (default)
1'b1: Mute CH2 DAC
[0] DAC_MUTE_CH1 Mutes the CH1 DAC datapath, will not mute the monitor signal.
1'b0: Normal CH1 operation (default)
1'b1: Mute CH1 DAC
Register 138: SOFT RAMP CONFIG
Bits [7:6] [5] [4:0]
Default 2'd0 1'b1 5'd3

Bits Mnemonic Description

[7:6] RESERVED N/A
[5] MUTE_RAMP_TO_GROUND 1'b0: When ramped to min volume during normal mute, do not
soft ramp to ground
1'b1: When ramped to min volume during normal mute, soft
ramp to ground for power saving (default)
normal mute includes: automute, mute by register, mute by
GPIO
[4:0] SOFT_RAMP_TIME Sets the amount of time that it takes to perform a soft start
ramp.
This time affects both "ramp to ground" and "ramp to AVCC/2".
Valid from 0 to 20 (inclusive).
215 · 2SOFT_RAMP_TIME · 2MCLK_24M_DIV2
Time [s] =
𝑀𝐶𝐿𝐾

119 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Register 139: AUTOMUTE ENABLE

Bits [7:2] [1] [0]
Default 6'd0 1'b1 1'b1

Bits Mnemonic Description

[7:2] RESERVED N/A
[1] AUTOMUTE_EN_CH2 Enables CH2 automute.
1'b0: Disabled
1'b1: Enabled (default)
Note: Automute will not engage if the ADC monitor is running.
[0] AUTOMUTE_EN_CH1 Enables CH1 automute.
1'b0: Disabled
1'b1: Enabled (default)
Note: Automute will not engage if the ADC monitor is running.
Register 141-140: AUTOMUTE TIME
Bits [15:11] [10:0]
Default 5'd0 11'h0F

Bits Mnemonic Description

[15:11] RESERVED N/A
[10:0] AUTOMUTE_TIME Configures the amount of time in seconds the audio must
remain below AUTOMUTE_LEVEL before an
automute condition is flagged.
11'h000: Disabled
11'h001: Slowest
11'h00F: Default
11'h7FF: Fastest
225
Time [s] =
AUTOMUTE_TIME · MCLK_128FS · 264FS_MODE
Register 143-142: AUTOMUTE LEVEL
Bits [15:0]
Default 16'h0008

Bits Mnemonic Description

[15:0] AUTOMUTE_LEVEL The threshold which the audio must be below before an
automute condition is flagged.
16'h0001: -138dB
16'h0008: -120dB (default)
16'hFFFF: -42dB
AUTOMUTE_LEVEL
Level [dB] = 20 · log10( )
(216 − 1) · 27
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 120
VERSION 0.3.2

ES9290 Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 122
VERSION 0.3.2

ES9290 Product Datasheet

Register 166: PLL REGULATOR

Bits [7:4] [3] [2:0]
Default 4'd0 1'b0 3'b010

Bits Mnemonic Description

[7:4] RESERVED N/A
[3] PLL_REG_PDB Power down the PLL regulator.
1'b0: Disable the PLL regulator (default)
1'b1: Enable the PLL regulator
[2:0] RESERVED N/A
Register 169-167: PLL FEEDBACK DIV
Bits [23:0]
Default 24'h100000

Bits Mnemonic Description

[23:0] PLL_CLK_FB_DIV Sets the PLL clock feedback divider (Nfb).
24'h000000: Reserved
24'h100000: Default
24'hn: Divide by 2^25/n
Register 172-170: PLL IN & OUT DIV
Bits [23:16] [15:12] [11:10] [9] [8:0]
Default 8'b00010000 4'd3 2'd0 1'b1 9'd0

Bits Mnemonic Description

[23:16] RESERVED N/A
[15:12] PLL_CLK_OUT_DIV Sets the PLL clock output divider (No).
4'd0: Reserved
4'd3: Divide by 4. (default)
4'dn: Divide by (n + 1).
[11:10] RESERVED N/A
[9] PLL_FB_DIV_LOAD Write 1'b1 then write 1'b0 to load CLK_FB_DIV.
[8:0] PLL_CLK_IN_DIV Sets the PLL clock input divider (Ni).
9'd0: Reserved (default)
9'dn: Divide by (n + 1).
Register 178-173: RESERVED

123 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

[15:0] PEAK_CH2 Channel 2 peak detector value readback.
PEAK_CH2
𝑃𝑒𝑎𝑘[dB] = 20 · log10( 16 )
2 −1

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 126
VERSION 0.3.2

ES9290 Product Datasheet

Register 242: DAC VOL MIN READ

Bits [7:2] [1] [0]
Default - -

Bits Mnemonic Description

[7:2] RESERVED N/A
[1] VOL_MIN_CH2 CH2 minimum volume flag.
[0] VOL_MIN_CH1 CH1 minimum volume flag.
Register 243: DAC AUTOMUTE READ
Bits [7:2] [1] [0]
Default - -

Bits Mnemonic Description

[7:2] RESERVED N/A
[1] AUTOMUTE_CH2 CH2 automute status flag.
[0] AUTOMUTE_CH1 CH1 automute status flag.
Register 244: DAC SOFT RAMP UP READ
Bits [7:2] [1] [0]
Default - -

Bits Mnemonic Description

[7:2] RESERVED N/A
[1] SS_RAMP_UP_CH2 CH2 soft ramped up flag.
[0] SS_RAMP_UP_CH1 CH1 soft ramped up flag.
Register 245: DAC SOFT RAMP DOWN READ
Bits [7:2] [1] [0]
Default - -

Bits Mnemonic Description

[7:2] RESERVED N/A
[1] SS_RAMP_DOWN_CH2 CH2 soft ramped down flag.
[0] SS_RAMP_DOWN_CH1 CH1 soft ramped down flag.
Register 251-246: RESERVED

127 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

ES9290 Reference Schematics

Software (SW) Mode

Figure 31 - ES9290 Software Mode Reference Schematic

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 128
VERSION 0.3.2

ES9290 Product Datasheet

Hardware (HW) Mode

Figure 32 - ES9290 Hardware Mode Reference Schematic

129 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Internal Pad Circuitry

Pin Name Type Pin Equivalent Circuit

AVCC_CP 1
AVCC_LD 2
Power
AVCC_ADC 11
AVDD 21

AGND_LD 3
AGND_DAC 7
AGND_ADC Ground 16
DGND 22
AGND_CP 37

CHIP_EN Reset 20

MODE 18
DATA_CLK 24
DATA1 25
DATA2 26
DATA3 27
GPIO1 28
GPIO2 29
Digital I/O
GPIO3 30
GPIO4/HW3 31
MISO/ADDR0/MUTE_MCLK_CTRL 32
SS/ADDR1/HW2 33
SCLK/SCL/HW1 34
MOSI/SDA/HW0 35
RT1 36

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 130
VERSION 0.3.2

ES9290 Product Datasheet

ACLK Clock I 19

VREF_BUF 8
VREF 9
MICBIAS Analog I/O 10
PLL_REG 17
C1 40

Analog I/O
C2 39
Neg

IN_P1 12
IN_M1 13
Analog I
IN_M2 14
IN_P2 15

131 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

Reflow Process Considerations

Temperature Controlled
For lead-free soldering, the characterization and optimization of the reflow process is the most important factor to consider.
The lead-free alloy solder has a melting point of 217°C. This alloy requires a minimum reflow temperature of 235°C to
ensure good wetting. The maximum reflow temperature is in the 245°C to 260°C range, depending on the package size
(RPC-2-Pb-Free Process - Classification Temperatures (Tc)). This narrows the process window for lead-free soldering to
10°C to 20°C.
The increase in peak reflow temperature in combination with the narrow process window makes the development of an
optimal reflow profile a critical factor for ensuring a successful lead-free assembly process. The major factors contributing
to the development of an optimal thermal profile are the size and weight of the assembly, the density of the components, the
mix of large and small components, and the paste chemistry being used.
Reflow profiling needs to be performed by attaching calibrated thermocouples well adhered to the device as well as other
critical locations on the board to ensure that all components are heated to temperatures above the minimum reflow
temperatures and that smaller components do not exceed the maximum temperature limits (Table RPC-2).
To ensure that all packages can be successfully and reliably assembled, the reflow profiles studied and recommended by
ESS are based on the JEDEC/IPC standard J-STD-020 revision D.1.

Figure 35 - IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1)

Reflow is allowed 3 times. Caution must be taken to ensure time between re-flow runs does not exceed the allowed time by
the moisture sensitivity label. If the time elapsed between the re-flows exceeds the moisture sensitivity time bake the board
according to the moisture sensitivity label instructions.

135 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Manual
Allowed up to 2 times with maximum temperature of 350ºC no longer than 3 seconds.

RPC-1 Classification Reflow Profile

Profile Feature Pb-Free Assembly
Preheat/Soak
Temperature Min (Tsmin) 150°C
Temperature Max (Tsmax) 200°C
Time (ts) from (Tsmin to Tsmax) 60-120 seconds
Ramp-up rate (TL to Tp) 3°C / second maximum
Liquidous temperature (TL) 217°C
Time (tL) maintained above TL 60-150 seconds
For users Tp must not exceed the classification temp in
Table RPC-2.
Peak package body temperature (Tp)
For suppliers Tp must equal or exceed the Classification
temp in Table RPC-2.
Time (tp)* within 5°C of the specified classification
30* seconds
temperature (Tc)
Ramp-down rate (Tp to TL) 6°C / second maximum
Time 25°C to peak temperature 8 minutes maximum
* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
Table 47 - RPC-1 Classification Reflow Profile
All temperatures refer to the center of the package, measured on the package body surface that is facing up during
assembly reflow (e.g., live-bug). If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e.,
dead-bug), Tp shall be within ±2°C of the live-bug Tp and still meet the Tc requirements, otherwise, the profile shall be
adjusted to achieve the latter. To accurately measure actual peak package body temperatures, refer to JEP140 for
recommended thermocouple use.
Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles.
Actual board assembly profiles should be developed based on specific process needs and board designs and should not
exceed the parameters in Table RPC-1.
For example, if Tc is 260°C and time tp is 30 seconds, this means the following for the supplier and the user.
For a supplier: The peak temperature must be at least 260°C. The time above 255°C must be at least 30 seconds.
For a user: The peak temperature must not exceed 260°C. The time above 255°C must not exceed 30 seconds.
All components in the test load shall meet the classification profile requirements.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 136
VERSION 0.3.2

ES9290 Product Datasheet

RPC-2-Pb-Free Process - Classification Temperatures (Tc)

Package Thickness Volume mm3, <350 Volume mm3, 350 to 2000 Volume mm3, >2000
<1.6 mm 260°C 260°C 260°C
1.6 mm - 2.5 mm 260°C 250°C 245°C
>2.5 mm 250°C 245°C 245°C
Table 48 - RPC-2 Pb Free Classification Temperature
At the discretion of the device manufacturer, but not the board assembler/user, the maximum peak package body
temperature (Tp) can exceed the values specified in Table RPC-2. The use of a higher Tp does not change the
classification temperature (Tc).
Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or nonintegral heat sinks.
The maximum component temperature reached during reflow depends on package thickness and volume. The use of
convection reflow processes reduces the thermal gradients between packages. However, thermal gradients due to
differences in thermal mass of SMD packages may still exist.

137 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link]
VERSION 0.3.2

ES9290 Product Datasheet

Ordering Information
Part Number Description Package
SABRE 32-bit 2 Channel ADC/DAC CODEC with built-in digital
ES9290Q 5mm x 5mm 40 QFN
filters, and multiple input-output formats.
Table 49 - Ordering Information

Revision History
Current Version 0.3.2

Rev. Date Notes

0.3.1 June, 2024 Initial Release
• Added note to daisy chain section about 32 & 24 bit daisy chain
• Updated DAC performance table
0.3.2 September, 2024 • Updated CLOCK VALID flag description
• Updated APLL divider value tables
• Corrected reference schematic titles

ESS ICs are not intended, authorized, or warranted for use as components in military applications, medical devices or life support systems. ESS assumes no liability and disclaims any
expressed, implied or statutory warranty for use of ESS ICs in such unsuitable applications.

No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise,
without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are
subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending.

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • [Link] 138

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