Interrupt Handling Structure of an MCU
We have already studied that the 8051 family MCU has the following interrupt
structure-t external interrupts, INTO and INT1 (also INT2 in 8052) and internal interrupts
from the timing and serial devices. There is an interrupt-handling mechanism for the masking
of an interrupt source, priority assign me and letting use of a vector address for the interrupt
service routine codes corresponding to an interrupt source or group of sources. The
mechanism uses the bits at the IE and IP registers at the SFR area with 8051 and uses the
processor vector addresses between 0x0003,and 0x005A. (Section 3.5). A program mer
programs the IE and IP bits for masking and priority assignments (Table 3.19). Programmer
cam also use the default priority assignments, which the system assigns at the start.
A precise and thorough understanding of the interrupt structure in 8051 and other MCU
families ha however not been dealt so far, though it is a matter of great importance for smart
use and for the realisation of full potential of any MCU. The interrupt structure lets us
employ an MCU for multiple real time control of the tasks. It lets us achieve the real time use
and synchronisation of the devices an resources, which are present in the MCU. In this
chapter these aspects will be dealt with in detail an concepts described here will enable a
reader to understand the interrupt structure of different MCUs.
Different elements of an interrupt handling structure are given in below diagram
1. Identification of the interrupt source. This activates the interrupt structure.m
2. Enabling (un-masking) or disabling (masking) of the sources. This enables the
uninterrupted ex- ecution of a set of instructions by disabling at the first instruction of the set
and enabling at the last instruction of the set. Also, at any given instance, the needed ones can
be enabled and remain- ing ones masked.
3. Finding or generating the address of the interrupt service routine (ISR) address where the
CPU vectors for the service and processor then vectoring to the ISR at that distinct address
for a dis- tinct source (or source group).
4. Priority assignments, default assignments, increasing or lowering priorities as per need
Routine, Interrupt and Interrupt Service Routine
Let us assume that a program or routine is executing and running a task. The running task is
at the foreground program. The foreground program may call another routine at some point
of time using an instruction (for example, ACALL or LCALL instruction of 8051). The call
instruction executes as follows:
1. Saves the PC (all upper and lower bytes at PGH and PCL) at the stack and re-adjusts the
stack pointer.
2. Gets the address of the called-routine (using 16 bits at the instruction in case of LCALL
and the 11 lower bits at the instruction and 5 higher bits from the 5 higher bits of PC in case
of ACALL).
3. The return instruction (a last instruction RET at the routine called) executes as follows:
Restores the PC (all upper and lower bytes at PCH and PCL) from the stack and re-adjusts
the stack pointer.
A call after executing an instruction is a planned (user programmed) diversion from
the task current sequence of instructions A to another sequence of instructions, which
services another task B. B can also call another task C at a certain point of time and that can
call third task D and so on. The calls to the B, C, and D are also referred as the nested calls
Any byte at an addressed location or register (other than the bytes at the PC) ma also be saved
in case the ISR is likely to change it during execution.
The ISR return instruction (a last instruction RETI at the ISR) executes as follows: and PCL)
at the stack and re-adjusts.
1. Restores the PC (all upper and lower bytes at PCH
2. stack pointerinterrupt structure. Make it identical to the one at their of he 3. Check another
pending interrupt service(s). If yes, initiate another servicing action(s).
4. If no, start executing the foreground A or the routine left ealier on the interrupt. ISR B
must also restore in the LIFO way the saved parameters by the pops from the stack. Any byte
bytes at the Prestres PC-like on RET in of an addressed location or instruction. The RETI ales
in the be restored by the ISR before all the previous states of the variables and flags in the
registers, so that h foreground program functioning does not affect.
SERVICING OF INTERRUPTS IN 8051
A program in 8051 is interruptible from the seven (or more in certain versions)
permissible south When an interrupt occurs, the CPU in Intel 8051 does the following
actions:
1. Completes the current instruction. If EA bit is 0 (IE.7, the bit 7 of the IE register, bit
address AFH) then it does not recognise any of the seven remaining IE bits, whether set for
masking offe enabling a source. EA is also called primary level bit as it functions as an
interrupt struct enabling bit. Therefore, the foreground program continues to execute as
before.
2. When EA=1 and the source, which is un-masked (enabled) by setting an appropriate bit at
the and following steps take place. 1, the servicing of that source interrupt will oceand
Step 1: The CPU pushes on to the internal stack two CPU registers PCH and PCL.
Step 2: Reset the EA0 momentarily (until execution of the first instruction) and the sets it
again 1 automatically at the ISR.
Step 3: CPU sets the PC bits as per the corresponding ISR_VECTADDR, one among the
seven vector addresses. ISR VECTADDR is a vector address (Table 3.20). It is an address
where the CPU program counter vectors (program flow changes the direction) for the
execution of the ISR after Step2 A service program can either execute the routine or jump or
call the ISR first instruction address if the ISR length is longer than 8 bytes and routine
executes from there.
Step 4: After the first instruction at the ISR, servicing of any further interrupts from any
lower prior ty interrupt are the only ones disabled until RETI executes and returns from the
ISR occurs. The higher riority ones are polled at the end of each instruction. (An ISR
instruction must not have reset EA=0)
1. A vector address is a memory address where the CPU program counter-vectors (program
flow changes the direction) automatically for the execution of the ISR, which corresponds to
the enabled (un-masked) interrupting source (or source group).
2. An action on interrupt from a source can occur only whenever the CPU has been
previously enabled by the program (or internally by the CPU itself) to respond to that
interrupt.
Identification of an Interrupt Source
A flag enables identification by the processor
an event when an either at a regist bits in the corupt status register of at the interrupt ptsource
activates. A flag can be with the control bits in the control register. Examples are TCON and
Scoregister or may coexist shows the exemplary occurrences of timer overflow TFO and
serial recede Re 8051. Figure 3.2(0) instances. Figure 5.2(b) shows exemplary occurrences of
repeated serial receive RI interrupts from the serial bits arriving at the RxD. Figure 5.2 (c)
exemplary occurrences of repeated INTO Inputs, the example, when counting the number of
rotations of a wheel. Identification of flag settings are also shown in these figures.
Address of Interrupt Service Routine (ISR)
A call is then to be the Consider that a CPU has been enabled to respond to an interrupt from
on interrupt to a service routine, ISR. Let the first instruction address of the ISR be ISR
ADDR to a service at the ISR_ADDR? That is, how is step 3 of the four steps pointed out
does the CPU find the diversion to the ISR? Table 5.1 gives three [Link] direct address
access forpain interrupt, vector address method for the ISR address for an interrupt source of
source group for an interrupt, or SR pointer method for obtaining the ISR address pointer for
an interrupt sour source group. Figures 5.3(a), (b), and (c) show the steps in three methods.
Advantages of Vector Addressing
The vector address of the multiple interrupts can separate by eight bytes or more. The eight
bytes can suffice for a short ISR piece multiple interruptsple, when the successive characters
of a string are to be sent on the TxD line from SBUF in 8051, the eight-byte space suffices
(Program Example 5.1).
Bestructure generates a vector address for the corresponding source ISR. The ISR can be a
maximum 8 bytes, which can be located at the vector address or from where a call can be
made to the longer piece of codes from there.
Example 5.1 Let RO store 60H and bytes to be sent are previously defined between 60H and
01 RAM in DATA space. Interrupts from SI have to be enabled by setting EA (IE.7) =1 and
ES (IE.4)=1 Write the ISR code for sending a string of 96 bytes on TxD from the 96
addresses between 60H to 018 Default RO address OOH is used
INTERRUPT LATENCY AND INTERRUPT DEADLINE
Interrupt latency can be defined as the interval between the interrupt event and the
start of the interrupt service for that event. For example, if a timer has overflowed at an
instance to and its service routine initiates at time t1, then latency interval for it equals That =
(t1t0) (Sections 5.6 and 6.3.1 for further description). Let timer overflow interrupt be serviced
latest by t2, then the deadline Td = (t2-10). When the repeated serial buffer interrupts (Figure
5.2(b)) are occurring at every (11/9600) second, the T= (11/9600) second. Therefore, the
latency for the serial port SI interrupt should be less than (11/ 9600) second. Ta<T is the
requirement and priority assignments has to be according to this otherwise, else a service to
an event is missed.
MULTIPLE SOURCES OF THE INTERRUPTS
An MCU has a number of devices and a device may have multiple functions. There
are thus, multi sources of the interrupts to a program being executed by the CPU of an MCU.
Figure 3.20 showed t multiple sources of the interrupt. For example, refer timer T1interrupt
and SI (Serial Port Interface) 8051 interrupt source.
A source can be internal or external. For example, INTO is an external interrupt and
TO overflow and demands a temporary control from the presently executed program to an
ISR The internal sources differ in different CPUs or microcontrollers. Ways of external
sources interrupt could also differ.
Hardware interrupts related to the internal devices
(1) An MCU has the interrupts from the internal timer overflows (timeouts):
(2) An MCU can have the input capture interrupt(s) (8052 and 68HC11/12.): (Section
14.5.2). Th input capture interrupt occurs when the timer count at that instance is captured in
a register whe an input or an event occurs. (Section 6.2.2)
(3) An MCU can have the out compare interrupt(s) (68HC11/12) (Section 14.5.3).
Out-compar interrupt occurs when the timer count at that instance equals to a preset time in a
compare register (Section 6.2.1)
(4) An MCU can interrupt on (i) end of a serial transmission of a character (serial
transmitter-buffe empty) and (ii) end of the serial reception of a charact (serial receive buffer
full) (Examples 8051, 68HC11/12, and 80196).
(5) An MCU (Example 80196) can also interrupt when a serial receive buffer (eight
bytes FIFO) in half-full or full.
(6) An MCU can interrupt on (i) start of analog to digital conversion and (ii) at the
end of the conversion. (Section 14.6 for details and example)
NON-MASKABLE INTERRUPT SOURCES
Certain interrupt sources cannot be masked (disabled from execution of the
corresponding ISR) and these must be serviced. (8051 has all interrupts maskable.)
80x86 An example, NMI pin interrupt in 80x86. It usually connects to
DRAM parity error detection circuit. A few of exceptions (traps) also need
to be always serviced
68HC11/12 Clock monitor failure. The clock slow down must interrupt and execute
the (a), Clock instructions. (b) Unimplemented instructio trap. (c) External
XIRO pin interrupt when declared as non-maskable within 64 clock cycles
after proces sor reset.
ENABLING (UN-MASKING) OR DISABLING OF THE SOURCES
There are number of devices and therefore multiple sources of interrupts. Figure 3.20 showed
different maskable interrupts in 8051 and Table 3.19 the interrupt enabling-disabling bits,
IE.0 to E1 for these. A MCU-based system may require the following during the execution of
a foreground program or routine:
1. Disable all interrupt sources to the running program. An example is the bits at the IE Table
3.19. Clearing IE.7 bit to 0 disables all interrupt-event responses by the interrupt structu of
8051. IE.7 is thus also called primary level enable bit.
2. Enable interrupt structure responses but masks certain specific source(s) or source
group(s). Fr example, IE.6-IE.0 bits at the IE register in Table 3.19 do this. Setting IE.7 to 1,
enables interrupt-event responses by the interrupt structure of 8051 and clearing IE.4= 0
masks the seni port interface interrupts. IE.4 is called SI mask bit or secondary level enable
bit.
There are certain interrupts that can be masked, so those certain events do not respond by the
interrupt-handling structure. All maskable interrupt sources can also be masked by a single
enabling disabling bit. This helps in execution of a current task service in the critical regions.
Therefore, all tr interrupts can be simultaneously disabled at the primary level at the CPU.
For example, by IE.7 EAM in 8051. By appropriate instructions in the user software, a write
to primary level enables and secondary level mask bits, either all or a part of the total
maskable interrupt sources can be disabled in the interrupt structure
POLLING TO DETERMINE THE INTERRUPT SOURCES AND ASSIGNMENT OF
THE PRIORITIES AMONG THEM
Section 5.1.3 showed that each occurrence event is identifiable from a bit or bits in the status
regis and/or in the interrupt-pending register. However, several interrupt events can occur in
quick successi before an interrupt is serviced by the ISR. There are the following
possibilities:
i. Several interrupts occurring at the same time during the execution of a set of instructions a
either all or a few of these are to be serviced in a certain order of priority.
ii. A program is under execution and an interrupt occurs which happens to be a critical ISR,
whic should be executed on priority.
iii. An interrupt is under servicing by a temporary diversion to an ISR, and at that instant,
anothe interrupt occurs which should also be serviced as per precedence assigned. Two
possibilitie exist either the second is serviced only after the completion of the ISR in service
of the fin interrupt or the second interrupt is to be serviced immediately, giving it precedence
over the first Let an MCU interrupt structure have the following features:
Each of the multiple-interrupt sources (including traps or exceptions) has a default assigned
priority on MCU reset. (8051 has default priorities assigned for the seven or nine sources
called source groups 8096 default priorities divides into eight maskable interrupt source
groups. 80960 has default priorities assigned between 8 and 255 for its 248 sources of
interrupt.