INSTRUCTION CYCLE:- The Instruc on Cycle is the process followed by a

computer to execute an instruc on. It consists of a sequence of steps carried

out by the CPU to fetch, decode, and execute an instruc on from memory.
Below is a detailed explana on:Phases of the Instruc on [Link]
Cycle:The CPU retrieves the instruc on from [Link]:The Program
Counter (PC) holds the memory address of the next instruc [Link] address in
the PC is sent to memory via the address [Link] instruc on is read from
memory into the Instruc on Register (IR) via the data [Link] PC is
incremented to point to the next instruc on in sequence.
[Link] Cycle:The CPU interprets the fetched instruc on to understand what
opera on to [Link]:The instruc on in the IR is divided into opcode
(opera on code) and [Link] opcode specifies the opera on, and the
operands indicate the data or address for the opera [Link] control unit
interprets the opcode and generates the necessary control signals.
[Link] Cycle:The CPU performs the opera on specified by the
instruc [Link]:The control signals generated during decoding direct the
execu [Link] arithme c or logical opera ons, the ALU (Arithme c Logic Unit)
processes the [Link] memory or I/O opera ons, the required data transfer
[Link] Back Cycle (if applicable):The result of the executed opera on
is stored back into a register or memory loca [Link]:The result is sent to the
specified des na on (e.g., accumulator or memory).Flags or status bits may be
updated based on the opera on's outcome.
Addi onal Steps (For Interrupts or Branches) Interrupt Handling:If an
interrupt is detected, the CPU suspends the current instruc on cycle, saves the
context, and jumps to the interrupt service rou [Link] Instruc ons:For
condi onal or uncondi onal branches, the PC is updated with the target
address, altering the sequence of execu on.
Fetch → Decode → Execute → Write Back

A program interrupt is a signal generated by either hardware or so ware that

temporarily halts the execu on of the current program and transfers control
to an Interrupt Service Rou ne (ISR). A er handling the interrupt, the system
resumes the interrupted program.
Explana on of Interrupt Handling in a Computer:-When a computer system
handles interrupts, it follows a systema c approach to ensure efficient
execu on. Below is the process, accompanied by a flowchart descrip on:Steps
for Handling Interrupts:Interrupt Request: A hardware or so ware interrupt is
[Link] Current State: The current state of the CPU (Program Counter,
registers, etc.) is saved to allow resump on a er the interrupt is
[Link] fy Interrupt: The type or source of the interrupt is determined
(via the Interrupt Vector Table or polling mechanism).
Execute Interrupt Service Rou ne (ISR):The appropriate Interrupt Service
Rou ne (ISR) is executed to handle the [Link] rou ne is specific to the
type of interrupt (e.g., I/O opera on, mer interrupt).Restore CPU State: A er
the ISR execu on, the saved state is [Link] Program Execu on: The
interrupted program resumes execu on from where it was paused.
Flowchart for Interrupt HandlingBelow is the step-by-step descrip on of the
flowchart:[Link]: Normal program execu on is [Link] Trigger:
Check if an interrupt request (IRQ) has [Link]: Proceed to save the
current CPU [Link]: Con nue normal execu [Link] CPU State: Store the
Program Counter and other relevant [Link] fy Interrupt: Determine
the source/type of the [Link] ISR: Call the appropriate Interrupt
Service Rou [Link] CPU State: Reload the saved CPU state to ensure a
seamless con nua [Link] Execu on: Return to the previously running
[Link]: Normal execu on resumes unless another interrupt occurs
Hardwired Control Unit:- Hardwired control unit generates the control signals
needed for the processor using logic circuits. Hardwired control unit is faster
when compared to microprogrammed control unit as the required control
signals are generated with the help of hardwares. Difficult to modify as the
control signals that need to be generated are hard wired More costlier as
everything has to be realized in terms of [Link] cannot handle complex
instruc ons as the circuit design for it becomes complex. Only limited number
of instruc ons are used due to the hardware implementa on Used in
computer that makes use of Reduced Instruc on Set Computers(RISC)
Microprogrammed Control Unit :-Microprogrammed control unit generates
the control signals with the help of micro instruc ons stored in control
memory. This is slower than the other as micro instruc ons are used for
genera ng signals here Easy to modify as the modifica on need to be done
only at the instruc on level Less costlier than hardwired control as only micro
instruc ons are used for genera ng control signals It can handle complex
instruc ons Control signals for many instruc ons can be generated Used in
computer that makes use of Complex Instruc on Set Computers(CISC

Common Bus Architecture:-A common bus is a system where mul ple

func onal units share a single data path for communica on, reducing
complexity and hardware requirements. It consists of three main
components:[Link] Bus – Carries control signals (Read, Write, etc.).[Link]
Bus – Transfers actual data between [Link] Bus – Carries
memory addresses for data access.
Working of Common Bus Architecture:Memory or registers send data through
the data [Link] control unit decides opera ons using the control [Link]
address bus selects the memory or register loca on for data [Link] ALU
(Arithme c Logic Unit) processes data from registers via the bus.
Various Computer Registers:-

Memory Address Register -Holds the memory address of data or instruc ons
(MAR) to be fetched.

Memory Data Register Holds the actual data being transferred between
(MDR) memory and CPU.

Program Counter Stores the address of the next instruc on to be

(PC) executed.

Instruc on Register (IR) Holds the current instruc on being executed.

Accumulator (A or AC) Stores intermediate results of calcula ons.

General-Purpose Registers (R1, Used for temporary data storage during

R2, ...) execu on.

Stack Pointer (SP) Points to the top of the stack in memory.

Flag
Stores condi on flags (Zero, Carry, Sign, etc.) used for decision-
Registe
making.
r (FR)
The interrupt cycle is a hardware implementa on of a branch and save return
address opera [Link] return address available in PC is stored in a specific
loca on. This loca on may be a processor register, a memory stack, or a
specific memory loca on.

Microinstruc on Format:-A microinstruc on is the smallest unit of control

informa on in a microprogrammed control unit. It contains control signals that
direct the internal opera ons of the processor.
Structure of a Microinstruc on:Control Field – Specifies control signals for
ALU, registers, memory, [Link] Field – Specifies the next microinstruc on
address for [Link] on Field – Specifies condi onal branching based
on status flags.
2. Microprogram Sequencer:-A microprogram sequencer is a hardware unit
responsible for fetching, decoding, and execu ng microinstruc ons in the
correct [Link] ons of a Microprogram Sequencer:-Fetch the next
microinstruc on from the control [Link] the next address based
on condi ons and branching [Link] control signals for the execu on
of microinstruc [Link] jumps and condi onal branches in microprogram
execu on.
What is Pipelining?Pipelining is a technique used in computer architecture to
improve instruc on execu on speed by dividing a process into mul ple
stages, where different stages execute in parallel. This increases the
throughput (number of instruc ons executed per unit me).
Two Types of Pipeline Organiza ons:-[Link] c Pipeline:-Used for
execu ng complex arithme c opera ons (e.g., floa ng-point
opera ons).Breaks opera ons into sub-steps that execute in
[Link]: Floa ng-point mul plica on in supercomputers.
[Link] on Pipeline:-Used in CPU instruc on execu on, where mul ple
instruc ons are processed simultaneously in different [Link]: Fetch-
Decode-Execute cycle in RISC processors like ARM and MIPS.

Instruc on Pipeline:-An instruc on pipeline breaks down instruc on

execu on into mul ple stages, allowing mul ple instruc ons to be executed
at different stages [Link] of Instruc on Pipeline:
A typical 5-stage pipeline consists of:[Link] on Fetch (IF) – Fetches the
instruc on from [Link] on Decode (ID) – Decodes the fetched
instruc [Link] Fetch (OF) – Retrieves the required operands from
registers or [Link] on (EX) – Performs the opera on using the
[Link] Back (WB) – Stores the result in the des na on register.
Array processors are also known as mul processors or vector processors.
They performcomputa ons on large arrays of data. Thus, they are used to
improve the performance of thecomputer.
Types of Array Processors:There are basically two types of array processors:
1. A ached Array Processors2. SIMD Array Processors
A ached Array Processors:-An a ached array processor is a processor which
is a ached to a general purpose computer and its purpose is to enhance and
improve the performance of that computer in numerical computa onal tasks.
It achieves high performance by means of paralel processing with mul ple
func onal units.
[Link] Array Processors:-SIMD is the organiza on of a single computer
containing mul ple processors opera ng in parallel. The processing units are
made to operate under the control of a common control unit,thus providing a
single instruc on stream and mul ple data streams.
A general block diagram of an array processor is shown below. It contains a
set of iden calprocessing elements (PE's), each of which is having a local
memory M. Each processor element includes an ALU and registers. The
master control unit controls all the opera ons of the processor elements. It
also decodes the instruc ons and determines how the instruc on is to be
executed .The main memory is used for storing the program. The control unit
is responsible for fetching theinstruc ons. Vector instruc ons are send to all
PE's simultaneously and results are returned to the memory.
The best known SIMD array processor is the ILLIAC IV computer developed by
the Burroughs corps. SIMD processors are highly specialized computers. They
are only suitable for numerical problems that can be expressed in vector or
matrix form and they are not suitable for other types of computa ons.

RISC (Reduced Instruc on Set CISC (Complex Instruc on Set

Aspect
Compu ng) Compu ng)

Instruc on Small, simple, and highly Large, complex set of instruc ons
Set op mized set of instruc ons. with mul ple addressing modes.

Instruc on Fixed-length instruc ons (usually Variable-length

Format 4 bytes). instruc ons.

Number of Few instruc ons, each Many instruc ons with

Instruc ons performing a simple opera on. complex opera ons.
Execu on Most instruc ons take one Instruc ons may take mul ple
Time clock cycle to execute. clock cycles to execute.

Memory Load and store opera ons Can perform memory access directly
Access are separate. within instruc ons.

Design Emphasizes simplicity and Emphasizes versa lity and

Philosophy speed. flexibility.

Uses a large number of registers Uses fewer registers, relies more

Registers
to hold operands. on memory access.

Examples ARM, MIPS, SPARC Intel x86, IBM 360, VAX

Highly op mized for pipelining More difficult to pipeline due to

Pipelining
due to simple instruc ons. complex instruc ons.

Control Unit Simpler control unit due to More complex control unit to
Complexity fewer instruc on types. handle diverse instruc ons.

Higher performance for simple Be er performance for

Performance
tasks due to faster execu on. complex tasks with less code.

An instruc on format defines the structure of a machine language instruc on

in a processor's memory. It specifies how the bits in an instruc on are
organized to represent various components like opera on codes (opcode),
operands, and addressing modes. The instruc on format plays a cri cal role in
how the CPU fetches, decodes, and executes instruc ons
Key Components of Instruc on Format:[Link] (Opera on Code):Specifies
the opera on to be performed (e.g., ADD, SUB, LOAD).Typically, the first part of
the instruc [Link]:Specifies the data or memory loca ons on which
the opera on will [Link] be registers, memory addresses, or immediate
[Link] Mode:Defines how to access the operands (e.g., direct,
indirect, register, or immediate addressing).[Link] Field:Specifies the
registers involved in the opera on, e.g., source or des na on
[Link] Bits (Flags):Used to specify specific condi ons, such as
whether an opera on is condi onal or if flags need to be set.
Parallel processing refers to the technique of using mul ple processors or
processing units simultaneously to execute mul ple instruc ons or tasks. The
goal is to improve computa onal speed by dividing a large task into smaller
sub-tasks and processing them [Link] processing is commonly
used in mul -core processors and distributed systems to solve complex
problems faster and more efficiently.
Types of Parallel Processing:Bit-level parallelism: Executes mul ple bit
opera ons [Link] on-level parallelism (ILP): Executes
mul ple instruc ons [Link]-level parallelism (DLP): Processes
mul ple data elements [Link]-level parallelism: Involves the
parallel execu on of independent tasks or processes.

Four Segments of Pipelining:[Link] (IF - Instruc on Fetch):The instruc on is

fetched from [Link] on: The program counter (PC) points to the
instruc on in memory, which is then fetched and loaded into the instruc on
[Link] (ID - Instruc on Decode):The fetched instruc on is decoded
to understand what opera on is [Link] on: The control unit
decodes the instruc on and determines which operands (e.g., registers or
memory loca ons) are involved in the opera on. The instruc on is parsed,
and the necessary signals are generated for execu [Link] (EX -
Execu on):The arithme c or logic opera on is [Link] on: The
Arithme c Logic Unit (ALU) performs the required opera on (e.g., addi on,
subtrac on, etc.), or it calculates the memory address if the instruc on
involves memory [Link] Back (WB - Write Back):The result of the
opera on is wri en back to the des na on register or [Link] on:
The result from the execu on stage is wri en to the appropriate register or
memory loca on.
Flynn’s Taxonomy :-Flynn’s Taxonomy is a classifica on system introduced by
Michael J. Flynn in 1966 to categorize computer architectures based on the
number of instruc on streams and data streams they can handle
simultaneously.4 category:-1. SISD (Single Instruc on, Single Data):Defini on:
Executes one instruc on at a me on a single data [Link]: Tradi onal
CPUs (Intel 8085, Intel Pen um 4).Use Case: Simple sequen al processing.
2. SIMD (Single Instruc on, Mul ple Data):Defini on: Executes the same
instruc on on mul ple data elements [Link]: Vector
processors, GPUs (NVIDIA CUDA, Intel AVX).Use Case: Image processing,
deeplearning, scien fic simula ons.3. MISD (Mul ple Instruc on, Single
Data)Defini on: Mul ple processors execute different instruc ons on the
same data [Link]: Used in specialized fault-tolerant systems (e.g.,
NASA space shu le computers).Use Case: Data encryp on, fault-tolerant
compu ng.
4. MIMD (Mul ple Instruc on, Mul ple Data):-Defini on: Mul ple processors
execute different instruc ons on different data [Link]:
Mul -core processors, supercomputers (Intel Core i9, IBM Blue Gene).Use
Case: Cloud compu ng, distributed systems, AI workloads.
Addressing Modes in Computer Architecture:-Addressing modes define how
an instruc on iden fies the operands (data) needed for execu on. They
allow flexibility in accessing data stored in registers or memory.
Types of Addressing Modes with Examples:1. Immediate Addressing
Mode;Defini on: The operand (data) is directly specified in the
instruc [Link] (Assembly Code):
MOV R1, #10 ; Load immediate value 10 into register R1
Use Case: When a constant value is needed.
2. Register Addressing ModeDefini on: The operand is located in a register.
Example:MOV R1, R2 ; Copy the value from register R2 to register R1
Use Case: Fast data access, efficient for arithme c opera ons.
3. Direct Addressing Mode;Defini on: The instruc on contains the memory
address of the operand.
Example:MOV R1, 5000H ; Load the value from memory address 5000H into
R1
Use Case: Accessing variables stored in fixed memory loca ons.
4. Indirect Addressing Mode;Defini on: The address of the operand is stored
in a register or memory loca on.
Example:MOV R1, (R2) ; Load value from the memory loca on pointed by R2
into R1
Use Case: Accessing dynamically allocated data structures.
5. Indexed Addressing Mode;Defini on: The effec ve address of the operand
is calculated by adding an index to a base address.
Example:MOV R1, ARRAY[R2] ; Load value from ARRAY base address + index
stored in R2
Use Case: Used in array processing.
6. Base Register Addressing Mode;Defini on: The effec ve address is
obtained by adding a base register value to a displacement.
Example:MOV R1, (Base + Offset) ; Load from address (Base + Offset) into R1
Use Case: Used in dynamic memory alloca on and posi on-independent
code.
7. Rela ve Addressing Mode;Defini on: The effec ve address is computed by
adding the instruc on counter (PC) to an offset.
Example:JMP LABEL ; Jump to an address rela ve to the current instruc on
Use Case: Used in branching and looping instruc ons.
8. Stack Addressing Mode;Defini on: Operands are implicitly stored in a stack
and accessed using push/pop opera ons.
Example:PUSH R1 ; Push register R1 onto the stack
POP R2 ; Pop the top value from the stack into R2
Use Case: Used in func on calls, recursion, and expression evalua on.
[Link]-Index Increment Addressing Mode:Defini on:The index register is
automa cally incremented a er accessing the [Link] simplifies accessing
sequen al memory loca ons, like itera ng through an array.
Example:-LDR R1, [R2], #4 ; Load value from memory at address R2 into R1,
then increment R2 by 4
[Link]-Index Decrement Addressing Mode:Defini on:The index register is
automa cally decremented a er accessing the [Link] in stack-based
opera ons and reverse itera on.
Example (Assembly Code):STR R1, [R2, #-4]! ; Store R1 into memory at (R2 -
4), then update R2 = R2 – 4
Register Stack:A register stack is a small, high-speed set of registers used to
store temporary values such as func on return addresses, local variables, and
intermediate computa ons.
Characteris cs:Uses CPU registers instead of [Link] in size (depends
on the number of available registers).Faster access compared to memory
[Link] memory read/write overhead.
PUSH R1 ; Push R1 onto the register stack
POP R2 ; Pop the top value from the register stack into R2
Memory Stack:-A memory stack is a region in RAM used to store func on
parameters, return addresses, and local variables. It is managed using a stack
pointer (SP) [Link] cs:Uses main memory (RAM) to store stack
[Link] store a large amount of data compared to register [Link]
access due to memory read/write opera [Link] for func on calls,
recursion, and local variables.
Parallel Processing:-Parallel processing is a compu ng technique where
mul ple processors (or cores) execute mul ple tasks simultaneously to
improve performance and efficiency. It is widely used in supercomputers,
mul -core processors, and distributed compu ng systems.
Types of Parallel Processing:
1. Bit-Level Parallelism:- Mul ple bits of data are processed simultaneously
within a single [Link]: 64-bit processors can process 64-bit data at
once, whereas 32-bit processors handle only 32-bit data per cycle.
2. Instruc on-Level Parallelism (ILP): Mul ple instruc ons are executed
simultaneously within a single [Link]: Pipelining, superscalar
execu on.
3. Data Parallelism: The same opera on is performed on mul ple data
elements at the same [Link]: Vector processors, SIMD (Single
Instruc on Mul ple Data)
4. Task Parallelism: Different tasks are executed in parallel on mul ple
[Link]: MIMD (Mul ple Instruc on, Mul ple Data) systems.
four Segments of Pipelining in Parallel Processing:-Pipelining is a key
technique in parallel processing, where an instruc on is broken into mul ple
stages, and different stages execute simultaneously.
Stages of an Instruc on Pipeline:[Link] (IF – Instruc on Fetch): The
instruc on is fetched from [Link] (ID – Instruc on Decode): The
instruc on is decoded, and operands are iden fi[Link] (EX –
Execu on): The instruc on is processed by the ALU or logic [Link] Back
(WB – Write Back): The result is stored in a register or memory.