지능형 반도체공학

Intelligent Semiconductor Engineering

Lecture 3. CMOS Fabrication, Floorplanning &

Implementation Styles

Jaeeun Jang
KwangWoon University
School of Semiconductor Systems Engineering
Layout
▪ Describes actual layers and geometry on the silicon substrate
to implement a function

▪ Need to define transistors, interconnection

▪ Transistor widths (for performance)
▪ Spacing, interconnect widths, to reduce defects, satisfy power
requirements
▪ Contacts (between poly or active and metal), and vias (between
metal layers)
▪ Wells and their contacts (to power or ground)

▪ Layout of lower-level cells constrained by higher-

level requirements: “floorplanning”
Layout (Cont.)
▪ Chips are specified with set of masks
▪ Minimum dimensions of masks determine transistor size
(and hence speed, cost, and power)
▪ Feature size f = distance between source and drain
▪ Set by minimum width of polysilicon
▪ Feature size improves 30% every 3 years or so
▪ Normalize for feature size when describing design rules
▪ Express rules in terms of  = f/2
▪ E.g.  = 0.3 m in 0.6 m process
CMOS Inverter Layout

Note: the N- and P- wells

are not shown here

V DD

Input Output

V SS
Another CMOS Inverter Layout
CMOS Inverter with Wider Transistors
Buffer with Two Inverters
Buffer with Stacked Inverters
Efficient Buffer with Stacked Inverters
Simplified Layout of NAND Gate
“Stick” Diagram for NAND Gate
▪ Identifies actual layers, can be annotated with transistor
sizes
Simplified Design Rules
▪ Conservative rules to get you started
Inverter Layout
▪ Transistor dimensions specified as Width / Length
▪ Minimum size 4 / 2 sometimes called 1 unit or standard
pitch
▪ In f = 0.6 m process, this is 1.2 m wide, 0.6 m long
Typical Layout Densities
▪ Typical numbers of high-quality layout
▪ Derate by 2 for class projects to allow routing and some
sloppy layout.
▪ Allocate space for big wiring channels

Element Area
Random logic (2 metal layers) 1000-1500 2 / transistor
Datapath 250 – 750 2 / transistor
Or 6 WL + 360 2 / transistor
SRAM 1000 2 / bit
DRAM 100 2 / bit
ROM 100 2 / bit
Area Calculation Example: NAND3
▪ Horizontal N-diffusion and p-diffusion strips
▪ Vertical polysilicon gates
▪ Metal1 VDD rail at top
▪ Metal1 GND rail at bottom
▪ 32  by 40 
Cell Flipping
▪ Flip every other cell
▪ Cells share VDD & GND
▪ Cells share N-WELL and
substrate connections
▪ Reduces cell height
▪ Measure contact center to
contact center
Wiring Tracks
▪ A wiring track is the space required for a wire
▪ 4  width, 4  spacing from neighbor = 8  pitch
▪ Transistors also consume one wiring track
Well spacing
▪ Wells must surround transistors by 6 
▪ Implies 12  between opposite transistor flavors
▪ Leaves room for one wire track
Area Estimation
▪ Estimate area by counting wiring tracks
▪ Multiply by 8 to express in 
Example: O3AI
▪ Sketch a stick diagram for O3AI and estimate area

Y = (A + B + C) * D
Example: O3AI
▪ Sketch a stick diagram for O3AI and estimate area

Y = (A + B + C) * D
Example: O3AI
▪ Sketch a stick diagram for O3AI and estimate area

Y = (A + B + C) * D
Floorplanning
Floorplanning 101
▪ Determine block sizes
▪ Function of SC pitch, Cell Placement,
RLM, SC/SDP, Custom/Memory Block
Sizing and Block Routing Overhead
(Signals, Clocking, Power)
Floorplanning 101
▪ Determine block sizes
▪ Function of SC pitch, Cell Placement, RLM, SC/SDP, Custom/Memory
Block Sizing and Block Routing Overhead (Signals, Clocking, Power)
▪ Determine core size
▪ Function of #Blocks, Block sizes, Block Aspect Ratios, Global
Routing Overhead (Signals, Clocking, Power)
▪ Determine I/O ring size
▪ Function of the number of I/O, Number of Power Pins and Placement
Floorplanning
▪ How do you estimate block areas?
▪ Begin with block diagram
▪ Each block has
▪ Inputs
▪ Outputs
▪ Function (draw schematic)
▪ Type: array, datapath, random logic
▪ Estimation depends on type of logic
▪ RLM: Random Logic Macro
▪ Datapath
▪ Array
Area Estimation
▪ Arrays:
▪ Layout basic cell
▪ Calculate core area from # of cells
▪ Allow area for decoders, column circuitry
▪ Datapaths
▪ Sketch slice plan
▪ Count area of cells from cell library
▪ Ensure wiring is possible
▪ Random logic
▪ Compare complexity do a design you have
done
Metal Planning
▪ Metal layer, width, spacing and shielding are negotiable
▪ “Negotiable” means you have to plead your case to the integration leader
▪ All of these impose a physical constraint for layout
▪ Typical 8 layer metal layer allocation
▪ M1,M2 : Local routing (standard cell)
▪ M3,M4, M5, M6 : Data and control
▪ M7,M8 : Power, Ground, Clock, Reset, etc
▪ Assume HVH routing:
▪ Metal-1: Horizontal
▪ Metal-2: Vertical
▪ Metal-3: Horizontal
▪ Metal-4: Vertical
▪ …..

▪ Use standard 'HALO' cells to make the resulting 'floor-plannable'

objects 'snap' to the desired power and routing grids.
▪ Added to the boundary of all custom layouts (as well as synthesized blocks).
Chip & Block Level Clock Routing
▪ Watch out for the clock, it’s your most critical net
▪ Make sure the physical design treats it accordingly
▪ Help reduce clock power by eliminating unnecessary load
▪ Make sure the clock net has enough via coverage
▪ Use a combination of Global (Chip) and Block Level Clock
distribution
Chip level power routing
▪ Power busses are a combination of
rings and/or grids.
▪ Rings are generally in the I/O ring.
▪ Grids are used at the chip and block level
▪ Grid pitch is set by horizontal and vertical
▪ routing resource requirements

▪ Special consideration needs to be

taken for multiple power domains.
▪ There can be any number of power domains
▪ depending on the system architecture
▪ Analog blocks require isolation rings
▪ Interfaces between blocks require
level shifters
Eye candy: Floorplan examples
Apple A8 SOC (for iPhone)
Apple A8X SOC (for iPAD)
Flip chip power mesh for AMD Jaguar
Analog Devices LNA
Implementation Techniques
Implementation Choices

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGA's)
Path from RTL to structural netlist
The Custom Approach

Intel 4004

Courtesy Intel
Transition to Automation and Regular Structures

Intel 4004 ( ' 71)

Intel 8080 Intel 8085

Intel 8286
Courtesy Intel Intel 8486
Cell-based Design (or standard cells)

Routing channel
requirements are
reduced by presence
of more interconnect
layers
Standard Cell — Example

[Brodersen92]
Standard Cell – The New Generation

Cell-structure
hidden under
interconnect layers
Standard Cell - Example

3-input NAND cell

(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time
Automatic Cell Generation

Initial transistor Placed Routed Compacted Finished

geometries transistors cell cell cell

Courtesy Cadabra
MacroModules

25632 (or 8192 bit) SRAM

Generated by hard-macro module generator
“Soft” MacroModules
“Intellectual Property” (IP) Cores

A Protocol Processor for Wireless

Semicustom Design Flow

Design Capture Behavioral

HDL
Pre-Layout
Simulation Structural
Logic Synthesis
Design Iteration

Floorplanning
Post-Layout
Simulation Placement Physical

Circuit Extraction Routing

Tape-out
The “Design Closure” Problem

Iterative Removal of Timing Violations (white lines)

Courtesy Synopsys
Integrating Synthesis with Physical Design

RTL (Timing) Constraints

Physical Synthesis

Macromodules Netlist with

Fixed netlists Place-and-Route Info

Place-and-Route
Optimization

Artwork
Late-Binding Implementation
Gate Array — Sea-of-gates

polysilicon

VDD

metal
rows of Uncommited
uncommitted possible
cells GND contact Cell

In 1 In 2 In 3 In4

routing
channel Committed
Cell
(4-input NOR)
Out
Sea-of-gates

Random Logic

Memory
Subsystem

LSI Logic LEA300K

(0.6 m CMOS)

Courtesy LSI Logic

Prewired Arrays
▪ Classification of prewired arrays (or field-programmable
devices):
▪ Based on Programming Technique
▪ Fuse-based (program-once)
▪ Non-volatile EPROM based
▪ RAM based
▪ Programmable Logic Style
▪ Array-Based
▪ Look-up Table
▪ Programmable Interconnect Style
▪ Channel-routing
▪ Mesh networks