ECE 6130: ADVANCED VLSI DESIGN

Chapter # 3
Physical Structure of CMOS Integrated Circuits

Shafaat Ahmed Bazaz (Ph.D France)

Professor
Beaconhouse National University, Lahore
Pakistan
Lecture # 2

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3.1 Integrated Circuit Layers
Material layers in CMOS: Stacking of layers in specific order
(Metal, Insulator, Silicon)

Layers after the stacking process is completed

(a) Side view (b) Top view

Insulating layers is SiO2

generally known as
Quartz Glass
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3.1 Integrated Circuit Layers
Addition of another insulator and a second metal layer

Chemical-Mechanical Polishing

(a) Side view (b) Top view

• Side view illustrates the order of stacking. Stacking order cannot be changed by
the VLSI designer
• Insulating layers separate two metal layers for electrical isolation
• Top view shows the patterning (shape) of each layer 3
3.2 Interconnect Resistance and Capacitance

Interconnect lines: connecting two or more transistors 4

3.2 Interconnect Resistance and Capacitance

Symbol for a Linear Resistor

Relationship between Boolean and Electrical Variables

• Boolean variable a, Voltage (Va), and Current (Ia)
• Parasitic resistance Rlineto be kept as small as possible
Geometry of a conducting Line

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3.2 Interconnect Resistance and Capacitance
Parasitic/Line resistance Rline

Resistivity

VLSI designer cannot change the value of t and σ. Why??

Design Rules

Sheet Resistance (ohms)

• It can be determined experimentally

• for l=w, for a square region
• Units of Sheet Resistance Ohm per Square
6
• used to calculate the line resistance
3.2 Interconnect Resistance and Capacitance
Parasitic/Line resistance Rline

(a) Top view geometry

Where

(b) Sheet resistance contribution

• n can be in fraction as well

• Line resistance should be small possible
• Smaller the line resistance allows high level of current flow. Thus speed of signal
goes high

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3.2 Interconnect Resistance and Capacitance
Parasitic/Line Capacitance Cline

(a) Physical Structure

Circuit symbol for a

capacitor

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3.2 Interconnect Resistance and Capacitance
Parasitic/Line Capacitance Cline Time constant

(a) Physical Structure General Equation

dx
(t ) + ax(t ) = A
1 V dt
a= , A= S
RS C RS C
t
−
1 v(t ) = K1 + K 2 e 
 = = RS C
a Time delay due to interconnect time
constant

Line resistance and Line Capacitances

must be kept as small as possible during
the design process

(b) Circuit model

3.2 MOSFETs at Physical Level
nFET circuit symbol and layers equivalent

(a) nFET symbol

(b) nFET Physical layers
• Gate acts as control voltage Operational Characteristics of Physical Structure
terminal, determines whether the
switch is OPEN or CLOSE
• Voltage applied on gate determines
the flow of current between Source
and Drain terminals

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Gate Signal G (VG )is responsible for the absence or presence of
the conducting region between DRAIN and SOURCE
Physical Structure of the Transistor: Exploded View
L=Channel Length (0.18u)
W= Channel Width
W/L= Aspect Ratio

Substrate

Views of a MOSFET Physical Structure

(a) Side view 11

(b) Top view
Physical Structure of the Transistor: Another Side View

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3.2.1 Electrical Conduction in Si
•Atomic Density of Si Crystal = 5  1022 atoms per cm3
• few number of electrons available for conduction due to thermal excitation
• Si is an intrinsic material
• Number of free electrons per cm3 (intrinsic Carrier Density)= ni depends on
temperature. At room temperature:

Mass Action Law

Intrinsic Carrier Density in thermal
equilibrium
• Creation of electron-hole pair in n-type Si: Donors
• Hole represents the absence of Electron and treated as
positive charge

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3.2.1 Electrical Conduction in Si: n-type material
•Dopants to create Doped Sample: Impurities addition to enhance either no of
holes or electrons to aid in the current flow
• Arsenic and Phosphorous are used to enhance no of electrons (n-type
materials with excess no of electrons). Act as donor atoms (donate electrons)

Mass Action Law

in thermal
equilibrium

N d = 1016 to1019 cm − 3
nn is electron density

Electrons are majority

Carriers and holes
are minority carriers

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3.2.1 Electrical Conduction in Si: p-type material
•Dopants to create Doped Sample: Impurities addition to enhance either no of
holes or electrons to aid in the current flow
• Boron is used to enhance no of positively charged holes (p-type materials
with excess no of holes). Since the hole can accept the electrons so act as
Acceptor dopant

• No of acceptors added per

cubic cm is Na
• Acceptor density pp is
same range as that of for
donors (1014 to 1019 cm-3)
•Conductivity in semiconductor with
carrier densities n and p
• μn & μp are electron and hole
mobilities

For n-Type region For p-Type region

Doping level is the most important factor in determining the 15

conductivity in n-type or p-type Silicon
 Home Work
Example 3.1, 3.2, 3.33

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3.2.2 nFETs and pFETs
• polarity of FET (n or p) is determined by the polarity of drain and Source

(a) nFET cross section (b) pFET cross section

• Donor density Nd is large • Source and drain are p-type regions but
(1019 cm-3) embedded in an n-type well layer to avoid
• Substrate layer is p-type with same p-type thus stopping the current
boron atoms doping density leakage into substrate
Na =(1015 cm-3) • Several pn junction formed to prevent the
• pn junction is formed to block flow of current in adjacent layers
the current from entering into •Keep in mind the nFET and pFETs are
substrate fabricated side by side on single wafer
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3.2.3 Current Flow in a FET
A parallel plate capacitor

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3.2.3 Current Flow in a FET

Oxide Capacitance
(F/cm2)
A thin layer of tox<1A0 for Gate Oxide
Gate Capacitance

The gate capacitor in an n-channel

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MOSFET
Eq 3.43

Eq 3.44

Eq 3.45

Eq 3.46

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 Threshold Voltage (VTn)= 0.7V
3.2.3 Current Flow in a FET
Controlling current flow in an
nFET Difference voltage (VG – VTn) shows
that no charge forms until VG
reaches VTn).
Negative sign shows the –ive charge

τt is transient time

(a) Zero gate voltage

Velocity of charge

Electric field
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(b) Positive Gate Voltage
3.2.3 Current Flow in nFET
Controlling current flow in an
nFET

Device tans-
conductance
A/v2
•nFET is open for Rn→ infinity
(a) Zero gate voltage • Acts as close for Rn between source and drain
•μn is the surface mobility different from bulk
mobility (inside the material) discussed earlier

•Simple estimate: μn ½ of the bulk

mobility measured in lab

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(b) Positive Gate Voltage
3.2.3 Current Flow in nFET
•Voltage current relationship is non linear
• For simple modeling, transistor resistance is linearized as:

Sheet
resistance:

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 All same except the polarities are reversed
3.2.3 Current Flow in pFET
Switching behavior of a pFET

(a) High gate voltage

(b) Negative gate voltage

• All modeling relies on the useful visualization of VLSI designer

• Often simple model is useful
• For same resistance for nFET and pFET??? 24
3.2.4 Driving the Gate Capacitance
Voltage and Current in a capacitor

•Voltage does not change instantaneously

•Gate capacitance introduces the signal delay

• Value of capacitance CG determines the amount
of charge necessary to change the voltage
• larger capacitance implies the larger delay

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3.2.4 Driving the Gate Capacitance
Driving the gate of a FET

•Storing energy brings delays in the signal

propagation
• Heat dissipation, temperature rise

• Switching delays are due to the physical characteristics of the devices and
interconnects
– Designer must understand the nature of switching delays for fast digital circuits
–Characteristics of both FET and interconnect effect the system speed
• Every switching event requires energy transfer in the circuit. This implies that power
dissipation will occur within the circuit
–Excessive heat may melt the Silicon and destroy the chip
– proper design of heat sinks
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– For portable devices, power dissipation should be less to extend the life of battery
3.3 CMOS Layers
• CMOS provides the economic basis for a huge segment of the world computing industry
• High density circuits are in demand
•CMOS Fabrication process: Sequence of steps used to take a bare Si Wafer to the finished
form of an electronic integrated structure.

• Layer types
• P-Substrate
Final Structure of MOSFET layers in an n-well process
• N-well
• n+ (nFET drain/source)
• p+ (pFET drain/source)
• Gate Oxide
• Gate (polysilicon)

• Start from p type substrate (wafer) as base layer for building all transistors
• nFET can be fabricated directly in the p-type substrate where as n well regions are
added for pFETs
• Layers (shown in figure) implies a region with distinct electrical characteristics
• Junction between n and p types block current flow thus are electrically isolated
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3.3 CMOS Layers

Top view FET patterning

Gate Oxide, FOX and p-Substrate are not shown explicitly
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3.3 CMOS Layers Adding Metal interconnect layers
Top view FET patterning

•VIA is needed to contact Metal1 with Metal2

Active Contact: To connect Metal1 with

drain/source

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3.3 CMOS Layers
Metal interconnect layers • Metal layers are electrically isolated
from each other and the transistor by
glass
• Electrical contacts between adjacent
conducting layers require that we create
Active/Gate Contact cuts and VIAS in
the oxide layer
• In the layout example, we can cross
the conducting without creating an
electrical connection between them
(Metal2 layer)
• VIA is needed to contact Metal1 with
Metal2
• Gate Contact is used to connect Metal1
and the gate layers
• Active Contact is used to connect
Metal1 to Drain/Source regions

•A CMOS Logic Circuit just consists of

only Transistors and Wires
• We have to learn then how the signal is
transmitted through them
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Interconnect layout example
3.4 Designing FET Arrays •using
Earlier, we learnt how to build logic gates
FETs at Schematic level
• Now, we learn how to pattern this device in
terms of Silicon
•two series-connected nFETs

(a) Schematic
Device can share
patterned region to
reduce layout size

(b) Surface pattern

•No need to make
individual FETs
•Avoid use of Wires

(c) Side view 31

3.4 Designing FET Arrays •representation
Color coding for each layer simplifies the
(Stick diagram)
Three series-connected nFETs • Design and verify the design first and then
start sizing it
• At initial stage of design, the width is not
important rather are interested in signal flow
path and circuit topology

(a) Schematic

Provide electrical
connection to outside
world

(b) Surface pattern

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 •Horizontal Drain-Source
3.4 Designing FET Arrays connection orientation
Parallel connecting FET patterning: Drain and Source
regions are connected with nodels X and Y

(a) Schematic
(b) Transistor pattern and wiring •Vertical Drain-Source
scheme connection orientation
Alternate layout strategy for parallel FETs Layout

(a) Schematic (b) Surface pattern

• Series Drain-Source connection orientation are not mandatory

• Only wiring and resulting connection are important 33
•Separate transistors require more area
3.4.1 Basic Gate Designs
Translating a NOT gate circuit to Si

(a) Circuit (b) Layer patterning

• Patterned lines are conducting lines to steer the

current and establish voltages
• Line widths are not important at this stage; only the
topology of the circuits is needed to trace the logic
•VDD and Gnd are routed using the Metal Layer
• n+ and p+ regions are denoted using same fill
pattern. pFETs are embedded within an n-well
boundary
• Contacts are needed from Metal to n+ or p+ since
they are at different levels in the structure
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 Variation in layout strategies are not
3.4.1 Basic Gate Designs important until the actual sizes of the
Alternate layout for a NOT gate: 2:1 Mux patterns are taken into account

(a) Circuit (a) Circuit

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(b) Layout patterning (b) Layout patterning
3.4.1 Basic Gate Designs
One main goal: Minimize the chip area.
Can be achieved using many techniques
Two NOT gates that share power supply and ground

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3.4.1 Basic Gate Designs
Non-inverting Buffer provides:
• electrical reshaping of the signal
• additional drive strength for large Fan-out

(a) Logic diagram

(b) Layout

Metal-to-poly Contact- Gate

Contact

Metal crossing poly

without contact

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2.5 Transmission Gate Circuits

Transmission Gate (TG)

Connecting nFEt and pFET in
parallel
Bi-directional switch

• Transmits all ranges (0, VDD) of voltages,

makes it attractive for many applications
(ASICs)
• Require two FETs and one inverter circuit
for S (b) Symbol
• TG circuits are found in many ASIC
structures

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3.4.1 Basic Gate Designs
Layout of a TG with a driver: Routing issues

(a) Logic diagram

TG

Issues
• Switching signal must produce S
• NOT gate must be connected to the power supply
and ground
• location of nFET and pFET of the TG is also
important
• Inverter FETs with tall n+ region
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3.4 Designing FET Arrays (Revise Fig 3.27)
Two series-connected nFETs

(a) Schematic
Device can share
patterned region to
reduce layout size

(b) Surface pattern

•No need to make
individual FETs
•Avoid use of Wires

(c) Side view 40

 •Horizontal Drain-Source
3.4 Designing FET Arrays (Revise fig 3.29) connection orientation
Parallel connecting FET patterning: Drain and Source
regions are connected with nodels X and Y

(a) Schematic
(b) Transistor pattern and wiring
scheme

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3.4.1 Basic Gate Designs 2 pFETs
NAND2 Gate Design

(a) Circuit (b) Layer design

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3.4.1 Basic Gate Designs
NOR2 Gate Design

(a) Circuit (b) Layer design

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3.4.1 Basic Gate Designs
NAND2-NOR2 layout comparison

Layout for 2-input gates

Flip the metal line vertically

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NAND2 Gate NOR2 Gate
 NOR2 Gate
3.4.1 Basic Gate Designs
NAND2-NOR2 (CELL) layout comparison:

NAND2 Gate

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NAND3 Gate NOR3 Gate
 •Horizontal Drain-Source
3.4 Designing FET Arrays (Revise fig 3.29) connection orientation
Parallel connecting FET patterning: Drain and Source
regions are connected with nodels X and Y

(a) Schematic
(b) Transistor pattern and wiring
scheme
3.4.2 Complex Logic Gates
Extension of layout technique to a complex logic gate

f = a.(b + c )
_____________
f = a .(b + c )
For pFET Array
For nFET ArrayDeMorgan Law For pFET Array Duality

• Single Poly gate for each input

(a) Circuit • Signal placement order is important
• Flip the metal wiring pattern around imaginary
horizontal line (see next)
3.4.2 Complex Logic Gates
Creation of the dual network

For nFET Array Duality For pFET Array

(a) Pattern

(b) Circuit

• Flip the metal wiring pattern around

imaginary horizontal line
•Not all logic implementations are simple
• Involves trial-and-error sketches
3.4.2 Complex Logic Gates
A general 4-input AOI gate

(a) Circuit
• Share n+ and p+ areas to minimize the size (b) Layout writing
• Use vertical Poly line for each input
• nFET patterning is easy as it requires two
groups in parallel each having 2FETs
• Thick line for metal wiring
3.4.3 General Discussion
General Gate Layout Geometry

• Regular patterns and arrays yield best packing density

• Avoid randomly placed polygons
• Every logic gate requires VDD and ground that runs with horizontal metal lines
• All FETs are placed between two power rails
• Gate line are perpendicular or parallel to power rails
• pFET will be embedded in n-well around VDD rail while nFETs are closer to Gnd rail
• Stick diagrams: each layer is represented by color and the routing consists of colored
lines
3.4.3 General Discussion
Basic stick layout diagram: Perform quick layout or study large complex routing diagrams

Placement of a FETs using graph theory

3.4.3 General Discussion
Construction of a Euler graph
(b) Euler graph

(a) Circuit with path

Layout using an Euler graph

3.4.4 Summary

• More graphics and art work required for VLSI designer (good to be
member of ARTS Society)
• Not only functional circuit but also a FAST circuit is required
– control parasitic resistance and capacitance
• What are the effect of fabrication process on the electrical
performance of the circuit